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Working dwell time feature

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- Bugfixes:
	- improve SPI timing in FPGA
	- fix markers and reduce CPU load when using markers with fast traces
- New features:
	- dwell time configurable in acquisition toolbar
	- PLL settling delay in device configuration
	- device configuration persistent across power cycles
This commit is contained in:
Jan Käberich 2025-01-03 14:36:10 +01:00
parent 24314e2361
commit a4faeb28b0
35 changed files with 516 additions and 289 deletions
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Software/PC_Application/LibreVNA-GUI/Device/devicedriver.cpp
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@ -118,7 +118,6 @@ DeviceDriver::Info::Info()
Limits.VNA.minIFBW = 1;
Limits.VNA.maxIFBW = 100000000;
Limits.VNA.maxPoints = 65535;
Limits.VNA.minDwellTime = 0;
Limits.VNA.maxDwellTime = 1;
Limits.Generator.ports = 2;