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Fix further sweep timeout issues

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This commit is contained in:
Jan Käberich 2022-06-26 18:47:34 +02:00
parent 4541dcb71b
commit 947a6b9d83
9 changed files with 53 additions and 14 deletions
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19
Software/VNA_embedded/Application/Drivers/FPGA/FPGA.cpp
View file

@ -402,12 +402,23 @@ void FPGA::ResetADCLimits() {
High(CS);
}
void FPGA::ResumeHaltedSweep() {
bool FPGA::ResumeHaltedSweep() {
uint32_t start = HAL_GetTick();
uint16_t cmd = 0x2000;
uint16_t status;
SwitchBytes(cmd);
Low(CS);
HAL_SPI_Transmit(&FPGA_SPI, (uint8_t*) &cmd, 2, 100);
High(CS);
do {
if(HAL_GetTick() - start > 100) {
LOG_WARN("Failed to resume sweep, timed out");
return false;
}
Low(CS);
HAL_SPI_TransmitReceive(&FPGA_SPI, (uint8_t*) &cmd, (uint8_t*) &status, 2, 100);
High(CS);
SwitchBytes(status);
} while(status & 0x0010);
// LOG_DEBUG("Status: 0x%04x", GetStatus());
return true;
}
void FPGA::SetupDFT(uint32_t f_firstBin, uint32_t f_binSpacing) {

2
Software/VNA_embedded/Application/Drivers/FPGA/FPGA.hpp
View file

@ -132,7 +132,7 @@ void StartDFT();
DFTResult ReadDFTResult();
ADCLimits GetADCLimits();
void ResetADCLimits();
void ResumeHaltedSweep();
bool ResumeHaltedSweep();
uint16_t GetStatus();
void OverwriteHardware(uint8_t attenuation, LowpassFilter filter, bool lowband, bool port1_enabled, bool port2_enabled);

2
Software/VNA_embedded/Application/Drivers/Log.cpp
View file

@ -79,7 +79,7 @@ void Log_Init() {
#endif
/* USART interrupt Init */
HAL_NVIC_SetPriority(NVIC_ISR, 0, 0);
HAL_NVIC_SetPriority(NVIC_ISR, 3, 0);
HAL_NVIC_EnableIRQ(NVIC_ISR);
}

8
Software/VNA_embedded/Application/Drivers/delay.cpp
View file

@ -9,10 +9,10 @@ void Delay::Init() {
// enable update interrupt
TIM1->DIER |= TIM_DIER_UIE;
HAL_NVIC_SetPriority(TIM1_UP_TIM16_IRQn, 6, 0);
HAL_NVIC_SetPriority(TIM1_UP_TIM16_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(TIM1_UP_TIM16_IRQn);
TIM1->CR1 |= TIM_CR1_CEN;
TIM1->CR1 |= TIM_CR1_CEN | TIM_CR1_UIFREMAP;
}
uint64_t Delay::get_us() {
@ -22,7 +22,7 @@ uint64_t Delay::get_us() {
uint64_t ret;
if(buf & 0x80000000) {
// UIF bit set, timer overflow not handled yet
ret = t_us + UINT16_MAX + timer_value;
ret = t_us + UINT16_MAX + 1 + timer_value;
} else {
ret = t_us + timer_value;
}
@ -46,7 +46,7 @@ void TIM1_UP_TIM16_IRQHandler() {
// clear bit
TIM1->SR &= ~TIM_SR_UIF;
// update count
t_us += UINT16_MAX;
t_us += UINT16_MAX + 1;
}
}

13
Software/VNA_embedded/Application/Hardware.cpp
View file

@ -21,7 +21,7 @@ HW::Mode activeMode;
static bool unlevel = false;
static Protocol::ReferenceSettings ref;
static uint64_t lastISR;
static volatile uint64_t lastISR;
static uint32_t IF1 = HW::DefaultIF1;
static uint32_t IF2 = HW::DefaultIF2;
@ -293,7 +293,16 @@ HW::AmplitudeSettings HW::GetAmplitudeSettings(int16_t cdbm, uint64_t freq, bool
bool HW::TimedOut() {
constexpr uint64_t timeout = 1000000;
if(activeMode != Mode::Idle && activeMode != Mode::Generator && Delay::get_us() - lastISR > timeout) {
auto bufISR = lastISR;
uint64_t now = Delay::get_us();
uint64_t timeSinceLast = now - bufISR;
if(activeMode != Mode::Idle && activeMode != Mode::Generator && timeSinceLast > timeout) {
LOG_WARN("Timed out, last ISR was at %lu%06lu, now %lu%06lu"
, (uint32_t) (bufISR / 1000000), (uint32_t)(bufISR%1000000)
, (uint32_t) (now / 1000000), (uint32_t)(now%1000000));
if(activeMode == Mode::VNA) {
VNA::PrintStatus();
}
return true;
} else {
return false;

13
Software/VNA_embedded/Application/VNA.cpp
View file

@ -498,3 +498,16 @@ void VNA::Stop() {
active = false;
FPGA::AbortSweep();
}
void VNA::PrintStatus() {
HAL_Delay(10);
LOG_INFO("VNA status:");
HAL_Delay(10);
LOG_INFO("Active: %d", active);
HAL_Delay(10);
LOG_INFO("Points: %d/%d", pointCnt, settings.points);
HAL_Delay(10);
LOG_INFO("Stages: %d/%d", stageCnt, stages);
HAL_Delay(10);
LOG_INFO("FPGA status: 0x%04x", FPGA::GetStatus());
}

2
Software/VNA_embedded/Application/VNA.hpp
View file

@ -12,5 +12,7 @@ void Work();
void SweepHalted();
void Stop();
void PrintStatus();
}