From 916d6e3e38f6a61e522827ca88e555942a3f09ec Mon Sep 17 00:00:00 2001
From: Andre Dunford <andredunford@gmail.com>
Date: Tue, 20 Dec 2022 11:14:02 -0800
Subject: [PATCH] refactor evaluation of standby waiting state

---
 Software/VNA_embedded/Application/Hardware.cpp | 4 +++-
 Software/VNA_embedded/Application/VNA.hpp      | 2 ++
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/Software/VNA_embedded/Application/Hardware.cpp b/Software/VNA_embedded/Application/Hardware.cpp
index dc675a5..3d0da00 100644
--- a/Software/VNA_embedded/Application/Hardware.cpp
+++ b/Software/VNA_embedded/Application/Hardware.cpp
@@ -250,6 +250,8 @@ void HW::SetIdle() {
 	FPGA::Enable(FPGA::Periphery::RefMixer, false);
 	FPGA::Enable(FPGA::Periphery::PortSwitch, false);
 	activeMode = Mode::Idle;
+	VNA::SetWaitingInStandby(false);
+
 }
 
 HW::AmplitudeSettings HW::GetAmplitudeSettings(int16_t cdbm, uint64_t freq, bool applyCorrections, bool port2) {
@@ -303,7 +305,7 @@ bool HW::TimedOut() {
 	auto bufISR = lastISR;
 	uint64_t now = Delay::get_us();
 	uint64_t timeSinceLast = now - bufISR;
-	if(activeMode != Mode::Idle && activeMode != Mode::Generator && !VNA::GetStandbyMode() && timeSinceLast > timeout) {
+	if(activeMode != Mode::Idle && activeMode != Mode::Generator && !VNA::IsWaitingInStandby() && timeSinceLast > timeout) {
 		LOG_WARN("Timed out, last ISR was at %lu%06lu, now %lu%06lu"
 				, (uint32_t) (bufISR / 1000000), (uint32_t)(bufISR%1000000)
 				, (uint32_t) (now / 1000000), (uint32_t)(now%1000000));
diff --git a/Software/VNA_embedded/Application/VNA.hpp b/Software/VNA_embedded/Application/VNA.hpp
index 1c4b352..a411085 100644
--- a/Software/VNA_embedded/Application/VNA.hpp
+++ b/Software/VNA_embedded/Application/VNA.hpp
@@ -9,6 +9,8 @@ namespace VNA {
 bool Setup(Protocol::SweepSettings s);
 void InitiateSweep();
 bool GetStandbyMode();
+bool IsWaitingInStandby();
+void SetWaitingInStandby(bool waiting);
 bool MeasurementDone(const FPGA::SamplingResult &result);
 void Work();
 void SweepHalted();