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https://github.com/jankae/LibreVNA.git
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Main thread using FreeRTOS notifications, added missing commands for firmware update
This commit is contained in:
Jan Käberich
parent
07ba714f1f
commit
8c33ae523a
11 changed files with 209 additions and 134 deletions
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@ -11,21 +11,22 @@
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#include "USB/usb.h"
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#include "Flash.hpp"
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#include "Firmware.hpp"
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#include "FreeRTOS.h"
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#include "task.h"
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#define LOG_LEVEL LOG_LEVEL_INFO
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#define LOG_MODULE "App"
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#include "Log.h"
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static volatile bool newResult;
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static Protocol::Datapoint result;
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static volatile bool newSettings = false;
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static Protocol::SweepSettings settings;
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static volatile bool newStatus = false;
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static FPGA::SamplingResult statusResult;
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static volatile bool newManual = false;
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static Protocol::ManualControl manual;
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static Protocol::PacketInfo packet;
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static TaskHandle_t handle;
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// TODO set proper values
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#define HW_REVISION 'A'
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#define FW_MAJOR 0
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@ -34,18 +35,34 @@ static Protocol::ManualControl manual;
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extern SPI_HandleTypeDef hspi1;
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static Flash flash = Flash(&hspi1, FLASH_CS_GPIO_Port, FLASH_CS_Pin);
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void VNACallback(Protocol::Datapoint res) {
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#define FLAG_USB_PACKET 0x01
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#define FLAG_DATAPOINT 0x02
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#define FLAG_STATUSRESULT 0x04
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static void VNACallback(Protocol::Datapoint res) {
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result = res;
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newResult = true;
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BaseType_t woken = false;
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xTaskNotifyFromISR(handle, FLAG_DATAPOINT, eSetBits, &woken);
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portYIELD_FROM_ISR(woken);
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}
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void VNAStatusCallback(FPGA::SamplingResult res) {
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static void VNAStatusCallback(FPGA::SamplingResult res) {
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statusResult = res;
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newStatus = true;
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BaseType_t woken = false;
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xTaskNotifyFromISR(handle, FLAG_STATUSRESULT, eSetBits, &woken);
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portYIELD_FROM_ISR(woken);
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}
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static void USBPacketReceived(Protocol::PacketInfo p) {
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packet = p;
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BaseType_t woken = false;
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xTaskNotifyFromISR(handle, FLAG_USB_PACKET, eSetBits, &woken);
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portYIELD_FROM_ISR(woken);
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}
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void App_Start() {
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handle = xTaskGetCurrentTaskHandle();
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usb_init(communication_usb_input);
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Log_Init();
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Communication::SetCallback(USBPacketReceived);
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// Pass on logging output to USB
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Log_SetRedirect(usb_log);
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LOG_INFO("Start");
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@ -66,66 +83,143 @@ void App_Start() {
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if (!VNA::Init()) {
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LOG_CRIT("Initialization failed, unable to start");
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}
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// Allow USB enumeration
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// USB_EN_GPIO_Port->BSRR = USB_EN_Pin;
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uint32_t lastNewPoint = HAL_GetTick();
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bool sweepActive = false;
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while (1) {
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if (newResult) {
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Protocol::PacketInfo packet;
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packet.type = Protocol::PacketType::Datapoint;
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packet.datapoint = result;
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Communication::Send(packet);
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newResult = false;
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lastNewPoint = HAL_GetTick();
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if(result.pointNum == settings.points - 1) {
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// end of sweep
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// read PLL temperatures
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uint8_t tempSource, tempLO;
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VNA::GetTemps(&tempSource, &tempLO);
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LOG_INFO("PLL temperatures: %u/%u", tempSource, tempLO);
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// Read ADC min/max
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auto limits = FPGA::GetADCLimits();
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#define ADC_LIMIT 30000
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// Compile info packet
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packet.type = Protocol::PacketType::DeviceInfo;
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packet.info.FPGA_configured = 1;
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if(limits.P1min < -ADC_LIMIT || limits.P1max > ADC_LIMIT
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|| limits.P2min < -ADC_LIMIT || limits.P2max > ADC_LIMIT
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|| limits.Rmin < -ADC_LIMIT || limits.Rmax > ADC_LIMIT) {
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packet.info.ADC_overload = true;
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} else {
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packet.info.ADC_overload = false;
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}
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packet.info.FW_major = FW_MAJOR;
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packet.info.FW_minor = FW_MINOR;
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packet.info.HW_Revision = HW_REVISION;
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auto status = FPGA::GetStatus();
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packet.info.LO1_locked = (status & (int) FPGA::Interrupt::LO1Unlock) ? 0 : 1;
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packet.info.source_locked = (status & (int) FPGA::Interrupt::SourceUnlock) ? 0 : 1;
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packet.info.extRefAvailable = 0;
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packet.info.extRefInUse = 0;
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packet.info.temperatures.LO1 = tempLO;
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packet.info.temperatures.source = tempSource;
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packet.info.temperatures.MCU = 0;
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uint32_t notification;
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if(xTaskNotifyWait(0x00, UINT32_MAX, ¬ification, 100) == pdPASS) {
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// something happened
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if(notification & FLAG_DATAPOINT) {
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Protocol::PacketInfo packet;
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packet.type = Protocol::PacketType::Datapoint;
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packet.datapoint = result;
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Communication::Send(packet);
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lastNewPoint = HAL_GetTick();
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if(result.pointNum == settings.points - 1) {
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// end of sweep
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// read PLL temperatures
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uint8_t tempSource, tempLO;
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VNA::GetTemps(&tempSource, &tempLO);
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LOG_INFO("PLL temperatures: %u/%u", tempSource, tempLO);
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// Read ADC min/max
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auto limits = FPGA::GetADCLimits();
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#define ADC_LIMIT 30000
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// Compile info packet
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packet.type = Protocol::PacketType::DeviceInfo;
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packet.info.FPGA_configured = 1;
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if(limits.P1min < -ADC_LIMIT || limits.P1max > ADC_LIMIT
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|| limits.P2min < -ADC_LIMIT || limits.P2max > ADC_LIMIT
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|| limits.Rmin < -ADC_LIMIT || limits.Rmax > ADC_LIMIT) {
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packet.info.ADC_overload = true;
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} else {
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packet.info.ADC_overload = false;
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}
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packet.info.FW_major = FW_MAJOR;
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packet.info.FW_minor = FW_MINOR;
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packet.info.HW_Revision = HW_REVISION;
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auto status = FPGA::GetStatus();
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packet.info.LO1_locked = (status & (int) FPGA::Interrupt::LO1Unlock) ? 0 : 1;
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packet.info.source_locked = (status & (int) FPGA::Interrupt::SourceUnlock) ? 0 : 1;
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packet.info.extRefAvailable = 0;
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packet.info.extRefInUse = 0;
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packet.info.temperatures.LO1 = tempLO;
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packet.info.temperatures.source = tempSource;
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packet.info.temperatures.MCU = 0;
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Communication::Send(packet);
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FPGA::ResetADCLimits();
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LOG_INFO("ADC limits: P1: %d/%d P2: %d/%d R: %d/%d",
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limits.P1min, limits.P1max, limits.P2min, limits.P2max,
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limits.Rmin, limits.Rmax);
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// Start next sweep
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FPGA::StartSweep();
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}
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}
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if(notification & FLAG_STATUSRESULT) {
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Protocol::PacketInfo p;
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p.type = Protocol::PacketType::Status;
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memset(&p.status, 0, sizeof(p.status));
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uint16_t isr_flags = FPGA::GetStatus();
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if (!(isr_flags & 0x0002)) {
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p.status.source_locked = 1;
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}
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if (!(isr_flags & 0x0001)) {
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p.status.LO_locked = 1;
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}
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auto limits = FPGA::GetADCLimits();
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FPGA::ResetADCLimits();
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LOG_INFO("ADC limits: P1: %d/%d P2: %d/%d R: %d/%d",
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limits.P1min, limits.P1max, limits.P2min, limits.P2max,
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limits.Rmin, limits.Rmax);
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// Start next sweep
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p.status.port1min = limits.P1min;
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p.status.port1max = limits.P1max;
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p.status.port2min = limits.P2min;
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p.status.port2max = limits.P2max;
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p.status.refmin = limits.Rmin;
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p.status.refmax = limits.Rmax;
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p.status.port1real = (float) statusResult.P1I / manual.Samples;
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p.status.port1imag = (float) statusResult.P1Q / manual.Samples;
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p.status.port2real = (float) statusResult.P2I / manual.Samples;
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p.status.port2imag = (float) statusResult.P2Q / manual.Samples;
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p.status.refreal = (float) statusResult.RefI / manual.Samples;
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p.status.refimag = (float) statusResult.RefQ / manual.Samples;
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VNA::GetTemps(&p.status.temp_source, &p.status.temp_LO);
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Communication::Send(p);
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// Trigger next status update
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FPGA::StartSweep();
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}
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if(notification & FLAG_USB_PACKET) {
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switch(packet.type) {
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case Protocol::PacketType::SweepSettings:
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LOG_INFO("New settings received");
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settings = packet.settings;
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VNA::ConfigureSweep(settings, VNACallback);
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sweepActive = true;
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lastNewPoint = HAL_GetTick();
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break;
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case Protocol::PacketType::ManualControl:
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sweepActive = false;
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manual = packet.manual;
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VNA::ConfigureManual(manual, VNAStatusCallback);
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break;
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case Protocol::PacketType::ClearFlash:
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FPGA::AbortSweep();
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sweepActive = false;
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LOG_DEBUG("Erasing FLASH in preparation for firmware update...");
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if(flash.eraseChip()) {
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LOG_DEBUG("...FLASH erased")
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Protocol::PacketInfo p;
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p.type = Protocol::PacketType::Ack;
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Communication::Send(p);
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} else {
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LOG_ERR("Failed to erase FLASH");
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}
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break;
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case Protocol::PacketType::FirmwarePacket:
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LOG_INFO("Writing firmware packet at address %u", packet.firmware.address);
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flash.write(packet.firmware.address, sizeof(packet.firmware.data), packet.firmware.data);
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Protocol::PacketInfo p;
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p.type = Protocol::PacketType::Ack;
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Communication::Send(p);
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break;
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case Protocol::PacketType::PerformFirmwareUpdate: {
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auto fw_info = Firmware::GetFlashContentInfo(&flash);
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if(fw_info.valid) {
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Protocol::PacketInfo p;
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p.type = Protocol::PacketType::Ack;
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Communication::Send(p);
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// Some delay to allow communication to finish
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vTaskDelay(1000);
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Firmware::PerformUpdate(&flash);
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// will never get here
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}
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}
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break;
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default:
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// ignore all other packets
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break;
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}
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}
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}
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if (newSettings) {
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LOG_INFO("New settings received");
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newSettings = false;
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VNA::ConfigureSweep(settings, VNACallback);
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sweepActive = true;
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lastNewPoint = HAL_GetTick();
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}
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if(sweepActive && HAL_GetTick() - lastNewPoint > 1000) {
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LOG_WARN("Timed out waiting for point, last received point was %d", result.pointNum);
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LOG_WARN("FPGA status: 0x%04x", FPGA::GetStatus());
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@ -134,52 +228,5 @@ void App_Start() {
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sweepActive = true;
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lastNewPoint = HAL_GetTick();
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}
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if (newManual) {
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LOG_INFO("New manual control");
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sweepActive = false;
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newManual = false;
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VNA::ConfigureManual(manual, VNAStatusCallback);
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}
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if (newStatus) {
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newStatus = false;
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Protocol::PacketInfo p;
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p.type = Protocol::PacketType::Status;
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memset(&p.status, 0, sizeof(p.status));
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uint16_t isr_flags = FPGA::GetStatus();
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if (!(isr_flags & 0x0002)) {
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p.status.source_locked = 1;
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}
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if (!(isr_flags & 0x0001)) {
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p.status.LO_locked = 1;
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}
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auto limits = FPGA::GetADCLimits();
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FPGA::ResetADCLimits();
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p.status.port1min = limits.P1min;
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p.status.port1max = limits.P1max;
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p.status.port2min = limits.P2min;
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p.status.port2max = limits.P2max;
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p.status.refmin = limits.Rmin;
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p.status.refmax = limits.Rmax;
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p.status.port1real = (float) statusResult.P1I / manual.Samples;
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p.status.port1imag = (float) statusResult.P1Q / manual.Samples;
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p.status.port2real = (float) statusResult.P2I / manual.Samples;
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p.status.port2imag = (float) statusResult.P2Q / manual.Samples;
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p.status.refreal = (float) statusResult.RefI / manual.Samples;
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p.status.refimag = (float) statusResult.RefQ / manual.Samples;
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VNA::GetTemps(&p.status.temp_source, &p.status.temp_LO);
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Communication::Send(p);
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// Trigger next status update
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FPGA::StartSweep();
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}
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}
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}
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void App::NewSettings(Protocol::SweepSettings s) {
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settings = s;
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newSettings = true;
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}
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void App::SetManual(Protocol::ManualControl m) {
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manual = m;
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newManual = true;
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}
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