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Use full multiplier bitwidth for windowing + increased number of DFT bins

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Jan Käberich 2020-11-07 17:10:41 +01:00
parent a2389fca13
commit 8b9b8265b9
21 changed files with 625 additions and 579 deletions
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2
Software/VNA_embedded/Application/Drivers/FPGA/FPGA.hpp
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@ -6,7 +6,7 @@
namespace FPGA {
static constexpr uint16_t MaxPoints = 4501;
static constexpr uint16_t DFTbins = 64;
static constexpr uint16_t DFTbins = 96;
static constexpr uint32_t Clockrate = 102400000UL;
enum class Reg {