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https://github.com/jankae/LibreVNA.git
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Allow different source PLL power per sweep point, add power range to sweep
This commit is contained in:
Jan Käberich
parent
6490d6fd14
commit
7bc18881a5
10 changed files with 96 additions and 389 deletions
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@ -4,7 +4,7 @@
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namespace Protocol {
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static constexpr uint16_t Version = 5;
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static constexpr uint16_t Version = 7;
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#pragma pack(push, 1)
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@ -22,10 +22,12 @@ using SweepSettings = struct _sweepSettings {
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uint64_t f_stop;
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uint16_t points;
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uint32_t if_bandwidth;
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int16_t cdbm_excitation; // in 1/100 dbm
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int16_t cdbm_excitation_start; // in 1/100 dbm
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uint8_t excitePort1:1;
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uint8_t excitePort2:1;
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uint8_t suppressPeaks:1;
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uint8_t fixedPowerSetting:1; // if set the attenuator and source PLL power will not be changed across the sweep
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int16_t cdbm_excitation_stop; // in 1/100 dbm
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};
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using ReferenceSettings = struct _referenceSettings {
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@ -197,6 +197,8 @@ void FPGA::WriteSweepConfig(uint16_t pointnum, bool lowband, uint32_t *SourceReg
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uint16_t Source_VCO = (SourceRegs[3] & 0xFC000000) >> 26;
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uint16_t Source_DIV_A = (SourceRegs[4] & 0x00700000) >> 20;
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uint16_t Source_Power = (SourceRegs[4] & 0x00000018) >> 3;
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send[1] = LO_M >> 4;
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if (halt) {
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send[1] |= 0x8000;
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@ -218,13 +220,13 @@ void FPGA::WriteSweepConfig(uint16_t pointnum, bool lowband, uint32_t *SourceReg
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send[1] |= (int) filter << 8;
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}
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send[2] = (LO_M & 0x000F) << 12 | LO_FRAC;
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send[3] = LO_DIV_A << 13 | LO_VCO << 7 | LO_N;
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send[4] = (uint16_t) attenuation << 8 | Source_M >> 4;
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send[3] = LO_DIV_A << 13 | LO_VCO << 7 | LO_N << 1;
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send[4] = Source_Power << 14 | (uint16_t) attenuation << 7 | Source_M >> 5;
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if (lowband) {
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send[4] |= 0x8000;
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send[3] |= 0x0001;
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}
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send[5] = (Source_M & 0x000F) << 12 | Source_FRAC;
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send[6] = Source_DIV_A << 13 | Source_VCO << 7 | Source_N;
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send[5] = (Source_M & 0x001F) << 11 | Source_FRAC >> 1;
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send[6] = (Source_FRAC & 0x0001) << 15 | Source_DIV_A << 12 | Source_VCO << 6 | Source_N;
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SwitchBytes(send[0]);
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SwitchBytes(send[1]);
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SwitchBytes(send[2]);
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@ -2,6 +2,7 @@
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#include <cstdint>
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#include "Flash.hpp"
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#include "max2871.hpp"
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namespace FPGA {
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@ -23,7 +23,7 @@ static uint16_t pointCnt;
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static bool excitingPort1;
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static Protocol::Datapoint data;
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static bool active = false;
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static bool sourceHighPower;
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static Si5351C::DriveStrength fixedPowerLowband;
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static bool adcShifted;
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static uint32_t actualBandwidth;
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@ -76,26 +76,24 @@ bool VNA::Setup(Protocol::SweepSettings s) {
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// has to be one less than actual number of samples
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FPGA::SetSamplesPerPoint(samplesPerPoint);
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// Set level (not very accurate)
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int16_t cdbm = s.cdbm_excitation;
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if(cdbm > -1000) {
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// use higher source power (approx 0dbm with no attenuation)
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sourceHighPower = true;
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Source.SetPowerOutA(MAX2871::Power::p5dbm, true);
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} else {
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// use lower source power (approx -10dbm with no attenuation)
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sourceHighPower = false;
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Source.SetPowerOutA(MAX2871::Power::n4dbm, true);
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cdbm += 1000;
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}
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uint8_t attenuator;
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if(cdbm >= 0) {
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attenuator = 0;
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} else if (cdbm <= -3175){
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attenuator = 127;
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} else {
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attenuator = (-cdbm) / 25;
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// Start with average level
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auto cdbm = (s.cdbm_excitation_start + s.cdbm_excitation_stop) / 2;
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// correct for port 1, assumes port 2 is identical
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auto centerFreq = (s.f_start + s.f_stop) / 2;
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// force calculation of amplitude setting for PLL, even with lower frequencies
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if(centerFreq < HW::BandSwitchFrequency) {
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centerFreq = HW::BandSwitchFrequency;
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}
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auto amplitude = HW::GetAmplitudeSettings(cdbm, centerFreq, true, false);
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uint8_t fixedAttenuatorHighband = amplitude.attenuator;
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Source.SetPowerOutA(amplitude.highBandPower, true);
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// amplitude calculation for lowband
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amplitude = HW::GetAmplitudeSettings(cdbm, HW::BandSwitchFrequency / 2, true, false);
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uint8_t fixedAttenuatorLowband = amplitude.attenuator;
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fixedPowerLowband = amplitude.lowBandPower;
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FPGA::WriteMAX2871Default(Source.GetRegisters());
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uint32_t last_LO2 = HW::IF1 - HW::IF2;
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@ -117,6 +115,7 @@ bool VNA::Setup(Protocol::SweepSettings s) {
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for (uint16_t i = 0; i < points; i++) {
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bool harmonic_mixing = false;
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uint64_t freq = s.f_start + (s.f_stop - s.f_start) * i / (points - 1);
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int16_t power = s.cdbm_excitation_start + (s.cdbm_excitation_stop - s.cdbm_excitation_start) * i / (points - 1);
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freq = Cal::FrequencyCorrectionToDevice(freq);
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if(freq > 6000000000ULL) {
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@ -206,6 +205,16 @@ bool VNA::Setup(Protocol::SweepSettings s) {
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pointsWithoutHalt = 0;
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}
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uint8_t attenuator = freq >= HW::BandSwitchFrequency ? fixedAttenuatorHighband : fixedAttenuatorLowband;
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if(!s.fixedPowerSetting) {
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// adapt power level throughout the sweep
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amplitude = HW::GetAmplitudeSettings(power, freq, true, false);
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if(freq >= HW::BandSwitchFrequency) {
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Source.SetPowerOutA(amplitude.highBandPower, true);
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}
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attenuator = amplitude.attenuator;
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}
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FPGA::WriteSweepConfig(i, lowband, Source.GetRegisters(),
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LO1.GetRegisters(), attenuator, freq, FPGA::SettlingTime::us20,
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FPGA::Samples::SPPRegister, needs_halt);
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@ -331,11 +340,20 @@ void VNA::SweepHalted() {
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uint64_t frequency = settings.f_start
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+ (settings.f_stop - settings.f_start) * pointCnt
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/ (settings.points - 1);
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int16_t power = settings.cdbm_excitation_start
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+ (settings.cdbm_excitation_stop - settings.cdbm_excitation_start)
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* pointCnt / (settings.points - 1);
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bool adcShiftRequired = false;
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if (frequency < HW::BandSwitchFrequency) {
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auto driveStrength = fixedPowerLowband;
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if(!settings.fixedPowerSetting) {
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auto amplitude = HW::GetAmplitudeSettings(power, frequency, true, false);
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// attenuator value has already been set in sweep setup
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driveStrength = amplitude.lowBandPower;
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}
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// need the Si5351 as Source
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Si5351.SetCLK(SiChannel::LowbandSource, frequency, Si5351C::PLL::B,
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sourceHighPower ? Si5351C::DriveStrength::mA8 : Si5351C::DriveStrength::mA4);
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Si5351.SetCLK(SiChannel::LowbandSource, frequency, Si5351C::PLL::B, driveStrength);
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if (pointCnt == 0) {
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// First point in sweep, enable CLK
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Si5351.Enable(SiChannel::LowbandSource);
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