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WIP: synchronization

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This commit is contained in:
Jan Käberich 2022-08-08 18:08:40 +02:00
parent 7b3aa6e158
commit 73e26a25c4
41 changed files with 439 additions and 163 deletions
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4
Software/VNA_embedded/Application/App.cpp
View file

@ -305,10 +305,6 @@ inline void App_Process() {
}
}
if(HW::TimedOut()) {
vTaskDelay(1000);
LOG_WARN("Timed out, FPGA status: 0x%04x", FPGA::GetStatus());
vTaskDelay(1000);
LOG_WARN("Trigger out: %d (last reported: %d), in: %d", (uint8_t) Trigger::GetOutput(), (uint8_t) lastReportedTrigger, (uint8_t) Trigger::GetInput());
HW::SetMode(HW::Mode::Idle);
// insert the last received packet (restarts the timed out operation)
Communication::BlockNextAck();

4
Software/VNA_embedded/Application/Communication/Protocol.hpp
View file

@ -130,7 +130,8 @@ using SweepSettings = struct _sweepSettings {
uint16_t points;
uint32_t if_bandwidth;
int16_t cdbm_excitation_start; // in 1/100 dbm
uint16_t unused:2;
uint16_t unused:1;
uint16_t syncMaster:1;
uint16_t suppressPeaks:1;
uint16_t fixedPowerSetting:1; // if set the attenuator and source PLL power will not be changed across the sweep
uint16_t logSweep:1;
@ -258,6 +259,7 @@ using SpectrumAnalyzerSettings = struct _spectrumAnalyzerSettings {
* 3: Trigger synchronization (not supported yet by hardware)
*/
uint8_t syncMode :2;
uint8_t syncMaster :1;
int64_t trackingGeneratorOffset;
int16_t trackingPower;
};

3
Software/VNA_embedded/Application/Drivers/FPGA/FPGA.cpp
View file

@ -130,7 +130,7 @@ void FPGA::SetSamplesPerPoint(uint32_t nsamples) {
WriteRegister(Reg::SamplesPerPoint, nsamples);
}
void FPGA::SetupSweep(uint8_t stages, uint8_t port1_stage, uint8_t port2_stage, bool synchronize) {
void FPGA::SetupSweep(uint8_t stages, uint8_t port1_stage, uint8_t port2_stage, bool synchronize, bool syncMaster) {
uint16_t value = 0x0000;
value |= (uint16_t) (stages & 0x07) << 13;
if(synchronize) {
@ -139,6 +139,7 @@ void FPGA::SetupSweep(uint8_t stages, uint8_t port1_stage, uint8_t port2_stage,
value |= (port1_stage & 0x07) << 3;
value |= (port2_stage & 0x07) << 0;
WriteRegister(Reg::SweepSetup, value);
Enable(Periphery::SyncMaster, syncMaster);
}
void FPGA::Enable(Periphery p, bool enable) {

4
Software/VNA_embedded/Application/Drivers/FPGA/FPGA.hpp
View file

@ -61,7 +61,7 @@ enum class Periphery {
DebugLED = 0x0080,
SourceChip = 0x0010,
LO1Chip = 0x0008,
SyncMaster = 0x0002,
PortSwitch = 0x0001,
};
@ -114,7 +114,7 @@ bool Init(HaltedCallback cb = nullptr);
void WriteRegister(FPGA::Reg reg, uint16_t value);
void SetNumberOfPoints(uint16_t npoints);
void SetSamplesPerPoint(uint32_t nsamples);
void SetupSweep(uint8_t stages, uint8_t port1_stage, uint8_t port2_stage, bool synchronize = false);
void SetupSweep(uint8_t stages, uint8_t port1_stage, uint8_t port2_stage, bool synchronize = false, bool syncMaster = false);
void Enable(Periphery p, bool enable = true);
void Disable(Periphery p);
bool IsEnabled(Periphery p);

2
Software/VNA_embedded/Application/Hardware.cpp
View file

@ -9,6 +9,7 @@
#include "delay.hpp"
#include "SpectrumAnalyzer.hpp"
#include "Communication.h"
#include "Trigger.hpp"
#include <cstring>
#define LOG_LEVEL LOG_LEVEL_INFO
@ -230,6 +231,7 @@ bool HW::GetTemps(uint8_t *source, uint8_t *lo) {
void HW::SetIdle() {
unlevel = false;
Trigger::SetInput(false);
FPGA::AbortSweep();
FPGA::SetMode(FPGA::Mode::FPGA);
FPGA::DisableHardwareOverwrite();

12
Software/VNA_embedded/Application/Led.cpp
View file

@ -87,8 +87,8 @@ void LED::Init() {
#if HW_REVISION == 'B'
led_ncnt = 0;
mode = Mode::Off;
HAL_TIM_Base_Start(&htim2);
HAL_TIM_PWM_Start(&htim2, TIM_CHANNEL_1);
// HAL_TIM_Base_Start(&htim2);
// HAL_TIM_PWM_Start(&htim2, TIM_CHANNEL_1);
LedStatusHandle = xTaskCreateStatic(LedStatus, "LedStatusTask", LED_STATUS_TASK_STACK_SIZE_WORDS,
NULL, 6, LedStatusStack, &LedStatusCB);
@ -132,3 +132,11 @@ void LED::Error(uint8_t code) {
vTaskResume(LedStatusHandle);
#endif
}
void LED::On() {
GPIOA->BSRR = GPIO_PIN_15;
}
void LED::Toggle() {
GPIOA->ODR ^= GPIO_PIN_15;
}

3
Software/VNA_embedded/Application/Led.hpp
View file

@ -9,4 +9,7 @@ void Pulsating();
void Off();
void Error(uint8_t code);
void On();
void Toggle();
}

2
Software/VNA_embedded/Application/SpectrumAnalyzer.cpp
View file

@ -225,7 +225,7 @@ void SA::Setup(Protocol::SpectrumAnalyzerSettings settings) {
FPGA::SetWindow((FPGA::Window) s.WindowType);
FPGA::Enable(FPGA::Periphery::LO1Chip);
FPGA::Enable(FPGA::Periphery::LO1RF);
FPGA::SetupSweep(0, s.trackingGeneratorPort == 1, s.trackingGeneratorPort == 0, s.syncMode != 0);
FPGA::SetupSweep(0, s.trackingGeneratorPort == 1, s.trackingGeneratorPort == 0, s.syncMode != 0, s.syncMaster);
FPGA::Enable(FPGA::Periphery::PortSwitch, s.trackingGenerator);
FPGA::Enable(FPGA::Periphery::Amplifier, s.trackingGenerator);
FPGA::Enable(FPGA::Periphery::Port1Mixer);

2
Software/VNA_embedded/Application/VNA.cpp
View file

@ -279,7 +279,7 @@ bool VNA::Setup(Protocol::SweepSettings s) {
FPGA::Enable(FPGA::Periphery::SourceRF);
FPGA::Enable(FPGA::Periphery::LO1Chip);
FPGA::Enable(FPGA::Periphery::LO1RF);
FPGA::SetupSweep(s.stages, s.port1Stage, s.port2Stage, s.syncMode != 0);
FPGA::SetupSweep(s.stages, s.port1Stage, s.port2Stage, s.syncMode != 0, s.syncMaster);
Trigger::SetMode((Trigger::Mode) s.syncMode);
FPGA::Enable(FPGA::Periphery::PortSwitch);
pointCnt = 0;

2
Software/VNA_embedded/VNA_embedded.ioc
View file

@ -405,7 +405,7 @@ SPI2.VirtualType=VM_MASTER
TIM1.IPParameters=Prescaler
TIM1.Prescaler=159
TIM2.Channel-PWM\ Generation1\ CH1=TIM_CHANNEL_1
TIM2.IPParameters=Channel-PWM Generation1 CH1,Prescaler,PeriodNoDither,OCMode_PWM-PWM Generation1 CH1
TIM2.IPParameters=Prescaler,PeriodNoDither,Channel-PWM Generation1 CH1,OCMode_PWM-PWM Generation1 CH1
TIM2.OCMode_PWM-PWM\ Generation1\ CH1=TIM_OCMODE_PWM2
TIM2.PeriodNoDither=99
TIM2.Prescaler=143