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WIP: synchronization

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This commit is contained in:
Jan Käberich 2022-08-08 18:08:40 +02:00
parent 7b3aa6e158
commit 73e26a25c4
41 changed files with 439 additions and 163 deletions
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2
FPGA/VNA/SPIConfig.vhd
View file

@ -52,6 +52,7 @@ entity SPICommands is
NSAMPLES : out STD_LOGIC_VECTOR (12 downto 0);
STAGES : out STD_LOGIC_VECTOR (2 downto 0);
SYNC_ENABLED : out STD_LOGIC;
SYNC_MASTER : out STD_LOGIC;
PORT1_STAGE : out STD_LOGIC_VECTOR (2 downto 0);
PORT2_STAGE : out STD_LOGIC_VECTOR (2 downto 0);
PORT1_EN : out STD_LOGIC;
@ -250,6 +251,7 @@ begin
WINDOW_SETTING <= spi_buf_out(6 downto 5);
SOURCE_CE_EN <= spi_buf_out(4);
LO_CE_EN <= spi_buf_out(3);
SYNC_MASTER <= spi_buf_out(1);
when 4 => ADC_PRESCALER <= spi_buf_out(7 downto 0);
when 5 => ADC_PHASEINC <= spi_buf_out(11 downto 0);
when 6 => STAGES <= spi_buf_out(15 downto 13);

39
FPGA/VNA/Sweep.vhd
View file

@ -62,9 +62,12 @@ entity Sweep is
SWEEP_RESUME : in STD_LOGIC;
SYNC_ENABLED : in STD_LOGIC;
SYNC_MASTER : in STD_LOGIC;
TRIGGER_IN : in STD_LOGIC;
TRIGGER_OUT : out STD_LOGIC;
NEW_DATA : out STD_LOGIC;
ATTENUATOR : out STD_LOGIC_VECTOR(6 downto 0);
SOURCE_FILTER : out STD_LOGIC_VECTOR(1 downto 0);
@ -85,7 +88,7 @@ end Sweep;
architecture Behavioral of Sweep is
signal point_cnt : unsigned(12 downto 0);
type Point_states is (TriggerSetup, SettingUp, Settling, WaitTriggerHigh, Exciting, WaitTriggerLow, SamplingDone, NextPoint, Done);
type Point_states is (WaitInitialLow, TriggerSetup, SettingUp, Settling, WaitTriggerHigh, Exciting, WaitTriggerLow, SamplingDone, NextPoint, Done);
signal state : Point_states;
signal settling_cnt : unsigned(15 downto 0);
signal settling_time : unsigned(15 downto 0);
@ -153,7 +156,7 @@ begin
if RESET = '1' then
point_cnt <= (others => '0');
stage_cnt <= (others => '0');
state <= WaitTriggerLow;
state <= WaitInitialLow;
START_SAMPLING <= '0';
RELOAD_PLL_REGS <= '0';
SWEEP_HALTED <= '0';
@ -164,19 +167,10 @@ begin
source_active <= '0';
else
case state is
when WaitTriggerLow =>
if SYNC_ENABLED = '1' and (std_logic_vector(stage_cnt) = PORT1_STAGE or std_logic_vector(stage_cnt) = PORT2_STAGE) then
TRIGGER_OUT <= '0';
end if;
when WaitInitialLow =>
TRIGGER_OUT <= '0';
if TRIGGER_IN = '0' or SYNC_ENABLED = '0' then
TRIGGER_OUT <= '0';
if stage_cnt = 0 then
-- first stage in point, need to trigger PLL setup
state <= TriggerSetup;
else
-- PLLs already configured correctly
state <= SettingUp;
end if;
state <= TriggerSetup;
end if;
when TriggerSetup =>
RELOAD_PLL_REGS <= '1';
@ -221,7 +215,7 @@ begin
else
-- need to wait for the trigger
state <= WaitTriggerHigh;
if SYNC_ENABLED = '1' and (std_logic_vector(stage_cnt) = PORT1_STAGE or std_logic_vector(stage_cnt) = PORT2_STAGE) then
if SYNC_MASTER = '1' then
-- this device generates the stimulus signal, it needs start the trigger itself
TRIGGER_OUT <= '1';
end if;
@ -238,14 +232,25 @@ begin
-- wait for sampling to finish
START_SAMPLING <= '0';
if SAMPLING_BUSY = '0' then
NEW_DATA <= '1';
RESULT_INDEX <= std_logic_vector(stage_cnt) & std_logic_vector(point_cnt);
state <= WaitTriggerLow;
end if;
when WaitTriggerLow =>
NEW_DATA <= '0';
if SYNC_MASTER = '1' then
TRIGGER_OUT <= '0';
end if;
if TRIGGER_IN = '0' or SYNC_ENABLED = '0' then
TRIGGER_OUT <= '0';
state <= SamplingDone;
end if;
when SamplingDone =>
NEW_DATA <= '0';
if stage_cnt < unsigned(STAGES) then
stage_cnt <= stage_cnt + 1;
-- can go directly to preperation for next stage
state <= WaitTriggerLow;
state <= Settling;
else
state <= NextPoint;
end if;
@ -254,7 +259,7 @@ begin
if point_cnt < unsigned(NPOINTS) then
point_cnt <= point_cnt + 1;
stage_cnt <= (others => '0');
state <= WaitTriggerLow;
state <= TriggerSetup;
else
point_cnt <= (others => '0');
state <= Done;

15
FPGA/VNA/VNA.gise
View file

@ -224,7 +224,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1659868712" xil_pn:in_ck="-4366097307991745463" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1659868712">
<transform xil_pn:end_ts="1659962405" xil_pn:in_ck="-4366097307991745463" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1659962405">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="ipcore_dir/DSP_SLICE.ngc"/>
@ -253,7 +253,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1659869263" xil_pn:in_ck="2241500006820465658" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="3256065936432453276" xil_pn:start_ts="1659869254">
<transform xil_pn:end_ts="1659974081" xil_pn:in_ck="2241500006820465658" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="3256065936432453276" xil_pn:start_ts="1659974072">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
@ -275,7 +275,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1659869266" xil_pn:in_ck="5411862124762956458" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="4604875190571501774" xil_pn:start_ts="1659869263">
<transform xil_pn:end_ts="1659974085" xil_pn:in_ck="5411862124762956458" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="4604875190571501774" xil_pn:start_ts="1659974081">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/>
@ -284,7 +284,7 @@
<outfile xil_pn:name="top.ngd"/>
<outfile xil_pn:name="top_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1659869298" xil_pn:in_ck="8512332261572065657" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-4668962392366239264" xil_pn:start_ts="1659869266">
<transform xil_pn:end_ts="1659974193" xil_pn:in_ck="8512332261572065657" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-4668962392366239264" xil_pn:start_ts="1659974085">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
@ -298,7 +298,7 @@
<outfile xil_pn:name="top_summary.xml"/>
<outfile xil_pn:name="top_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1659869311" xil_pn:in_ck="1117507038335044978" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-1085068593928086116" xil_pn:start_ts="1659869298">
<transform xil_pn:end_ts="1659974205" xil_pn:in_ck="1117507038335044978" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-1085068593928086116" xil_pn:start_ts="1659974193">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
@ -312,8 +312,9 @@
<outfile xil_pn:name="top_pad.txt"/>
<outfile xil_pn:name="top_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1659869318" xil_pn:in_ck="154288912438" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="3274353840855015246" xil_pn:start_ts="1659869311">
<transform xil_pn:end_ts="1659974213" xil_pn:in_ck="154288912438" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="3274353840855015246" xil_pn:start_ts="1659974205">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<outfile xil_pn:name="top.bgn"/>
@ -365,7 +366,7 @@
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="InputRemoved"/>
</transform>
<transform xil_pn:end_ts="1659869311" xil_pn:in_ck="8512326635937592693" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1659869308">
<transform xil_pn:end_ts="1659974205" xil_pn:in_ck="8512326635937592693" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1659974202">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>

BIN
FPGA/VNA/top.bin
View file

Binary file not shown.

32
FPGA/VNA/top.vhd
View file

@ -139,8 +139,10 @@ architecture Behavioral of top is
SWEEP_HALTED : out STD_LOGIC;
SWEEP_RESUME : in STD_LOGIC;
SYNC_ENABLED : in STD_LOGIC;
SYNC_MASTER : in STD_LOGIC;
TRIGGER_IN : in STD_LOGIC;
TRIGGER_OUT : out STD_LOGIC;
NEW_DATA : out STD_LOGIC;
ATTENUATOR : OUT std_logic_vector(6 downto 0);
SOURCE_FILTER : OUT std_logic_vector(1 downto 0);
STAGES : in STD_LOGIC_VECTOR (2 downto 0);
@ -253,6 +255,7 @@ architecture Behavioral of top is
NSAMPLES : OUT std_logic_vector(12 downto 0);
STAGES : out STD_LOGIC_VECTOR (2 downto 0);
SYNC_ENABLED : out STD_LOGIC;
SYNC_MASTER : out STD_LOGIC;
PORT1_STAGE : out STD_LOGIC_VECTOR (2 downto 0);
PORT2_STAGE : out STD_LOGIC_VECTOR (2 downto 0);
PORT1_EN : out STD_LOGIC;
@ -376,6 +379,7 @@ architecture Behavioral of top is
signal sweep_points : std_logic_vector(12 downto 0);
signal sweep_stages : STD_LOGIC_VECTOR (2 downto 0);
signal sweep_sync_enabled: STD_LOGIC;
signal sweep_sync_master : STD_LOGIC;
signal sweep_port1_stage : STD_LOGIC_VECTOR (2 downto 0);
signal sweep_port2_stage : STD_LOGIC_VECTOR (2 downto 0);
signal sweep_config_data : std_logic_vector(95 downto 0);
@ -395,6 +399,9 @@ architecture Behavioral of top is
signal sweep_excite_port1 : std_logic;
signal sweep_excite_port2 : std_logic;
signal sweep_trigger_in : std_logic;
signal sweep_trigger_out : std_logic;
-- Configuration signals
signal settling_time : std_logic_vector(15 downto 0);
signal def_reg_4 : std_logic_vector(31 downto 0);
@ -531,7 +538,21 @@ begin
CLK => clk_pll,
SYNC_IN => MCU_NSS,
SYNC_OUT => nss_sync
);
);
Sync_TRIGGER_IN : Synchronizer
GENERIC MAP(stages => 2)
PORT MAP(
CLK => clk_pll,
SYNC_IN => TRIGGER_IN,
SYNC_OUT => sweep_trigger_in
);
Sync_TRIGGER_OUT : Synchronizer
GENERIC MAP(stages => 2)
PORT MAP(
CLK => clk_pll,
SYNC_IN => sweep_trigger_out,
SYNC_OUT => TRIGGER_OUT
);
Source: MAX2871
@ -644,7 +665,7 @@ begin
REF => ref_windowed,
ADC_START => adc_trigger_sample,
NEW_SAMPLE => windowing_ready,
DONE => sampling_done,
DONE => open,
PRE_DONE => open,
START => sampling_start,
SAMPLES => sampling_samples,
@ -689,8 +710,10 @@ begin
SWEEP_HALTED => sweep_halted,
SWEEP_RESUME => sweep_resume,
SYNC_ENABLED => sweep_sync_enabled,
TRIGGER_IN => TRIGGER_IN,
TRIGGER_OUT => TRIGGER_OUT,
SYNC_MASTER => sweep_sync_master,
TRIGGER_IN => sweep_trigger_in,
TRIGGER_OUT => sweep_trigger_out,
NEW_DATA => sampling_done,
ATTENUATOR => sweep_attenuator,
SOURCE_FILTER => sweep_source_filter,
STAGES => sweep_stages,
@ -772,6 +795,7 @@ begin
SWEEP_RESUME => sweep_resume,
STAGES => sweep_stages,
SYNC_ENABLED => sweep_sync_enabled,
SYNC_MASTER => sweep_sync_master,
PORT1_STAGE => sweep_port1_stage,
PORT2_STAGE => sweep_port2_stage,
SPI_OVERWRITE_ENABLED => HW_overwrite_enabled,