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fix order of LO1 and source unlock LEDs

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This commit is contained in:
Jan Käberich 2025-01-05 18:15:30 +01:00
parent b77ba278de
commit 733d0ffbf4
3 changed files with 24 additions and 10 deletions
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30
FPGA/VNA/VNA.gise
View file

@ -140,6 +140,10 @@
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@ -174,6 +178,7 @@
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@ -187,6 +192,11 @@
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@ -218,7 +228,10 @@
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@ -230,6 +243,7 @@
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@ -244,7 +258,7 @@
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@ -273,7 +287,7 @@
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@ -291,11 +305,11 @@
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<outfile xil_pn:name="xst"/>
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@ -304,7 +318,7 @@
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@ -318,7 +332,7 @@
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@ -333,7 +347,7 @@
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@ -386,7 +400,7 @@
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BIN
FPGA/VNA/top.bin
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4
FPGA/VNA/top.vhd
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@ -459,8 +459,8 @@ begin
LEDS(0) <= user_leds(2);
-- Lock status of PLLs
LEDS(1) <= clk_locked;
LEDS(2) <= SOURCE_LD;
LEDS(3) <= LO1_LD;
LEDS(2) <= LO1_LD;
LEDS(3) <= SOURCE_LD;
-- Sweep and active port
PORT_SELECT2 <= (sweep_excite_port2 and portswitch_en) when HW_overwrite_enabled = '0' else HW_overwrite_data(3);
PORT2_SELECT <= (sweep_excite_port2 and portswitch_en) when HW_overwrite_enabled = '0' else HW_overwrite_data(3);