From 7151fffcdbf4a3a3f6e0f75e810e0bfbbbdd80d7 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jan=20K=C3=A4berich?= <j.kaeberich@gmx.de>
Date: Wed, 22 Jun 2022 23:00:09 +0200
Subject: [PATCH] Zero span improvements

---
 Software/PC_Application/VNA/vna.cpp                 | 5 ++---
 Software/VNA_embedded/Application/Drivers/delay.cpp | 6 +++---
 Software/VNA_embedded/Application/Hardware.cpp      | 2 +-
 3 files changed, 6 insertions(+), 7 deletions(-)

diff --git a/Software/PC_Application/VNA/vna.cpp b/Software/PC_Application/VNA/vna.cpp
index 1ac96c9..0c030e9 100644
--- a/Software/PC_Application/VNA/vna.cpp
+++ b/Software/PC_Application/VNA/vna.cpp
@@ -843,9 +843,8 @@ void VNA::NewDatapoint(Protocol::Datapoint d)
 
     auto vd = VNAData(d);
 
-    if(!settings.zerospan) {
-        vd = average.process(vd);
-    }
+    vd = average.process(vd);
+
     if(calMeasuring) {
         if(average.currentSweep() == averages) {
             // this is the last averaging sweep, use values for calibration
diff --git a/Software/VNA_embedded/Application/Drivers/delay.cpp b/Software/VNA_embedded/Application/Drivers/delay.cpp
index 29ad975..65a9a2f 100644
--- a/Software/VNA_embedded/Application/Drivers/delay.cpp
+++ b/Software/VNA_embedded/Application/Drivers/delay.cpp
@@ -9,7 +9,7 @@ void Delay::Init() {
 
 	// enable update interrupt
 	TIM1->DIER |= TIM_DIER_UIE;
-    HAL_NVIC_SetPriority(TIM1_UP_TIM16_IRQn, 0, 0);
+    HAL_NVIC_SetPriority(TIM1_UP_TIM16_IRQn, 6, 0);
     HAL_NVIC_EnableIRQ(TIM1_UP_TIM16_IRQn);
 
 	TIM1->CR1 |= TIM_CR1_CEN;
@@ -36,8 +36,8 @@ void Delay::ms(uint32_t t) {
 	}
 }
 void Delay::us(uint32_t t) {
-	uint64_t start = get_us();
-	while(start + t > get_us());
+	uint64_t start = TIM1->CNT;
+	while(TIM1->CNT - start < t);
 }
 
 extern "C" {
diff --git a/Software/VNA_embedded/Application/Hardware.cpp b/Software/VNA_embedded/Application/Hardware.cpp
index 36110d6..f4a3d0a 100644
--- a/Software/VNA_embedded/Application/Hardware.cpp
+++ b/Software/VNA_embedded/Application/Hardware.cpp
@@ -61,8 +61,8 @@ static void ReadComplete(const FPGA::SamplingResult &result) {
 }
 
 static void FPGA_Interrupt(void*) {
-	lastISR = Delay::get_us();
 	FPGA::InitiateSampleRead(ReadComplete);
+	lastISR = Delay::get_us();
 }
 
 void HW::Work() {