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HAL layer for VNA functionality to use similar firmware on both hardware revisions

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This commit is contained in:
Jan Käberich 2020-09-11 23:08:30 +02:00
parent f4a6b24a8e
commit 6960498fcb
12 changed files with 164 additions and 87 deletions
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14
Software/VNA_embedded/Application/Drivers/Exti.cpp
View file

@ -11,13 +11,13 @@ static constexpr uint8_t MaxEntries = 16;
static Entry entries[MaxEntries];
void Exti::Init() {
HAL_NVIC_SetPriority(EXTI0_IRQn, 1, 0);
HAL_NVIC_SetPriority(EXTI1_IRQn, 1, 0);
HAL_NVIC_SetPriority(EXTI2_IRQn, 1, 0);
HAL_NVIC_SetPriority(EXTI3_IRQn, 1, 0);
HAL_NVIC_SetPriority(EXTI4_IRQn, 1, 0);
HAL_NVIC_SetPriority(EXTI9_5_IRQn, 1, 0);
HAL_NVIC_SetPriority(EXTI15_10_IRQn, 1, 0);
HAL_NVIC_SetPriority(EXTI0_IRQn, 5, 0);
HAL_NVIC_SetPriority(EXTI1_IRQn, 5, 0);
HAL_NVIC_SetPriority(EXTI2_IRQn, 5, 0);
HAL_NVIC_SetPriority(EXTI3_IRQn, 5, 0);
HAL_NVIC_SetPriority(EXTI4_IRQn, 5, 0);
HAL_NVIC_SetPriority(EXTI9_5_IRQn, 5, 0);
HAL_NVIC_SetPriority(EXTI15_10_IRQn, 5, 0);
HAL_NVIC_EnableIRQ(EXTI0_IRQn);
HAL_NVIC_EnableIRQ(EXTI1_IRQn);
HAL_NVIC_EnableIRQ(EXTI2_IRQn);

36
Software/VNA_embedded/Application/Drivers/FPGA.cpp → Software/VNA_embedded/Application/Drivers/FPGA/FPGA.cpp
View file

@ -2,42 +2,18 @@
#include "delay.hpp"
#include "stm.hpp"
#include "main.h"
#include "FPGA_HAL.hpp"
#define LOG_LEVEL LOG_LEVEL_DEBUG
#define LOG_MODULE "FPGA"
#include "Log.h"
#define FPGA_SPI hspi1
#define CONFIGURATION_SPI hspi2
extern SPI_HandleTypeDef FPGA_SPI, CONFIGURATION_SPI;
using GPIO = struct {
GPIO_TypeDef *gpio;
uint16_t pin;
};
static constexpr GPIO CS = {.gpio = FPGA_CS_GPIO_Port, .pin = FPGA_CS_Pin};
static constexpr GPIO PROGRAM_B = {.gpio = FPGA_PROGRAM_B_GPIO_Port, .pin = FPGA_PROGRAM_B_Pin};
static constexpr GPIO INIT_B = {.gpio = FPGA_INIT_B_GPIO_Port, .pin = FPGA_INIT_B_Pin};
static constexpr GPIO DONE = {.gpio = FPGA_DONE_GPIO_Port, .pin = FPGA_DONE_Pin};
static constexpr GPIO FPGA_RESET = {.gpio = FPGA_RESET_GPIO_Port, .pin = FPGA_RESET_Pin};
static constexpr GPIO AUX1 = {.gpio = FPGA_AUX1_GPIO_Port, .pin = FPGA_AUX1_Pin};
static constexpr GPIO AUX2 = {.gpio = FPGA_AUX2_GPIO_Port, .pin = FPGA_AUX2_Pin};
static constexpr GPIO AUX3 = {.gpio = FPGA_AUX3_GPIO_Port, .pin = FPGA_AUX3_Pin};
static inline void Low(GPIO g) {
g.gpio->BSRR = g.pin << 16;
}
static inline void High(GPIO g) {
g.gpio->BSRR = g.pin;
}
bool isHigh(GPIO g) {
return g.gpio->IDR & g.pin;
}
static FPGA::HaltedCallback halted_cb;
static uint16_t SysCtrlReg = 0x0000;
static uint16_t ISRMaskReg = 0x0000;
using namespace FPGAHAL;
void WriteRegister(FPGA::Reg reg, uint16_t value) {
uint16_t cmd[2] = {(uint16_t) (0x8000 | (uint16_t) reg), value};
Low(CS);
@ -46,6 +22,12 @@ void WriteRegister(FPGA::Reg reg, uint16_t value) {
}
bool FPGA::Configure(Flash *f, uint32_t start_address, uint32_t bitstream_size) {
if(!PROGRAM_B.gpio) {
LOG_WARN("PROGRAM_B not defined, assuming FPGA configures itself in master configuration");
// wait too allow enough time for FPGA configuration
HAL_Delay(2000);
return true;
}
LOG_INFO("Loading bitstream of size %lu...", bitstream_size);
Low(PROGRAM_B);
while(isHigh(INIT_B));

0
Software/VNA_embedded/Application/Drivers/FPGA.hpp → Software/VNA_embedded/Application/Drivers/FPGA/FPGA.hpp
View file

43
Software/VNA_embedded/Application/Drivers/FPGA/FPGA_HAL.hpp Normal file
View file

@ -0,0 +1,43 @@
#pragma once
#include "stm.hpp"
#include "main.h"
#define FPGA_SPI hspi1
#define CONFIGURATION_SPI hspi2
extern SPI_HandleTypeDef FPGA_SPI, CONFIGURATION_SPI;
namespace FPGAHAL {
using GPIO = struct {
GPIO_TypeDef *gpio;
uint16_t pin;
};
static constexpr GPIO CS = {.gpio = FPGA_CS_GPIO_Port, .pin = FPGA_CS_Pin};
static constexpr GPIO PROGRAM_B = {.gpio = FPGA_PROGRAM_B_GPIO_Port, .pin = FPGA_PROGRAM_B_Pin};
static constexpr GPIO INIT_B = {.gpio = FPGA_INIT_B_GPIO_Port, .pin = FPGA_INIT_B_Pin};
static constexpr GPIO DONE = {.gpio = FPGA_DONE_GPIO_Port, .pin = FPGA_DONE_Pin};
static constexpr GPIO FPGA_RESET = {.gpio = FPGA_RESET_GPIO_Port, .pin = FPGA_RESET_Pin};
static constexpr GPIO AUX1 = {.gpio = FPGA_AUX1_GPIO_Port, .pin = FPGA_AUX1_Pin};
static constexpr GPIO AUX2 = {.gpio = FPGA_AUX2_GPIO_Port, .pin = FPGA_AUX2_Pin};
static constexpr GPIO AUX3 = {.gpio = FPGA_AUX3_GPIO_Port, .pin = FPGA_AUX3_Pin};
static inline void Low(GPIO g) {
if(g.gpio) {
g.gpio->BSRR = g.pin << 16;
}
}
static inline void High(GPIO g) {
if(g.gpio) {
g.gpio->BSRR = g.pin;
}
}
bool isHigh(GPIO g) {
if(g.gpio) {
return g.gpio->IDR & g.pin;
} else {
return false;
}
}
}