WIP: device synchronization

FPGA/Generator/ipcore_dir/PLL.ucf

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+# file: PLL.ucf
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
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+# rights to the materials distributed herewith. Except as
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+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
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+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+# Input clock periods. These duplicate the values entered for the
+#  input clocks. You can use these to time your system
+#----------------------------------------------------------------
+NET "CLK_IN1" TNM_NET = "CLK_IN1";
+TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 62.5 ns HIGH 50% INPUT_JITTER 625.0ps;
+
+
+# FALSE PATH constraints 
+PIN "RESET" TIG;
+