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WIP: device synchronization

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Jan Käberich 2022-08-07 03:01:22 +02:00
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Documentation/DeveloperInfo/FPGA_protocol.pdf
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Documentation/DeveloperInfo/FPGA_protocol.tex
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@ -65,12 +65,17 @@ MOSI & in & MOSI for SPI communication/MOSI for PLL communication\\
MISO & out & MISO for SPI communication/MUX for PLL communication\\
NSS & in & Chip Select for SPI communication/LE for PLL communication\\
INTR & out & Active high interrupt indicator\\
RESET & in & FPGA reset\\
RESET\footnotemark & in & FPGA reset\\
AUX1 & in & Selector for direct communication with Source PLL\\
AUX2 & in & Selector for direct communication with LO PLL\\
AUX3 & in & Active low sweep enable. Has to be high when changing settings\\
Trigger In\footnotemark & in & Trigger input for synchronization across devices\\
Trigger Out\footnotemark & Out & Trigger output for synchronization across devices\\
\end{tabular}
\end{center}
\footnotetext[1]{Reset is named "MCU\_FPGA\_UNUSED1" in the schematic as this is a later software addition}
\footnotetext[2]{Trigger In is named "MCU\_FPGA\_UNUSED2" in the schematic as this is a later software addition}
\footnotetext[3]{Trigger Out is named "MCU\_FPGA\_UNUSED3" in the schematic as this is a later software addition}
Depending on the voltage on AUX1/AUX2 the SPI port controls either the FPGA or one of the MAX2871 PLLs:
\begin{center}
\begin{tabular}{ c|c|c }
@ -415,7 +420,7 @@ Each point in the sweep is done in stages. Each stage consists of (optionally) r
\begin{tikzpicture}
\bitrect{16}{16-\bit}
\rwbits{0}{3}{Stages}
\rwbits{3}{1}{IH}
\rwbits{3}{1}{SYNC}
\robits{4}{6}{reserved}
\rwbits{10}{3}{Port 1 stage}
\rwbits{13}{3}{Port 2 stage}
@ -423,7 +428,7 @@ Each point in the sweep is done in stages. Each stage consists of (optionally) r
\end{center}
\begin{itemize}
\item \textbf{Stages} Number of stages per point - 1. Normally the number of stages is equal to the number of ports but it can also be less (e.g. if only S11 is measured).
\item \textbf{IH:} Individual halt: Sets the behavior of the "halt sweep" bit (see section~\ref{sweepconfig}). If 1, the sampling is halted before each stage. If 0, the sampling is only halted before the point and all stages are executed without additional halts inbetween.
\item \textbf{SYNC:} Enables synchronization mode (see section~\ref{synchronization}).
\item \textbf{Port 1 stage} Number of stage during which the source signal is routed to port 1. Must not have the same value as Port 2 stage.
\item \textbf{Port 2 stage} Number of stage during which the source signal is routed to port 2. Must not have the same value as Port 1 stage.
\end{itemize}
@ -715,4 +720,37 @@ Each point in the sweep generates a sampling results for each stage (see section
\end{tikzpicture}
\end{center}
\section{Synchronization}
\label{synchronization}
The FPGA supports synchronization of the sweep across multiple devices. This feature can be enabled by setting the SYNC bit in the sweep setup register (see section~\ref{reg:sweepsetup}). When enabled, the following conditions must be met:
\begin{itemize}
\item All participating devices must be connected in a loop via the trigger input and output pins. The order of the devices is not important.
\item All devices must use the same sweep settings with the exception of the "Port 1 stage" and "Port 2 stage" settings in the sweep setup register.
\item The port stages must be configured in such a way, that for each stage exactly one port is active in one device.
\end{itemize}
The synchronization works by delaying sampling until the stimulus signal is present, even when generated by another device. For each sampling stage, performs the following steps:
\begin{itemize}
\item When the device generates the stimulus signal in the current phase:
\begin{itemize}
\item Set up source and 1.LO PLLs
\item If applicable: wait for the "resume sweep" command
\item Set the trigger output to high
\item Wait for high level on trigger input
\item Sample ADCs
\item Set the trigger output to low
\item Wait for low level on trigger input
\end{itemize}
\item When the device does not generate the stimulus signal in the current phase:
\begin{itemize}
\item Set 1.LO PLL
\item If applicable: wait for the "resume sweep" command
\item Wait for high level on trigger input
\item Set trigger output to high
\item Sample ADCs
\item Wait for low level on trigger input
\item Set the trigger output to low
\end{itemize}
\end{itemize}
\end{document}