jankae/LibreVNA
1
0
Fork 0
mirror of https://github.com/jankae/LibreVNA.git synced 2026-04-06 06:53:37 +00:00
Code Issues Projects Releases Packages Wiki Activity

mitigation for peaks caused by limited fractional divider in PLLs

Browse source
This commit is contained in:
Jan Käberich 2020-09-20 10:13:06 +02:00
parent fc3ce7a828
commit 57b4ebfb26
23 changed files with 654 additions and 274 deletions
Download patch file Download diff file Expand all files Collapse all files

3
Software/VNA_embedded/Application/Drivers/max2871.cpp
View file

@ -39,6 +39,9 @@ bool MAX2871::Init(uint32_t f_ref, bool doubler, uint16_t r, bool div2) {
// automatically switch to integer mode if F = 0
regs[5] |= (1UL << 24);
// recommended phase setting
regs[1] |= (1UL << 15);
SetMode(Mode::LowSpur2);
// for all other CP modes the PLL reports unlock condition (output signal appears to be locked)
SetCPMode(CPMode::CP20);