mitigation for peaks caused by limited fractional divider in PLLs

This commit is contained in:
Jan Käberich 2020-09-20 10:13:06 +02:00
parent fc3ce7a828
commit 57b4ebfb26
23 changed files with 654 additions and 274 deletions

View file

@ -3,6 +3,7 @@
#include "usbd_core.h"
USBD_HandleTypeDef hUsbDeviceFS;
extern PCD_HandleTypeDef hpcd_USB_FS;
#define EP_DATA_IN_ADDRESS 0x81
#define EP_DATA_OUT_ADDRESS 0x01
@ -186,7 +187,9 @@ void usb_init(usbd_callback_t callback) {
USBD_Init(&hUsbDeviceFS, &FS_Desc, 0);
USBD_RegisterClass(&hUsbDeviceFS, &USBD_ClassDriver);
USBD_Start(&hUsbDeviceFS);
HAL_NVIC_EnableIRQ(USB_HP_IRQn);
HAL_NVIC_SetPriority(USB_HP_IRQn, 6, 0);
HAL_NVIC_EnableIRQ(USB_HP_IRQn);
HAL_NVIC_SetPriority(USB_LP_IRQn, 6, 0);
HAL_NVIC_EnableIRQ(USB_LP_IRQn);
}
@ -217,3 +220,12 @@ void usb_log(const char *log, uint16_t length) {
// still busy, unable to send log
}
}
void USB_HP_IRQHandler(void)
{
HAL_PCD_IRQHandler(&hpcd_USB_FS);
}
void USB_LP_IRQHandler(void)
{
HAL_PCD_IRQHandler(&hpcd_USB_FS);
}

View file

@ -39,6 +39,9 @@ bool MAX2871::Init(uint32_t f_ref, bool doubler, uint16_t r, bool div2) {
// automatically switch to integer mode if F = 0
regs[5] |= (1UL << 24);
// recommended phase setting
regs[1] |= (1UL << 15);
SetMode(Mode::LowSpur2);
// for all other CP modes the PLL reports unlock condition (output signal appears to be locked)
SetCPMode(CPMode::CP20);