mirror of
https://github.com/jankae/LibreVNA.git
synced 2026-04-04 22:17:31 +00:00
mitigation for peaks caused by limited fractional divider in PLLs
This commit is contained in:
Jan Käberich
parent
fc3ce7a828
commit
57b4ebfb26
23 changed files with 654 additions and 274 deletions
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@ -176,6 +176,7 @@ static Protocol::SweepSettings DecodeSweepSettings(uint8_t *buf) {
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e.get<int16_t>(d.cdbm_excitation);
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d.excitePort1 = e.getBits(1);
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d.excitePort2 = e.getBits(1);
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d.suppressPeaks = e.getBits(1);
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return d;
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}
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static int16_t EncodeSweepSettings(Protocol::SweepSettings d, uint8_t *buf,
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@ -188,6 +189,7 @@ static int16_t EncodeSweepSettings(Protocol::SweepSettings d, uint8_t *buf,
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e.add<int16_t>(d.cdbm_excitation);
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e.addBits(d.excitePort1, 1);
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e.addBits(d.excitePort2, 1);
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e.addBits(d.suppressPeaks, 1);
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return e.getSize();
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}
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@ -23,6 +23,7 @@ using SweepSettings = struct _sweepSettings {
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int16_t cdbm_excitation; // in 1/100 dbm
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uint8_t excitePort1:1;
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uint8_t excitePort2:1;
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uint8_t suppressPeaks:1;
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};
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using ReferenceSettings = struct _referenceSettings {
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@ -3,6 +3,7 @@
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#include "usbd_core.h"
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USBD_HandleTypeDef hUsbDeviceFS;
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extern PCD_HandleTypeDef hpcd_USB_FS;
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#define EP_DATA_IN_ADDRESS 0x81
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#define EP_DATA_OUT_ADDRESS 0x01
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@ -186,7 +187,9 @@ void usb_init(usbd_callback_t callback) {
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USBD_Init(&hUsbDeviceFS, &FS_Desc, 0);
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USBD_RegisterClass(&hUsbDeviceFS, &USBD_ClassDriver);
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USBD_Start(&hUsbDeviceFS);
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HAL_NVIC_EnableIRQ(USB_HP_IRQn);
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HAL_NVIC_SetPriority(USB_HP_IRQn, 6, 0);
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HAL_NVIC_EnableIRQ(USB_HP_IRQn);
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HAL_NVIC_SetPriority(USB_LP_IRQn, 6, 0);
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HAL_NVIC_EnableIRQ(USB_LP_IRQn);
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}
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@ -217,3 +220,12 @@ void usb_log(const char *log, uint16_t length) {
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// still busy, unable to send log
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}
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}
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void USB_HP_IRQHandler(void)
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{
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HAL_PCD_IRQHandler(&hpcd_USB_FS);
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}
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void USB_LP_IRQHandler(void)
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{
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HAL_PCD_IRQHandler(&hpcd_USB_FS);
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}
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@ -39,6 +39,9 @@ bool MAX2871::Init(uint32_t f_ref, bool doubler, uint16_t r, bool div2) {
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// automatically switch to integer mode if F = 0
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regs[5] |= (1UL << 24);
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// recommended phase setting
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regs[1] |= (1UL << 15);
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SetMode(Mode::LowSpur2);
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// for all other CP modes the PLL reports unlock condition (output signal appears to be locked)
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SetCPMode(CPMode::CP20);
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@ -92,9 +92,9 @@ bool HW::Init(WorkRequest wr) {
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Si5351.Disable(SiChannel::ReferenceOut);
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// Both MAX2871 get a 100MHz reference
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Si5351.SetCLK(SiChannel::Source, 100000000, Si5351C::PLL::A, Si5351C::DriveStrength::mA2);
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Si5351.SetCLK(SiChannel::Source, HW::PLLRef, Si5351C::PLL::A, Si5351C::DriveStrength::mA2);
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Si5351.Enable(SiChannel::Source);
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Si5351.SetCLK(SiChannel::LO1, 100000000, Si5351C::PLL::A, Si5351C::DriveStrength::mA2);
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Si5351.SetCLK(SiChannel::LO1, HW::PLLRef, Si5351C::PLL::A, Si5351C::DriveStrength::mA2);
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Si5351.Enable(SiChannel::LO1);
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// 16MHz FPGA clock
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Si5351.SetCLK(SiChannel::FPGA, 16000000, Si5351C::PLL::A, Si5351C::DriveStrength::mA2);
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@ -133,7 +133,7 @@ bool HW::Init(WorkRequest wr) {
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// enable source synthesizer
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FPGA::Enable(FPGA::Periphery::SourceChip);
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FPGA::SetMode(FPGA::Mode::SourcePLL);
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Source.Init(100000000, false, 1, false);
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Source.Init(HW::PLLRef, false, 1, false);
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Source.SetPowerOutA(MAX2871::Power::n4dbm);
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// output B is not used
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Source.SetPowerOutB(MAX2871::Power::n4dbm, false);
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@ -150,7 +150,7 @@ bool HW::Init(WorkRequest wr) {
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FPGA::Disable(FPGA::Periphery::SourceChip);
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FPGA::Enable(FPGA::Periphery::LO1Chip);
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FPGA::SetMode(FPGA::Mode::LOPLL);
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LO1.Init(100000000, false, 1, false);
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LO1.Init(HW::PLLRef, false, 1, false);
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LO1.SetPowerOutA(MAX2871::Power::n4dbm);
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LO1.SetPowerOutB(MAX2871::Power::n4dbm);
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if(!LO1.BuildVCOMap()) {
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@ -6,8 +6,11 @@
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namespace HW {
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static constexpr uint32_t ADCSamplerate = 914000;
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static constexpr uint32_t IF1 = 60100000;
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static constexpr uint32_t IF1 = 60000000;
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static constexpr uint32_t IF2 = 250000;
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static constexpr uint32_t LO1_minFreq = 25000000;
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static constexpr uint32_t MaxSamples = 130944;
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static constexpr uint32_t PLLRef = 100000000;
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enum class Mode {
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Idle,
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@ -18,6 +18,7 @@ static uint32_t sampleNum;
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static Protocol::PacketInfo p;
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static bool active = false;
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static uint32_t lastLO2;
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static uint32_t actualRBW;
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static float port1Measurement, port2Measurement;
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@ -40,20 +41,42 @@ static void StartNextSample() {
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FPGA::WriteRegister(FPGA::Reg::PhaseIncrement, 1120);
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break;
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case 1:
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// Shift first LO to other side
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LO1freq = freq - HW::IF1;
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LO2freq = HW::IF1 - HW::IF2;
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break;
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// Shift first LO to other side
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// depending on the measurement frequency this is not possible or additive mixing has to be used
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if(freq >= HW::IF1 + HW::LO1_minFreq) {
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// frequency is high enough to shift 1.LO below measurement frequency
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LO1freq = freq - HW::IF1;
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break;
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} else if(freq <= HW::IF1 - HW::LO1_minFreq) {
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// frequency is low enough to add 1.LO to measurement frequency
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LO1freq = HW::IF1 - freq;
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break;
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}
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// unable to reach required frequency with 1.LO, skip this signal ID step
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signalIDstep++;
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/* no break */
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case 2:
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// Shift both LOs to other side
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LO1freq = freq + HW::IF1;
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LO2freq = HW::IF1 + HW::IF2;
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break;
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case 3:
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// Shift second LO to other side
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LO1freq = freq - HW::IF1;
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LO2freq = HW::IF1 + HW::IF2;
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break;
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// Shift second LO to other side
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// depending on the measurement frequency this is not possible or additive mixing has to be used
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if(freq >= HW::IF1 + HW::LO1_minFreq) {
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// frequency is high enough to shift 1.LO below measurement frequency
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LO1freq = freq - HW::IF1;
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break;
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} else if(freq <= HW::IF1 - HW::LO1_minFreq) {
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// frequency is low enough to add 1.LO to measurement frequency
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LO1freq = HW::IF1 - freq;
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break;
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}
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// unable to reach required frequency with 1.LO, skip this signal ID step
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signalIDstep++;
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/* no break */
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case 4:
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// Use default frequencies with different ADC samplerate to remove images in final IF
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LO1freq = freq + HW::IF1;
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@ -66,7 +89,7 @@ static void StartNextSample() {
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int32_t LO1deviation = (int64_t) LO1.GetActualFrequency() - LO1freq;
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LO2freq += LO1deviation;
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// only adjust LO2 PLL if necessary (if the deviation is significantly less than the RBW it does not matter)
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if((uint32_t) abs(LO2freq - lastLO2) > s.RBW / 2) {
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if((uint32_t) abs(LO2freq - lastLO2) > actualRBW / 2) {
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Si5351.SetCLK(SiChannel::Port1LO2, LO2freq, Si5351C::PLL::B, Si5351C::DriveStrength::mA2);
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Si5351.SetCLK(SiChannel::Port2LO2, LO2freq, Si5351C::PLL::B, Si5351C::DriveStrength::mA2);
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lastLO2 = LO2freq;
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@ -88,19 +111,23 @@ void SA::Setup(Protocol::SpectrumAnalyzerSettings settings) {
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// in almost all cases a full sweep requires more points than the FPGA can handle at a time
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// individually start each point and do the sweep in the uC
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FPGA::SetNumberOfPoints(1);
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// calculate amount of required points
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points = 2 * (s.f_stop - s.f_start) / s.RBW;
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// adjust to integer multiple of requested result points (in order to have the same amount of measurements in each bin)
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points += s.pointNum - points % s.pointNum;
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binSize = points / s.pointNum;
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LOG_DEBUG("%u displayed points, resulting in %lu points and bins of size %u", s.pointNum, points, binSize);
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// calculate required samples per measurement for requested RBW
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// see https://www.tek.com/blog/window-functions-spectrum-analyzers for window factors
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constexpr float window_factors[4] = {0.89f, 2.23f, 1.44f, 3.77f};
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sampleNum = HW::ADCSamplerate * window_factors[s.WindowType] / s.RBW;
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// round up to next multiple of 128
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sampleNum += 128 - sampleNum%128;
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if(sampleNum >= HW::MaxSamples) {
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sampleNum = HW::MaxSamples;
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}
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actualRBW = HW::ADCSamplerate * window_factors[s.WindowType] / sampleNum;
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FPGA::SetSamplesPerPoint(sampleNum);
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// calculate amount of required points
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points = 2 * (s.f_stop - s.f_start) / actualRBW;
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// adjust to integer multiple of requested result points (in order to have the same amount of measurements in each bin)
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points += s.pointNum - points % s.pointNum;
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binSize = points / s.pointNum;
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LOG_DEBUG("%u displayed points, resulting in %lu points and bins of size %u", s.pointNum, points, binSize);
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// set initial state
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pointCnt = 0;
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// enable the required hardware resources
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@ -14,10 +14,6 @@
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#define LOG_MODULE "VNA"
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#include "Log.h"
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static constexpr uint32_t IF1 = 60100000;
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static constexpr uint32_t IF1_alternate = 57000000;
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static constexpr uint32_t IF2 = 250000;
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static VNA::SweepCallback sweepCallback;
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static Protocol::SweepSettings settings;
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static uint16_t pointCnt;
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@ -27,11 +23,10 @@ static bool active = false;
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using IFTableEntry = struct {
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uint16_t pointCnt;
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uint32_t IF1;
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uint8_t clkconfig[8];
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};
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static constexpr uint16_t IFTableNumEntries = 100;
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static constexpr uint16_t IFTableNumEntries = 500;
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static IFTableEntry IFTable[IFTableNumEntries];
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static uint16_t IFTableIndexCnt = 0;
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@ -58,6 +53,7 @@ bool VNA::Setup(Protocol::SweepSettings s, SweepCallback cb) {
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uint32_t samplesPerPoint = (HW::ADCSamplerate / s.if_bandwidth);
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// round up to next multiple of 128 (128 samples are spread across 35 IF2 periods)
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samplesPerPoint = ((uint32_t) ((samplesPerPoint + 127) / 128)) * 128;
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uint32_t actualBandwidth = HW::ADCSamplerate / samplesPerPoint;
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// has to be one less than actual number of samples
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FPGA::SetSamplesPerPoint(samplesPerPoint);
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@ -70,89 +66,82 @@ bool VNA::Setup(Protocol::SweepSettings s, SweepCallback cb) {
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attenuator = (-1000 - s.cdbm_excitation) / 25;
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}
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uint32_t last_IF1 = IF1;
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uint32_t last_LO2 = HW::IF1 - HW::IF2;
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Si5351.SetCLK(SiChannel::Port1LO2, last_LO2, Si5351C::PLL::B, Si5351C::DriveStrength::mA2);
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Si5351.SetCLK(SiChannel::Port2LO2, last_LO2, Si5351C::PLL::B, Si5351C::DriveStrength::mA2);
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Si5351.SetCLK(SiChannel::RefLO2, last_LO2, Si5351C::PLL::B, Si5351C::DriveStrength::mA2);
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Si5351.ResetPLL(Si5351C::PLL::B);
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IFTableIndexCnt = 0;
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bool last_lowband = false;
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if(!s.suppressPeaks) {
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// invalidate first entry of IFTable, preventing switing of 2.LO in halted callback
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IFTable[0].pointCnt = 0xFFFF;
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}
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// Transfer PLL configuration to FPGA
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for (uint16_t i = 0; i < points; i++) {
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uint64_t freq = s.f_start + (s.f_stop - s.f_start) * i / (points - 1);
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// SetFrequency only manipulates the register content in RAM, no SPI communication is done.
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// No mode-switch of FPGA necessary here.
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// Check which IF frequency is a better fit
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uint32_t used_IF = IF1;
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// if (freq < 290000000) {
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// // for low frequencies the harmonics of the IF and source frequency should not be too close
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// uint32_t dist_primary;
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// if(freq < IF1) {
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// dist_primary = IF1 - freq * (IF1 / freq);
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// if (dist_primary > freq / 2) {
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// dist_primary = freq - dist_primary;
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// }
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// } else {
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// dist_primary = freq - IF1 * (freq / IF1);
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// if (dist_primary > IF1 / 2) {
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// dist_primary = IF1 - dist_primary;
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// }
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// }
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// uint32_t dist_alternate;
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// if(freq < IF1_alternate) {
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// dist_alternate = IF1_alternate - freq * (IF1_alternate / freq);
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// if (dist_alternate > freq / 2) {
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// dist_alternate = freq - dist_primary;
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// }
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// } else {
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// dist_alternate = freq - IF1_alternate * (freq / IF1_alternate);
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// if (dist_alternate > IF1_alternate / 2) {
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// dist_alternate = IF1_alternate - dist_primary;
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// }
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// }
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// if(dist_alternate > dist_primary) {
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// used_IF = IF1_alternate;
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// }
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// LOG_INFO("Distance: %lu/%lu", dist_primary, dist_alternate);
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// }
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bool needs_halt = false;
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if (used_IF != last_IF1) {
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last_IF1 = used_IF;
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LOG_INFO("Changing IF1 to %lu at point %u (f=%lu)", used_IF, i, (uint32_t) freq);
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needs_halt = true;
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if (IFTableIndexCnt >= IFTableNumEntries) {
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LOG_ERR("IF table full, unable to add new entry");
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return false;
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}
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IFTable[IFTableIndexCnt].pointCnt = i;
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IFTable[IFTableIndexCnt].IF1 = used_IF;
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// Configure LO2 for the changed IF1. This is not necessary right now but it will generate
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// the correct clock settings
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Si5351.SetCLK(SiChannel::RefLO2, used_IF + IF2, Si5351C::PLL::A, Si5351C::DriveStrength::mA2);
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// store calculated clock configuration for later change
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Si5351.ReadRawCLKConfig(1, IFTable[IFTableIndexCnt].clkconfig);
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IFTableIndexCnt++;
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}
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uint64_t actualSourceFreq;
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bool lowband = false;
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if (freq < BandSwitchFrequency) {
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needs_halt = true;
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lowband = true;
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actualSourceFreq = freq;
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} else {
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Source.SetFrequency(freq);
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actualSourceFreq = Source.GetActualFrequency();
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}
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if (last_lowband && !lowband) {
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// additional halt before first highband point to enable highband source
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needs_halt = true;
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}
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LO1.SetFrequency(freq + used_IF);
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LO1.SetFrequency(freq + HW::IF1);
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uint32_t actualFirstIF = LO1.GetActualFrequency() - actualSourceFreq;
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uint32_t actualFinalIF = actualFirstIF - last_LO2;
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uint32_t IFdeviation = abs(actualFinalIF - HW::IF2);
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bool needs_LO2_shift = false;
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if(IFdeviation > actualBandwidth / 2) {
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needs_LO2_shift = true;
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}
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if (s.suppressPeaks && needs_LO2_shift) {
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if (IFTableIndexCnt < IFTableNumEntries) {
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// still room in table
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LOG_INFO("Changing 2.LO at point %lu to reach correct 2.IF frequency");
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needs_halt = true;
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IFTable[IFTableIndexCnt].pointCnt = i;
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// Configure LO2 for the changed IF1. This is not necessary right now but it will generate
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// the correct clock settings
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last_LO2 = actualFirstIF - HW::IF2;
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Si5351.SetCLK(SiChannel::RefLO2, last_LO2,
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Si5351C::PLL::B, Si5351C::DriveStrength::mA2);
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// store calculated clock configuration for later change
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Si5351.ReadRawCLKConfig(1, IFTable[IFTableIndexCnt].clkconfig);
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IFTableIndexCnt++;
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needs_LO2_shift = false;
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}
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}
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if(needs_LO2_shift) {
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// if shift is still needed either peak suppression is disabled or no more room in IFTable was available
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LOG_WARN(
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"PLL deviation of %luHz for measurement at %lu%06luHz, will cause a peak",
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IFdeviation, (uint32_t ) (freq / 1000000), (uint32_t ) (freq % 1000000));
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}
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FPGA::WriteSweepConfig(i, lowband, Source.GetRegisters(),
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LO1.GetRegisters(), attenuator, freq, FPGA::SettlingTime::us20,
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FPGA::Samples::SPPRegister, needs_halt);
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last_lowband = lowband;
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}
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// // revert clk configuration to previous value (might have been changed in sweep calculation)
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// Si5351.SetCLK(1, IF1 + IF2, Si5351C::PLL::B, Si5351C::DriveStrength::mA2);
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// Si5351.ResetPLL(Si5351C::PLL::B);
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// revert clk configuration to previous value (might have been changed in sweep calculation)
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Si5351.SetCLK(SiChannel::RefLO2, HW::IF1 - HW::IF2, Si5351C::PLL::B, Si5351C::DriveStrength::mA2);
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Si5351.ResetPLL(Si5351C::PLL::B);
|
||||
// Enable mixers/amplifier/PLLs
|
||||
FPGA::SetWindow(FPGA::Window::None);
|
||||
FPGA::Enable(FPGA::Periphery::Port1Mixer);
|
||||
|
|
@ -249,15 +238,15 @@ void VNA::SweepHalted() {
|
|||
}
|
||||
LOG_DEBUG("Halted before point %d", pointCnt);
|
||||
// Check if IF table has entry at this point
|
||||
// if (IFTable[IFTableIndexCnt].pointCnt == pointCnt) {
|
||||
// LOG_DEBUG("Shifting IF to %lu at point %u",
|
||||
// IFTable[IFTableIndexCnt].IF1, pointCnt);
|
||||
// Si5351.WriteRawCLKConfig(1, IFTable[IFTableIndexCnt].clkconfig);
|
||||
// Si5351.WriteRawCLKConfig(4, IFTable[IFTableIndexCnt].clkconfig);
|
||||
// Si5351.WriteRawCLKConfig(5, IFTable[IFTableIndexCnt].clkconfig);
|
||||
// Si5351.ResetPLL(Si5351C::PLL::B);
|
||||
// IFTableIndexCnt++;
|
||||
// }
|
||||
if (IFTable[IFTableIndexCnt].pointCnt == pointCnt) {
|
||||
Si5351.WriteRawCLKConfig(SiChannel::Port1LO2, IFTable[IFTableIndexCnt].clkconfig);
|
||||
Si5351.WriteRawCLKConfig(SiChannel::Port2LO2, IFTable[IFTableIndexCnt].clkconfig);
|
||||
Si5351.WriteRawCLKConfig(SiChannel::RefLO2, IFTable[IFTableIndexCnt].clkconfig);
|
||||
Si5351.ResetPLL(Si5351C::PLL::B);
|
||||
IFTableIndexCnt++;
|
||||
// PLL reset causes the 2.LO to turn off briefly and then ramp on back, needs delay before next point
|
||||
Delay::us(1300);
|
||||
}
|
||||
uint64_t frequency = settings.f_start
|
||||
+ (settings.f_stop - settings.f_start) * pointCnt
|
||||
/ (settings.points - 1);
|
||||
|
|
|
|||
|
|
@ -57,8 +57,6 @@ void DMA1_Channel1_IRQHandler(void);
|
|||
void DMA1_Channel2_IRQHandler(void);
|
||||
void DMA1_Channel3_IRQHandler(void);
|
||||
void DMA1_Channel4_IRQHandler(void);
|
||||
void USB_HP_IRQHandler(void);
|
||||
void USB_LP_IRQHandler(void);
|
||||
void TIM1_TRG_COM_TIM17_IRQHandler(void);
|
||||
void UCPD1_IRQHandler(void);
|
||||
/* USER CODE BEGIN EFP */
|
||||
|
|
|
|||
|
|
@ -507,11 +507,6 @@ void HAL_PCD_MspInit(PCD_HandleTypeDef* hpcd)
|
|||
|
||||
/* Peripheral clock enable */
|
||||
__HAL_RCC_USB_CLK_ENABLE();
|
||||
/* USB interrupt Init */
|
||||
HAL_NVIC_SetPriority(USB_HP_IRQn, 6, 0);
|
||||
// HAL_NVIC_EnableIRQ(USB_HP_IRQn);
|
||||
HAL_NVIC_SetPriority(USB_LP_IRQn, 6, 0);
|
||||
// HAL_NVIC_EnableIRQ(USB_LP_IRQn);
|
||||
/* USER CODE BEGIN USB_MspInit 1 */
|
||||
|
||||
/* USER CODE END USB_MspInit 1 */
|
||||
|
|
@ -541,9 +536,6 @@ void HAL_PCD_MspDeInit(PCD_HandleTypeDef* hpcd)
|
|||
*/
|
||||
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_11|GPIO_PIN_12);
|
||||
|
||||
/* USB interrupt DeInit */
|
||||
HAL_NVIC_DisableIRQ(USB_HP_IRQn);
|
||||
HAL_NVIC_DisableIRQ(USB_LP_IRQn);
|
||||
/* USER CODE BEGIN USB_MspDeInit 1 */
|
||||
|
||||
/* USER CODE END USB_MspDeInit 1 */
|
||||
|
|
|
|||
|
|
@ -60,7 +60,6 @@
|
|||
extern DMA_HandleTypeDef hdma_spi1_rx;
|
||||
extern DMA_HandleTypeDef hdma_spi1_tx;
|
||||
extern TIM_HandleTypeDef htim1;
|
||||
extern PCD_HandleTypeDef hpcd_USB_FS;
|
||||
extern TIM_HandleTypeDef htim17;
|
||||
|
||||
/* USER CODE BEGIN EV */
|
||||
|
|
@ -219,34 +218,6 @@ void DMA1_Channel4_IRQHandler(void)
|
|||
/* USER CODE END DMA1_Channel4_IRQn 1 */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles USB high priority interrupt remap.
|
||||
*/
|
||||
void USB_HP_IRQHandler(void)
|
||||
{
|
||||
/* USER CODE BEGIN USB_HP_IRQn 0 */
|
||||
|
||||
/* USER CODE END USB_HP_IRQn 0 */
|
||||
HAL_PCD_IRQHandler(&hpcd_USB_FS);
|
||||
/* USER CODE BEGIN USB_HP_IRQn 1 */
|
||||
|
||||
/* USER CODE END USB_HP_IRQn 1 */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles USB low priority interrupt remap.
|
||||
*/
|
||||
void USB_LP_IRQHandler(void)
|
||||
{
|
||||
/* USER CODE BEGIN USB_LP_IRQn 0 */
|
||||
|
||||
/* USER CODE END USB_LP_IRQn 0 */
|
||||
HAL_PCD_IRQHandler(&hpcd_USB_FS);
|
||||
/* USER CODE BEGIN USB_LP_IRQn 1 */
|
||||
|
||||
/* USER CODE END USB_LP_IRQn 1 */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles TIM1 trigger and commutation interrupts and TIM17 global interrupt.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -165,8 +165,6 @@ NVIC.TIM1_TRG_COM_TIM17_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
|
|||
NVIC.TimeBase=TIM1_TRG_COM_TIM17_IRQn
|
||||
NVIC.TimeBaseIP=TIM17
|
||||
NVIC.UCPD1_IRQn=true\:6\:0\:true\:false\:true\:true\:true\:false
|
||||
NVIC.USB_HP_IRQn=true\:6\:0\:true\:false\:true\:true\:true\:true
|
||||
NVIC.USB_LP_IRQn=true\:6\:0\:true\:false\:true\:true\:true\:true
|
||||
NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
|
||||
PA1.GPIOParameters=GPIO_Label
|
||||
PA1.GPIO_Label=FPGA_AUX1
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue