mirror of
https://github.com/jankae/LibreVNA.git
synced 2026-04-04 14:07:30 +00:00
mitigation for peaks caused by limited fractional divider in PLLs
This commit is contained in:
Jan Käberich
parent
fc3ce7a828
commit
57b4ebfb26
23 changed files with 654 additions and 274 deletions
261
FPGA/VNA/DFT.vhd
Normal file
261
FPGA/VNA/DFT.vhd
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@ -0,0 +1,261 @@
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----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 20:38:37 09/18/2020
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-- Design Name:
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-- Module Name: DFT - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity DFT is
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Generic (BINS : integer);
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Port ( CLK : in STD_LOGIC;
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RESET : in STD_LOGIC;
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PORT1 : in STD_LOGIC_VECTOR (15 downto 0);
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PORT2 : in STD_LOGIC_VECTOR (15 downto 0);
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NEW_SAMPLE : in STD_LOGIC;
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NSAMPLES : in STD_LOGIC_VECTOR (15 downto 0);
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BIN1_PHASEINC : in STD_LOGIC_VECTOR (15 downto 0);
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DIFFBIN_PHASEINC : in STD_LOGIC_VECTOR (15 downto 0);
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WINDOW_INC : in STD_LOGIC_VECTOR (15 downto 0);
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WINDOW_TYPE : in STD_LOGIC_VECTOR (1 downto 0);
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RESULT_READY : out STD_LOGIC;
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OUTPUT : out STD_LOGIC_VECTOR (191 downto 0);
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NEXT_OUTPUT : in STD_LOGIC);
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end DFT;
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architecture Behavioral of DFT is
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COMPONENT SinCos
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PORT (
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clk : IN STD_LOGIC;
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phase_in : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
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cosine : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
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sine : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
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);
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END COMPONENT;
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COMPONENT SinCosMult
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PORT (
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clk : IN STD_LOGIC;
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a : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
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b : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
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p : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
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);
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END COMPONENT;
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COMPONENT window
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PORT(
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CLK : IN std_logic;
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INDEX : IN std_logic_vector(6 downto 0);
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WINDOW_TYPE : IN std_logic_vector(1 downto 0);
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VALUE : OUT std_logic_vector(15 downto 0)
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);
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END COMPONENT;
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type result is array(BINS-1 downto 0) of std_logic_vector(47 downto 0);
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signal port1_real : result;
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signal port1_imag : result;
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signal port2_real : result;
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signal port2_imag : result;
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signal sample_cnt : integer range 0 to 65535;
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signal bin_cnt : integer range 0 to BINS+2;
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signal output_cnt : integer range 0 to BINS-1;
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type States is (WaitingForSample, WindowingStart, WaitMult, WaitMult2, PhaseReady, WindowingReady, WaitSinCos, Busy, Ready);
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signal state : States;
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signal port1_latch : std_logic_vector(15 downto 0);
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signal port2_latch : std_logic_vector(15 downto 0);
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signal window_index : std_logic_vector(6 downto 0);
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signal window_cnt : unsigned(
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signal window_value : std_logic_vector(15 downto 0);
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signal phase : std_logic_vector(31 downto 0);
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signal phase_inc : std_logic_vector(31 downto 0);
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signal sine : std_logic_vector(15 downto 0);
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signal cosine : std_logic_vector(15 downto 0);
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signal mult1_a : std_logic_vector(15 downto 0);
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signal mult1_b : std_logic_vector(15 downto 0);
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signal mult1_p : std_logic_vector(31 downto 0);
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signal mult2_a : std_logic_vector(15 downto 0);
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signal mult2_b : std_logic_vector(15 downto 0);
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signal mult2_p : std_logic_vector(31 downto 0);
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signal mult3_a : std_logic_vector(15 downto 0);
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signal mult3_b : std_logic_vector(15 downto 0);
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signal mult3_p : std_logic_vector(31 downto 0);
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signal mult4_a : std_logic_vector(15 downto 0);
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signal mult4_b : std_logic_vector(15 downto 0);
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signal mult4_p : std_logic_vector(31 downto 0);
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begin
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LookupTable : SinCos
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PORT MAP (
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clk => CLK,
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phase_in => phase(31 downto 20),
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cosine => cosine,
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sine => sine
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);
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Mult1 : SinCosMult
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PORT MAP (
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clk => CLK,
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a => mult1_a,
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b => mult1_b,
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p => mult1_p
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);
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Mult2 : SinCosMult
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PORT MAP (
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clk => CLK,
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a => mult2_a,
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b => mult2_b,
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p => mult2_p
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);
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Mult3 : SinCosMult
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PORT MAP (
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clk => CLK,
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a => mult3_a,
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b => mult3_b,
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p => mult3_p
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);
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Mult4 : SinCosMult
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PORT MAP (
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clk => CLK,
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a => mult4_a,
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b => mult4_b,
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p => mult4_p
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);
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WindowROM: window PORT MAP(
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CLK => CLK,
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INDEX => window_index(15 downto 9),
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WINDOW_TYPE => WINDOW_TYPE,
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VALUE => window_value
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);
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process(CLK, RESET)
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begin
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if rising_edge(CLK) then
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if RESET = '1' then
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window_index <= (others => '0');
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sample_cnt <= 0;
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RESULT_READY <= '1';
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state <= WaitingForSample;
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else
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case state is
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when WaitingForSample =>
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RESULT_READY <= '1';
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OUTPUT <= port1_real(output_cnt) & port1_imag(output_cnt) & port2_real(output_cnt) & port2_imag(output_cnt);
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if NEXT_OUTPUT = '1' then
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if output_cnt < BINS - 1 then
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output_cnt <= output_cnt + 1;
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else
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output_cnt <= 0;
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end if;
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end if;
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if NEW_SAMPLE = '1' then
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-- calculate phase for initial bin
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mult1_a <= std_logic_vector(to_unsigned(sample_cnt, 16));
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mult1_b <= BIN1_PHASEINC;
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mult2_a <= std_logic_vector(to_unsigned(sample_cnt, 16));
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mult2_b <= DIFFBIN_PHASEINC;
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-- window ADC data
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mult3_a <= PORT1;
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mult3_b <= window_value;
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mult4_a <= PORT2;
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mult4_b <= window_value;
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state <= WaitMult;
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end if;
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when WaitMult =>
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RESULT_READY <= '0';
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state <= WaitMult2;
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when WaitMult2 =>
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RESULT_READY <= '0';
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state <= PhaseReady;
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when PhaseReady =>
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RESULT_READY <= '0';
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-- initial phase is ready
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phase <= mult1_p;
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phase_inc <= mult2_p;
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state <= WindowingReady;
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when WindowingReady =>
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RESULT_READY <= '0';
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phase <= std_logic_vector(unsigned(phase)+unsigned(phase_inc));
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port1_latch <= mult3_p(31 downto 16);
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port2_latch <= mult4_p(31 downto 16);
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bin_cnt <= 0;
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state <= WaitSinCos;
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when WaitSinCos =>
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phase <= std_logic_vector(unsigned(phase)+unsigned(phase_inc));
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RESULT_READY <= '0';
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if bin_cnt < 4 then
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bin_cnt <= bin_cnt + 1;
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else
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bin_cnt <= 0;
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state <= BUSY;
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end if;
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when BUSY =>
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phase <= std_logic_vector(unsigned(phase)+unsigned(phase_inc));
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mult1_a <= port1_latch;
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mult1_b <= sine;
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mult2_a <= port1_latch;
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mult2_b <= cosine;
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mult3_a <= port2_latch;
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mult3_b <= sine;
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mult4_a <= port2_latch;
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mult4_b <= cosine;
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if bin_cnt >= 3 then
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-- multiplier result is available, accumulate
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if sample_cnt = 0 then
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port1_real(bin_cnt-3) <= mult1_p;
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port1_imag(bin_cnt-3) <= mult2_p;
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port2_real(bin_cnt-3) <= mult3_p;
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port2_imag(bin_cnt-3) <= mult4_p;
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else
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port1_real(bin_cnt-3) <= std_logic_vector(unsigned(port1_real(bin_cnt-3))+unsigned(mult1_p));
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port1_imag(bin_cnt-3) <= std_logic_vector(unsigned(port1_imag(bin_cnt-3))+unsigned(mult2_p));
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port2_real(bin_cnt-3) <= std_logic_vector(unsigned(port2_real(bin_cnt-3))+unsigned(mult3_p));
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--port2_imag(bin_cnt-3) <= std_logic_vector(unsigned(port2_imag(bin_cnt-3))+unsigned(mult4_p));
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end if;
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end if;
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if bin_cnt >= BINS+2 then
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state <= WaitingForSample;
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RESULT_READY <= '1';
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sample_cnt <= sample_cnt + 1;
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window_index <= std_logic_vector(unsigned(window_index)+unsigned(WINDOW_INC));
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output_cnt <= 0;
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else
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RESULT_READY <= '0';
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bin_cnt <= bin_cnt + 1;
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end if;
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when others =>
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RESULT_READY <= '0';
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state <= WaitingForSample;
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end case;
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end if;
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end if;
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end process;
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end Behavioral;
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136
FPGA/VNA/Test_DFT.vhd
Normal file
136
FPGA/VNA/Test_DFT.vhd
Normal file
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@ -0,0 +1,136 @@
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--------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 21:25:23 09/18/2020
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-- Design Name:
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-- Module Name: /home/jan/Projekte/VNA2/FPGA/VNA/Test_DFT.vhd
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-- Project Name: VNA
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-- Target Device:
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-- Tool versions:
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-- Description:
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--
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-- VHDL Test Bench Created by ISE for module: DFT
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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-- Notes:
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-- This testbench has been automatically generated using types std_logic and
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-- std_logic_vector for the ports of the unit under test. Xilinx recommends
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-- that these types always be used for the top-level I/O of a design in order
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-- to guarantee that the testbench will bind correctly to the post-implementation
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-- simulation model.
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--------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--USE ieee.numeric_std.ALL;
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ENTITY Test_DFT IS
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END Test_DFT;
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ARCHITECTURE behavior OF Test_DFT IS
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT DFT
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GENERIC(BINS : integer);
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PORT(
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CLK : IN std_logic;
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RESET : IN std_logic;
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PORT1 : IN std_logic_vector(15 downto 0);
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PORT2 : IN std_logic_vector(15 downto 0);
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NEW_SAMPLE : IN std_logic;
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BIN1_PHASEINC : IN std_logic_vector(15 downto 0);
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DIFFBIN_PHASEINC : IN std_logic_vector(15 downto 0);
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WINDOW_INC : IN std_logic_vector(15 downto 0);
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WINDOW_TYPE : IN std_logic_vector(1 downto 0);
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RESULT_READY : OUT std_logic;
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OUTPUT : out STD_LOGIC_VECTOR (191 downto 0);
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NEXT_OUTPUT : IN std_logic
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);
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END COMPONENT;
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--Inputs
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signal CLK : std_logic := '0';
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signal RESET : std_logic := '0';
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signal PORT1 : std_logic_vector(15 downto 0) := (others => '0');
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signal PORT2 : std_logic_vector(15 downto 0) := (others => '0');
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signal NEW_SAMPLE : std_logic := '0';
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signal BIN1_PHASEINC : std_logic_vector(15 downto 0) := (others => '0');
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signal DIFFBIN_PHASEINC : std_logic_vector(15 downto 0) := (others => '0');
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signal WINDOW_INC : std_logic_vector(15 downto 0) := (others => '0');
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signal WINDOW_TYPE : std_logic_vector(1 downto 0) := (others => '0');
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signal NEXT_OUTPUT : std_logic := '0';
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--Outputs
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signal RESULT_READY : std_logic;
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signal OUTPUT : STD_LOGIC_VECTOR (191 downto 0);
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-- Clock period definitions
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constant CLK_period : time := 10 ns;
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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uut: DFT
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GENERIC MAP(BINS => 100)
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PORT MAP (
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CLK => CLK,
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RESET => RESET,
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PORT1 => PORT1,
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PORT2 => PORT2,
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NEW_SAMPLE => NEW_SAMPLE,
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BIN1_PHASEINC => BIN1_PHASEINC,
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DIFFBIN_PHASEINC => DIFFBIN_PHASEINC,
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WINDOW_INC => WINDOW_INC,
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WINDOW_TYPE => WINDOW_TYPE,
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RESULT_READY => RESULT_READY,
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OUTPUT => OUTPUT,
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NEXT_OUTPUT => NEXT_OUTPUT
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);
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-- Clock process definitions
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CLK_process :process
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begin
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CLK <= '0';
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wait for CLK_period/2;
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CLK <= '1';
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wait for CLK_period/2;
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end process;
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-- Stimulus process
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stim_proc: process
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begin
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-- hold reset state for 100 ns.
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RESET <= '1';
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PORT1 <= "1000000000000000";
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PORT2 <= "0100000000000000";
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BIN1_PHASEINC <= "0100000000000000";
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DIFFBIN_PHASEINC <= "0010000000000000";
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WINDOW_INC <= "0000100000000000";
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wait for 100 ns;
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RESET <= '0';
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wait for CLK_period*10;
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NEW_SAMPLE <= '1';
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wait for CLK_period;
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NEW_SAMPLE <= '0';
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--wait until RESULT_READY = '1';
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wait for CLK_period*112;
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NEW_SAMPLE <= '1';
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wait for CLK_period;
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NEW_SAMPLE <= '0';
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-- insert stimulus here
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wait;
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end process;
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END;
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@ -26,6 +26,7 @@
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<file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="MCP33131.vhi"/>
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<file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="ResetDelay.vhi"/>
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<file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="SPICommands.vhi"/>
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<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="SPICommands_isim_beh.exe"/>
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<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="Sampling.cmd_log"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="Sampling.lso"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="Sampling.prj"/>
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|
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@ -37,10 +38,11 @@
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<file xil_pn:fileType="FILE_XRPT" xil_pn:name="Sampling_xst.xrpt"/>
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<file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="Sweep.vhi"/>
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<file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="Synchronizer.vhi"/>
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<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="Test_DFT_beh.prj"/>
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<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_DFT_isim_beh.exe"/>
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<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="Test_DFT_isim_beh.wdb"/>
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<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_MAX2871_isim_beh.exe"/>
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<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="Test_MCP33131_beh.prj"/>
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<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_MCP33131_isim_beh.exe"/>
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<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="Test_MCP33131_isim_beh.wdb"/>
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<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_PLL_isim_beh.exe"/>
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<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_SPICommands_isim_beh.exe"/>
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<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_SPI_isim_beh.exe"/>
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|
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@ -60,7 +62,6 @@
|
|||
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
|
||||
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
|
||||
<file xil_pn:fileType="FILE_LOG" xil_pn:name="fuse.log"/>
|
||||
<file xil_pn:fileType="FILE_LOG" xil_pn:name="ipcore_dir/coregen.log"/>
|
||||
<file xil_pn:fileType="FILE_CMD" xil_pn:name="ise_impact.cmd"/>
|
||||
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
|
||||
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/>
|
||||
|
|
@ -124,106 +125,70 @@
|
|||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1600358010" xil_pn:in_ck="6180625018917402544" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1600358010">
|
||||
<transform xil_pn:end_ts="1600501620" xil_pn:in_ck="-6581597313105561379" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1600501620">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="OutOfDateForOutputs"/>
|
||||
<status xil_pn:value="InputAdded"/>
|
||||
<status xil_pn:value="InputChanged"/>
|
||||
<status xil_pn:value="InputRemoved"/>
|
||||
<status xil_pn:value="OutputRemoved"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1600461368" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-5354180755060525133" xil_pn:start_ts="1600461368">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1600461368" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="4601062479098204721" xil_pn:start_ts="1600461368">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1600501224" xil_pn:in_ck="-6615228739331305497" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1600501223">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="OutOfDateForOutputs"/>
|
||||
<status xil_pn:value="InputAdded"/>
|
||||
<status xil_pn:value="InputChanged"/>
|
||||
<status xil_pn:value="InputRemoved"/>
|
||||
<status xil_pn:value="OutputChanged"/>
|
||||
<outfile xil_pn:name="MAX2871.vhd"/>
|
||||
<outfile xil_pn:name="MCP33131.vhd"/>
|
||||
<outfile xil_pn:name="ResetDelay.vhd"/>
|
||||
<outfile xil_pn:name="SPIConfig.vhd"/>
|
||||
<outfile xil_pn:name="Sampling.vhd"/>
|
||||
<outfile xil_pn:name="Sweep.vhd"/>
|
||||
<outfile xil_pn:name="Synchronizer.vhd"/>
|
||||
<outfile xil_pn:name="Test_MAX2871.vhd"/>
|
||||
<outfile xil_pn:name="Test_MCP33131.vhd"/>
|
||||
<outfile xil_pn:name="Test_PLL.vhd"/>
|
||||
<outfile xil_pn:name="Test_SPI.vhd"/>
|
||||
<outfile xil_pn:name="Test_SPICommands.vhd"/>
|
||||
<outfile xil_pn:name="Test_Sampling.vhd"/>
|
||||
<outfile xil_pn:name="Test_SinCos.vhd"/>
|
||||
<outfile xil_pn:name="Test_Sync.vhd"/>
|
||||
<outfile xil_pn:name="Test_Window.vhd"/>
|
||||
<outfile xil_pn:name="spi_slave.vhd"/>
|
||||
<outfile xil_pn:name="top.vhd"/>
|
||||
<outfile xil_pn:name="window.vhd"/>
|
||||
<status xil_pn:value="OutputRemoved"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1600358010" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-1206566934435318832" xil_pn:start_ts="1600358010">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1600358010" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-273551377395144626" xil_pn:start_ts="1600358010">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1600256363" xil_pn:in_ck="-6165752171532536899" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1600256363">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<outfile xil_pn:name="ipcore_dir/PLL.vhd"/>
|
||||
<outfile xil_pn:name="ipcore_dir/SinCos.ngc"/>
|
||||
<outfile xil_pn:name="ipcore_dir/SinCos.vhd"/>
|
||||
<outfile xil_pn:name="ipcore_dir/SinCosMult.ngc"/>
|
||||
<outfile xil_pn:name="ipcore_dir/SinCosMult.vhd"/>
|
||||
<outfile xil_pn:name="ipcore_dir/SweepConfigMem.ngc"/>
|
||||
<outfile xil_pn:name="ipcore_dir/SweepConfigMem.vhd"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1600358010" xil_pn:in_ck="6180625018917402544" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1600358010">
|
||||
<transform xil_pn:end_ts="1600461349" xil_pn:in_ck="-760725241865927573" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1600461349">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
<status xil_pn:value="OutOfDateForOutputs"/>
|
||||
<status xil_pn:value="InputAdded"/>
|
||||
<status xil_pn:value="InputChanged"/>
|
||||
<status xil_pn:value="InputRemoved"/>
|
||||
<status xil_pn:value="OutputChanged"/>
|
||||
<outfile xil_pn:name="MAX2871.vhd"/>
|
||||
<outfile xil_pn:name="MCP33131.vhd"/>
|
||||
<outfile xil_pn:name="ResetDelay.vhd"/>
|
||||
<outfile xil_pn:name="SPIConfig.vhd"/>
|
||||
<outfile xil_pn:name="Sampling.vhd"/>
|
||||
<outfile xil_pn:name="Sweep.vhd"/>
|
||||
<outfile xil_pn:name="Synchronizer.vhd"/>
|
||||
<outfile xil_pn:name="Test_MAX2871.vhd"/>
|
||||
<outfile xil_pn:name="Test_MCP33131.vhd"/>
|
||||
<outfile xil_pn:name="Test_PLL.vhd"/>
|
||||
<outfile xil_pn:name="Test_SPI.vhd"/>
|
||||
<outfile xil_pn:name="Test_SPICommands.vhd"/>
|
||||
<outfile xil_pn:name="Test_Sampling.vhd"/>
|
||||
<outfile xil_pn:name="Test_SinCos.vhd"/>
|
||||
<outfile xil_pn:name="Test_Sync.vhd"/>
|
||||
<outfile xil_pn:name="Test_Window.vhd"/>
|
||||
<outfile xil_pn:name="spi_slave.vhd"/>
|
||||
<outfile xil_pn:name="top.vhd"/>
|
||||
<outfile xil_pn:name="window.vhd"/>
|
||||
<status xil_pn:value="OutputRemoved"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1600358012" xil_pn:in_ck="3204048457877733613" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-3530939538078141760" xil_pn:start_ts="1600358010">
|
||||
<transform xil_pn:end_ts="1600461373" xil_pn:in_ck="-7092619378539932792" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-5642200015192194106" xil_pn:start_ts="1600461368">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="OutOfDateForProperties"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
<status xil_pn:value="OutOfDateForOutputs"/>
|
||||
<status xil_pn:value="InputAdded"/>
|
||||
<status xil_pn:value="InputChanged"/>
|
||||
<status xil_pn:value="InputRemoved"/>
|
||||
<status xil_pn:value="OutputChanged"/>
|
||||
<outfile xil_pn:name="Test_MCP33131_beh.prj"/>
|
||||
<outfile xil_pn:name="Test_MCP33131_isim_beh.exe"/>
|
||||
<outfile xil_pn:name="fuse.log"/>
|
||||
<outfile xil_pn:name="isim"/>
|
||||
<outfile xil_pn:name="isim.log"/>
|
||||
<outfile xil_pn:name="xilinxsim.ini"/>
|
||||
<status xil_pn:value="OutputRemoved"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1600358012" xil_pn:in_ck="-6256802959996678011" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="6352116336892055917" xil_pn:start_ts="1600358012">
|
||||
<transform xil_pn:end_ts="1600461373" xil_pn:in_ck="-3358899429776077154" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-8724408846642916045" xil_pn:start_ts="1600461373">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="OutOfDateForProperties"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
<status xil_pn:value="OutOfDateForOutputs"/>
|
||||
<status xil_pn:value="InputRemoved"/>
|
||||
<status xil_pn:value="OutputChanged"/>
|
||||
<outfile xil_pn:name="Test_MCP33131_isim_beh.wdb"/>
|
||||
<outfile xil_pn:name="isim.cmd"/>
|
||||
<outfile xil_pn:name="isim.log"/>
|
||||
<status xil_pn:value="OutputRemoved"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1600270761" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1600270761">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
|
|
@ -236,13 +201,12 @@
|
|||
<transform xil_pn:end_ts="1600270761" xil_pn:in_ck="-6165752171532536899" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1600270761">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<outfile xil_pn:name="ipcore_dir/PLL.vhd"/>
|
||||
<outfile xil_pn:name="ipcore_dir/SinCos.ngc"/>
|
||||
<outfile xil_pn:name="ipcore_dir/SinCos.vhd"/>
|
||||
<outfile xil_pn:name="ipcore_dir/SinCosMult.ngc"/>
|
||||
<outfile xil_pn:name="ipcore_dir/SinCosMult.vhd"/>
|
||||
<outfile xil_pn:name="ipcore_dir/SweepConfigMem.ngc"/>
|
||||
<outfile xil_pn:name="ipcore_dir/SweepConfigMem.vhd"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="OutOfDateForOutputs"/>
|
||||
<status xil_pn:value="InputAdded"/>
|
||||
<status xil_pn:value="InputChanged"/>
|
||||
<status xil_pn:value="InputRemoved"/>
|
||||
<status xil_pn:value="OutputRemoved"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1600270761" xil_pn:in_ck="277585929807082169" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1600270761">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
|
|
@ -255,90 +219,77 @@
|
|||
<transform xil_pn:end_ts="1600270761" xil_pn:in_ck="277585929807082169" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="250970745955965653" xil_pn:start_ts="1600270761">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1600270761" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="6527189854873920525" xil_pn:start_ts="1600270761">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1600362196" xil_pn:in_ck="-1505308035655400832" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="3256065936432453276" xil_pn:start_ts="1600362176">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="WarningsGenerated"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
<status xil_pn:value="OutOfDateForOutputs"/>
|
||||
<status xil_pn:value="InputAdded"/>
|
||||
<status xil_pn:value="InputChanged"/>
|
||||
<status xil_pn:value="InputRemoved"/>
|
||||
<status xil_pn:value="OutputChanged"/>
|
||||
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
|
||||
<outfile xil_pn:name="top.lso"/>
|
||||
<outfile xil_pn:name="top.ngc"/>
|
||||
<outfile xil_pn:name="top.ngr"/>
|
||||
<outfile xil_pn:name="top.prj"/>
|
||||
<outfile xil_pn:name="top.stx"/>
|
||||
<outfile xil_pn:name="top.syr"/>
|
||||
<outfile xil_pn:name="top.xst"/>
|
||||
<outfile xil_pn:name="top_xst.xrpt"/>
|
||||
<outfile xil_pn:name="webtalk_pn.xml"/>
|
||||
<outfile xil_pn:name="xst"/>
|
||||
<status xil_pn:value="OutputRemoved"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1600270780" xil_pn:in_ck="934418963425178690" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="6693835875156060939" xil_pn:start_ts="1600270780">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1600362202" xil_pn:in_ck="490340488621696080" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="4604875190571501774" xil_pn:start_ts="1600362196">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<outfile xil_pn:name="_ngo"/>
|
||||
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
|
||||
<outfile xil_pn:name="top.bld"/>
|
||||
<outfile xil_pn:name="top.ngd"/>
|
||||
<outfile xil_pn:name="top_ngdbuild.xrpt"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
<status xil_pn:value="OutOfDateForOutputs"/>
|
||||
<status xil_pn:value="InputAdded"/>
|
||||
<status xil_pn:value="InputChanged"/>
|
||||
<status xil_pn:value="InputRemoved"/>
|
||||
<status xil_pn:value="OutputRemoved"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1600362238" xil_pn:in_ck="8512332261572065657" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="1448924893915930207" xil_pn:start_ts="1600362202">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="WarningsGenerated"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="NotReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
<status xil_pn:value="OutOfDateForOutputs"/>
|
||||
<status xil_pn:value="InputRemoved"/>
|
||||
<status xil_pn:value="OutputChanged"/>
|
||||
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
|
||||
<outfile xil_pn:name="top.pcf"/>
|
||||
<outfile xil_pn:name="top_map.map"/>
|
||||
<outfile xil_pn:name="top_map.mrp"/>
|
||||
<outfile xil_pn:name="top_map.ncd"/>
|
||||
<outfile xil_pn:name="top_map.ngm"/>
|
||||
<outfile xil_pn:name="top_map.xrpt"/>
|
||||
<outfile xil_pn:name="top_summary.xml"/>
|
||||
<outfile xil_pn:name="top_usage.xml"/>
|
||||
<status xil_pn:value="OutputRemoved"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1600362265" xil_pn:in_ck="1117507038335044978" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="93661965788626211" xil_pn:start_ts="1600362238">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
|
||||
<outfile xil_pn:name="top.ncd"/>
|
||||
<outfile xil_pn:name="top.pad"/>
|
||||
<outfile xil_pn:name="top.par"/>
|
||||
<outfile xil_pn:name="top.ptwx"/>
|
||||
<outfile xil_pn:name="top.unroutes"/>
|
||||
<outfile xil_pn:name="top.xpi"/>
|
||||
<outfile xil_pn:name="top_pad.csv"/>
|
||||
<outfile xil_pn:name="top_pad.txt"/>
|
||||
<outfile xil_pn:name="top_par.xrpt"/>
|
||||
<status xil_pn:value="NotReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
<status xil_pn:value="OutOfDateForOutputs"/>
|
||||
<status xil_pn:value="InputRemoved"/>
|
||||
<status xil_pn:value="OutputRemoved"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1600362278" xil_pn:in_ck="154288912438" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="3274353840855015246" xil_pn:start_ts="1600362265">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="WarningsGenerated"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
|
||||
<outfile xil_pn:name="top.bgn"/>
|
||||
<outfile xil_pn:name="top.bin"/>
|
||||
<outfile xil_pn:name="top.bit"/>
|
||||
<outfile xil_pn:name="top.drc"/>
|
||||
<outfile xil_pn:name="top.ut"/>
|
||||
<outfile xil_pn:name="usage_statistics_webtalk.html"/>
|
||||
<outfile xil_pn:name="webtalk.log"/>
|
||||
<outfile xil_pn:name="webtalk_pn.xml"/>
|
||||
<status xil_pn:value="NotReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
<status xil_pn:value="OutOfDateForOutputs"/>
|
||||
<status xil_pn:value="InputRemoved"/>
|
||||
<status xil_pn:value="OutputRemoved"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1591357065" xil_pn:in_ck="154288899584" xil_pn:name="TRAN_impactProgrammingTool" xil_pn:prop_ck="-2382555676865099342" xil_pn:start_ts="1591357065">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="NotReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
<status xil_pn:value="OutOfDateForOutputs"/>
|
||||
<status xil_pn:value="InputAdded"/>
|
||||
<status xil_pn:value="InputChanged"/>
|
||||
|
|
@ -347,8 +298,9 @@
|
|||
</transform>
|
||||
<transform xil_pn:end_ts="1591357024" xil_pn:in_ck="154288899584" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="-8856759851099153863" xil_pn:start_ts="1591357024">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="NotReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
<status xil_pn:value="OutOfDateForOutputs"/>
|
||||
<status xil_pn:value="InputAdded"/>
|
||||
<status xil_pn:value="InputChanged"/>
|
||||
|
|
@ -358,8 +310,9 @@
|
|||
</transform>
|
||||
<transform xil_pn:end_ts="1591357058" xil_pn:in_ck="154288899584" xil_pn:name="TRAN_genImpactFile" xil_pn:prop_ck="7381105705363676227" xil_pn:start_ts="1591357058">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="NotReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
<status xil_pn:value="OutOfDateForOutputs"/>
|
||||
<status xil_pn:value="InputAdded"/>
|
||||
<status xil_pn:value="InputChanged"/>
|
||||
|
|
@ -369,10 +322,12 @@
|
|||
</transform>
|
||||
<transform xil_pn:end_ts="1600362265" xil_pn:in_ck="8512326635937592693" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1600362259">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
|
||||
<outfile xil_pn:name="top.twr"/>
|
||||
<outfile xil_pn:name="top.twx"/>
|
||||
<status xil_pn:value="NotReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
<status xil_pn:value="OutOfDateForOutputs"/>
|
||||
<status xil_pn:value="InputRemoved"/>
|
||||
<status xil_pn:value="OutputRemoved"/>
|
||||
</transform>
|
||||
</transforms>
|
||||
|
||||
|
|
|
|||
|
|
@ -23,11 +23,11 @@
|
|||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
<file xil_pn:name="MCP33131.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
|
||||
</file>
|
||||
<file xil_pn:name="Test_MCP33131.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="5"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="5"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="5"/>
|
||||
|
|
@ -126,6 +126,16 @@
|
|||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="139"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="139"/>
|
||||
</file>
|
||||
<file xil_pn:name="DFT.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="143"/>
|
||||
</file>
|
||||
<file xil_pn:name="Test_DFT.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="144"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="144"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="144"/>
|
||||
</file>
|
||||
<file xil_pn:name="ipcore_dir/SweepConfigMem.xise" xil_pn:type="FILE_COREGENISE">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
|
|
@ -382,8 +392,8 @@
|
|||
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/top/SPI" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.SPICommands" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/testbench" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.testbench" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
|
|
@ -401,7 +411,7 @@
|
|||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.SPICommands" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.testbench" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
|
|
@ -453,7 +463,7 @@
|
|||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|Test_MCP33131|behavior" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|Test_DFT|behavior" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="VNA" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue