mirror of
https://github.com/jankae/LibreVNA.git
synced 2026-04-04 14:07:30 +00:00
Bugfixes and improvements for new hardware
This commit is contained in:
Jan Käberich
parent
7d9d5e27eb
commit
4cbd60e62d
33 changed files with 747 additions and 193 deletions
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@ -14,10 +14,17 @@ static uint16_t ISRMaskReg = 0x0000;
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using namespace FPGAHAL;
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static void SwitchBytes(uint16_t &value) {
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value = (value & 0xFF00) >> 8 | (value & 0x00FF) << 8;
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}
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static void SwitchBytes(int16_t &value) {
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value = (value & 0xFF00) >> 8 | (value & 0x00FF) << 8;
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}
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void WriteRegister(FPGA::Reg reg, uint16_t value) {
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uint16_t cmd[2] = {(uint16_t) (0x8000 | (uint16_t) reg), value};
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uint8_t cmd[4] = {0x80, (uint8_t) reg, (uint8_t) (value >> 8), (uint8_t) (value & 0xFF)};
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Low(CS);
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HAL_SPI_Transmit(&FPGA_SPI, (uint8_t*) cmd, 2, 100);
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HAL_SPI_Transmit(&FPGA_SPI, (uint8_t*) cmd, 4, 100);
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High(CS);
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}
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@ -34,8 +41,18 @@ bool FPGA::Configure(Flash *f, uint32_t start_address, uint32_t bitstream_size)
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High(PROGRAM_B);
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while(!isHigh(INIT_B));
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if(isHigh(DONE)) {
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LOG_ERR("DONE not asserted, aborting configuration");
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return false;
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}
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uint32_t lastmessage = HAL_GetTick();
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uint8_t buf[256];
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while(bitstream_size > 0) {
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if(HAL_GetTick() - lastmessage > 100) {
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LOG_DEBUG("Remaining: %lu", bitstream_size);
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lastmessage = HAL_GetTick();
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}
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uint16_t size = sizeof(buf);
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if(size > bitstream_size) {
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size = bitstream_size;
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@ -73,18 +90,20 @@ bool FPGA::Init(HaltedCallback cb) {
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Delay::ms(10);
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// Check if FPGA response is as expected
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uint16_t cmd[2] = {0x4000, 0x0000};
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uint16_t recv[2];
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uint8_t cmd[4] = {0x40, 0x00, 0x00, 0x00};
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uint8_t recv[4];
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Low(CS);
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HAL_SPI_TransmitReceive(&FPGA_SPI, (uint8_t*) cmd, (uint8_t*) recv, 2, 100);
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HAL_SPI_TransmitReceive(&FPGA_SPI, (uint8_t*) cmd, (uint8_t*) recv, 4, 100);
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High(CS);
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if(recv[1] != 0xF0A5) {
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LOG_ERR("Initialization failed, got 0x%04x instead of 0xF0A5", recv[1]);
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uint16_t resp = (uint16_t) recv[2] << 8 | recv[3];
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uint16_t status = (uint16_t) recv[0] << 8 | recv[1];
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if(resp != 0xF0A5) {
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LOG_ERR("Initialization failed, got 0x%04x instead of 0xF0A5", resp);
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return false;
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}
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LOG_DEBUG("Initialized, status register: 0x%04x", recv[0]);
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LOG_DEBUG("Initialized, status register: 0x%04x", status);
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return true;
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}
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@ -183,8 +202,15 @@ void FPGA::WriteSweepConfig(uint16_t pointnum, bool lowband, uint32_t *SourceReg
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}
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send[5] = (Source_M & 0x000F) << 12 | Source_FRAC;
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send[6] = Source_DIV_A << 13 | Source_VCO << 7 | Source_N;
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SwitchBytes(send[0]);
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SwitchBytes(send[1]);
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SwitchBytes(send[2]);
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SwitchBytes(send[3]);
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SwitchBytes(send[4]);
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SwitchBytes(send[5]);
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SwitchBytes(send[6]);
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Low(CS);
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HAL_SPI_Transmit(&FPGA_SPI, (uint8_t*) send, 7, 100);
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HAL_SPI_Transmit(&FPGA_SPI, (uint8_t*) send, 14, 100);
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High(CS);
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}
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@ -194,17 +220,18 @@ static inline int64_t sign_extend_64(int64_t x, uint16_t bits) {
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}
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static FPGA::ReadCallback callback;
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static uint16_t raw[18];
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static uint8_t raw[36];
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static bool halted;
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bool FPGA::InitiateSampleRead(ReadCallback cb) {
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callback = cb;
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uint16_t cmd = 0xC000;
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uint8_t cmd[2] = {0xC0, 0x00};
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uint16_t status;
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Low(CS);
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HAL_SPI_TransmitReceive(&FPGA_SPI, (uint8_t*) &cmd, (uint8_t*) &status, 1,
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100);
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HAL_SPI_TransmitReceive(&FPGA_SPI, cmd, (uint8_t*) &status, 2, 100);
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SwitchBytes(status);
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if (status & 0x0010) {
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halted = true;
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@ -227,27 +254,28 @@ bool FPGA::InitiateSampleRead(ReadCallback cb) {
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}
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// Start data read
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HAL_SPI_Receive_DMA(&FPGA_SPI, (uint8_t*) raw, 18);
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HAL_SPI_Receive_DMA(&FPGA_SPI, raw, 36);
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return true;
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}
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static int64_t assembleSampleResultValue(uint8_t *raw) {
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return sign_extend_64(
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(uint16_t) raw[0] << 8 | raw[1] | (uint32_t) raw[2] << 24
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| (uint32_t) raw[3] << 16 | (uint64_t) raw[4] << 40
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| (uint64_t) raw[5] << 32, 48);
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}
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extern "C" {
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void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi) {
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FPGA::SamplingResult result;
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High(CS);
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// Assemble data from words
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result.P1I = sign_extend_64(
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(uint64_t) raw[17] << 32 | (uint32_t) raw[16] << 16 | raw[15], 48);
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result.P1Q = sign_extend_64(
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(uint64_t) raw[14] << 32 | (uint32_t) raw[13] << 16 | raw[12], 48);
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result.P2I = sign_extend_64(
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(uint64_t) raw[11] << 32 | (uint32_t) raw[10] << 16 | raw[9], 48);
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result.P2Q = sign_extend_64(
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(uint64_t) raw[8] << 32 | (uint32_t) raw[7] << 16 | raw[6], 48);
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result.RefI = sign_extend_64(
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(uint64_t) raw[5] << 32 | (uint32_t) raw[4] << 16 | raw[3], 48);
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result.RefQ = sign_extend_64(
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(uint64_t) raw[2] << 32 | (uint32_t) raw[1] << 16 | raw[0], 48);
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result.P1I = assembleSampleResultValue(&raw[30]);
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result.P1Q = assembleSampleResultValue(&raw[24]);
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result.P2I = assembleSampleResultValue(&raw[18]);
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result.P2Q = assembleSampleResultValue(&raw[12]);
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result.RefI = assembleSampleResultValue(&raw[6]);
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result.RefQ = assembleSampleResultValue(&raw[0]);
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if (callback) {
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callback(result);
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}
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@ -293,36 +321,45 @@ void FPGA::SetMode(Mode mode) {
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}
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uint16_t FPGA::GetStatus() {
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uint16_t cmd = 0x4000;
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uint16_t status;
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uint8_t cmd[2] = {0x40, 0x00};
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uint8_t status[2];
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Low(CS);
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HAL_SPI_TransmitReceive(&FPGA_SPI, (uint8_t*) &cmd, (uint8_t*) &status, 1,
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HAL_SPI_TransmitReceive(&FPGA_SPI, (uint8_t*) &cmd, (uint8_t*) &status, 2,
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100);
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High(CS);
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return status;
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return (uint16_t) status[0] << 8 | status[1];
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}
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FPGA::ADCLimits FPGA::GetADCLimits() {
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uint16_t cmd = 0xE000;
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SwitchBytes(cmd);
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Low(CS);
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HAL_SPI_Transmit(&FPGA_SPI, (uint8_t*) &cmd, 1, 100);
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HAL_SPI_Transmit(&FPGA_SPI, (uint8_t*) &cmd, 2, 100);
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ADCLimits limits;
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HAL_SPI_Receive(&FPGA_SPI, (uint8_t*) &limits, 6, 100);
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HAL_SPI_Receive(&FPGA_SPI, (uint8_t*) &limits, 12, 100);
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High(CS);
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SwitchBytes(limits.P1max);
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SwitchBytes(limits.P1min);
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SwitchBytes(limits.P2max);
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SwitchBytes(limits.P2min);
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SwitchBytes(limits.Rmax);
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SwitchBytes(limits.Rmin);
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return limits;
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}
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void FPGA::ResetADCLimits() {
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uint16_t cmd = 0x6000;
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SwitchBytes(cmd);
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Low(CS);
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HAL_SPI_Transmit(&FPGA_SPI, (uint8_t*) &cmd, 1, 100);
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HAL_SPI_Transmit(&FPGA_SPI, (uint8_t*) &cmd, 2, 100);
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High(CS);
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}
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void FPGA::ResumeHaltedSweep() {
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uint16_t cmd = 0x2000;
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SwitchBytes(cmd);
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Low(CS);
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HAL_SPI_Transmit(&FPGA_SPI, (uint8_t*) &cmd, 1, 100);
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HAL_SPI_Transmit(&FPGA_SPI, (uint8_t*) &cmd, 2, 100);
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High(CS);
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}
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@ -1,5 +1,13 @@
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#include "Flash.hpp"
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#include "FreeRTOS.h"
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#include "task.h"
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#include <cstring>
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#define LOG_LEVEL LOG_LEVEL_INFO
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#define LOG_MODULE "Flash"
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#include "Log.h"
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bool Flash::isPresent() {
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CS(false);
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// read JEDEC ID
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@ -24,16 +32,18 @@ void Flash::read(uint32_t address, uint16_t length, void *dest) {
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bool Flash::write(uint32_t address, uint16_t length, uint8_t *src) {
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if((address & 0xFF) != 0 || length%256 != 0) {
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// only writes to complete pages allowed
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LOG_ERR("Invalid write address/size: %lu/%u", address, length);
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return false;
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}
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address &= 0x00FFFFFF;
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LOG_DEBUG("Writing %u bytes to address %lu", length, address);
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while(length > 0) {
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EnableWrite();
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CS(false);
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uint8_t cmd[4] = {
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0x02,
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((uint8_t) address >> 16) & 0xFF,
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((uint8_t) address >> 8) & 0xFF,
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(uint8_t) (address >> 16) & 0xFF,
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(uint8_t) (address >> 8) & 0xFF,
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(uint8_t) (address & 0xFF),
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};
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// issue read command
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@ -41,9 +51,18 @@ bool Flash::write(uint32_t address, uint16_t length, uint8_t *src) {
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// write data
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HAL_SPI_Transmit(spi, src, 256, 1000);
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CS(true);
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if(!WaitBusy(5)) {
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if(!WaitBusy(20)) {
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LOG_ERR("Write timed out");
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return false;
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}
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// Verify
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uint8_t buf[256];
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read(address, 256, buf);
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if(memcmp(src, buf, 256)) {
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LOG_ERR("Verification error");
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return false;
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}
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address += 256;
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length -= 256;
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src += 256;
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}
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@ -59,6 +78,7 @@ void Flash::EnableWrite() {
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}
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bool Flash::eraseChip() {
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LOG_INFO("Erasing...");
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EnableWrite();
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CS(false);
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// enable write latch
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@ -73,8 +93,8 @@ void Flash::initiateRead(uint32_t address) {
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CS(false);
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uint8_t cmd[4] = {
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0x03,
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((uint8_t) address >> 16) & 0xFF,
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((uint8_t) address >> 8) & 0xFF,
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(uint8_t) (address >> 16) & 0xFF,
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(uint8_t) (address >> 8) & 0xFF,
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(uint8_t) (address & 0xFF),
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};
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// issue read command
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@ -86,15 +106,17 @@ bool Flash::WaitBusy(uint32_t timeout) {
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CS(false);
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uint8_t readStatus1 = 0x05;
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HAL_SPI_Transmit(spi, &readStatus1, 1, 100);
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while(HAL_GetTick() - starttime > timeout) {
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do {
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vTaskDelay(1);
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uint8_t status1;
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HAL_SPI_Receive(spi, &status1, 1, 100);
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if(!(status1 & 0x01)) {
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if (!(status1 & 0x01)) {
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CS(true);
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return true;
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}
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}
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} while (HAL_GetTick() - starttime < timeout);
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// timed out
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CS(true);
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LOG_ERR("Timeout occured");
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return false;
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}
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@ -6,7 +6,7 @@ extern "C" {
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//#define LOG_BLOCKING
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#define LOG_USART 2
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#define LOG_USART 3
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#define LOG_SENDBUF_LENGTH 1024
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//#define LOG_USE_MUTEX
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@ -2,7 +2,7 @@
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#include <cmath>
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#define LOG_LEVEL LOG_LEVEL_DEBUG
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#define LOG_LEVEL LOG_LEVEL_INFO
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#define LOG_MODULE "SI5351"
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#include "Log.h"
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@ -296,12 +296,14 @@ void MAX2871::UpdateFrequency() {
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}
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void MAX2871::Write(uint8_t reg, uint32_t val) {
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uint16_t data[2];
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uint8_t data[4];
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// split value into two 16 bit words
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data[0] = val >> 16;
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data[1] = (val & 0xFFF8) | reg;
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data[0] = (val >> 24) & 0xFF;
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data[1] = (val >> 16) & 0xFF;
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data[2] = (val >> 8) & 0xFF;
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data[3] = (val & 0xF8) | reg;
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Delay::us(1);
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HAL_SPI_Transmit(hspi, (uint8_t*) data, 2, 20);
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HAL_SPI_Transmit(hspi, (uint8_t*) data, 4, 20);
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LE->BSRR = LEpin;
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Delay::us(1);
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LE->BSRR = LEpin << 16;
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@ -309,15 +311,16 @@ void MAX2871::Write(uint8_t reg, uint32_t val) {
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// Assumes that the MUX pin is already configured as "Read register 6" and connected to MISO
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uint32_t MAX2871::Read() {
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uint16_t transmit[2] = {0x0000, 0x0006};
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HAL_SPI_Transmit(hspi, (uint8_t*) transmit, 2, 20);
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uint8_t transmit[4] = {0x00, 0x00, 0x00, 0x06};
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HAL_SPI_Transmit(hspi, (uint8_t*) transmit, 4, 20);
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LE->BSRR = LEpin;
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memset(transmit, 0, sizeof(transmit));
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uint16_t recv[2];
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HAL_SPI_TransmitReceive(hspi, (uint8_t*) transmit, (uint8_t*) recv, 2, 20);
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uint8_t recv[4];
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HAL_SPI_TransmitReceive(hspi, (uint8_t*) transmit, (uint8_t*) recv, 4, 20);
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LE->BSRR = LEpin << 16;
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// assemble readback result
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uint32_t result = ((uint32_t) recv[0] << 16) | (recv[1] & 0xFFFF);
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uint32_t result = ((uint32_t) recv[0] << 24) | ((uint32_t) recv[1] << 16
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) | ((uint32_t) recv[2] << 8) | (recv[3] & 0xFF);
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result <<= 2;
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LOG_DEBUG("Readback: 0x%08x", result);
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return result;
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