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Bugfixes and improvements for new hardware

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This commit is contained in:
Jan Käberich 2020-09-14 23:13:32 +02:00
parent 7d9d5e27eb
commit 4cbd60e62d
33 changed files with 747 additions and 193 deletions
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1
FPGA/.gitignore vendored
View file

@ -7,4 +7,5 @@
*/ipcore_dir
!*.gise
!*.xise
!*.py

14
FPGA/VNA/VNA.gise
View file

@ -223,7 +223,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1600073684" xil_pn:in_ck="-94812602667091528" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="3256065936432453276" xil_pn:start_ts="1600073666">
<transform xil_pn:end_ts="1600104613" xil_pn:in_ck="-94812602667091528" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="3256065936432453276" xil_pn:start_ts="1600104595">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
@ -241,11 +241,11 @@
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1598796368" xil_pn:in_ck="934418963425178690" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="6693835875156060939" xil_pn:start_ts="1598796368">
<transform xil_pn:end_ts="1600116406" xil_pn:in_ck="934418963425178690" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="6693835875156060939" xil_pn:start_ts="1600116406">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1600073692" xil_pn:in_ck="490340488621696080" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="4604875190571501774" xil_pn:start_ts="1600073686">
<transform xil_pn:end_ts="1600116413" xil_pn:in_ck="490340488621696080" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="4604875190571501774" xil_pn:start_ts="1600116406">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/>
@ -254,7 +254,7 @@
<outfile xil_pn:name="top.ngd"/>
<outfile xil_pn:name="top_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1600073728" xil_pn:in_ck="8512332261572065657" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="1448924893915930207" xil_pn:start_ts="1600073692">
<transform xil_pn:end_ts="1600116446" xil_pn:in_ck="8512332261572065657" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="1448924893915930207" xil_pn:start_ts="1600116413">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
@ -270,7 +270,7 @@
<outfile xil_pn:name="top_summary.xml"/>
<outfile xil_pn:name="top_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1600073755" xil_pn:in_ck="1117507038335044978" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="93661965788626211" xil_pn:start_ts="1600073728">
<transform xil_pn:end_ts="1600116473" xil_pn:in_ck="1117507038335044978" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="93661965788626211" xil_pn:start_ts="1600116446">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
@ -284,7 +284,7 @@
<outfile xil_pn:name="top_pad.txt"/>
<outfile xil_pn:name="top_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1600073768" xil_pn:in_ck="154288912438" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="4970201210546912173" xil_pn:start_ts="1600073755">
<transform xil_pn:end_ts="1600116486" xil_pn:in_ck="154288912438" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="3274353840855015246" xil_pn:start_ts="1600116473">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
@ -330,7 +330,7 @@
<status xil_pn:value="OutputChanged"/>
<status xil_pn:value="OutputRemoved"/>
</transform>
<transform xil_pn:end_ts="1600073755" xil_pn:in_ck="8512326635937592693" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1600073748">
<transform xil_pn:end_ts="1600116473" xil_pn:in_ck="8512326635937592693" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1600116466">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>

2
FPGA/VNA/VNA.xise
View file

@ -406,7 +406,7 @@
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Float" xil_pn:valueState="non-default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>

8
FPGA/VNA/top.ucf
View file

@ -68,10 +68,10 @@ NET "ATTENUATION[3]" LOC = P12;
NET "ATTENUATION[2]" LOC = P14;
NET "ATTENUATION[1]" LOC = P15;
NET "ATTENUATION[0]" LOC = P16;
NET "LEDS[0]" LOC = P92;
NET "LEDS[1]" LOC = P93;
NET "LEDS[2]" LOC = P88;
NET "LEDS[3]" LOC = P87;
NET "LEDS[0]" LOC = P87;
NET "LEDS[1]" LOC = P92;
NET "LEDS[2]" LOC = P93;
NET "LEDS[3]" LOC = P88;
NET "LEDS[4]" LOC = P85;
NET "LEDS[5]" LOC = P84;
NET "LEDS[6]" LOC = P83;

17
FPGA/VNA/top.vhd
View file

@ -365,10 +365,10 @@ begin
LEDS(2) <= SOURCE_LD;
LEDS(3) <= LO1_LD;
-- Sweep and active port
PORT_SELECT2 <= sweep_port_select;
PORT2_SELECT <= sweep_port_select;
PORT_SELECT1 <= not sweep_port_select;
PORT1_SELECT <= not sweep_port_select;
PORT_SELECT2 <= not sweep_port_select;
PORT2_SELECT <= not sweep_port_select;
PORT_SELECT1 <= sweep_port_select;
PORT1_SELECT <= sweep_port_select;
BAND_SELECT_HIGH <= not sweep_band;
BAND_SELECT_LOW <= sweep_band;
PORT1_MIX2_EN <= port1mix_en;
@ -377,8 +377,8 @@ begin
PORT2_MIX1_EN <= not port2mix_en;
REF_MIX2_EN <= refmix_en;
REF_MIX1_EN <= not refmix_en;
LEDS(4) <= not (not sweep_reset and sweep_port_select);
LEDS(5) <= not (not sweep_reset and not sweep_port_select);
LEDS(4) <= not (not sweep_reset and not sweep_port_select);
LEDS(5) <= not (not sweep_reset and sweep_port_select);
-- Uncommitted LEDs
LEDS(7 downto 6) <= user_leds(1 downto 0);
--LEDS(7) <= '0';
@ -608,7 +608,10 @@ begin
LO1_MOSI <= MCU_MOSI when aux2_sync = '1' else fpga_LO1_MOSI;
LO1_LE <= MCU_NSS when aux2_sync = '1' else fpga_LO1_LE;
-- select MISO source
MCU_MISO <= SOURCE_MUX when aux1_sync = '1' else LO1_MUX when aux2_sync = '1' else fpga_miso;
MCU_MISO <= SOURCE_MUX when aux1_sync = '1' else
LO1_MUX when aux2_sync = '1' else
fpga_miso when MCU_NSS = '0' else
'Z';
lo_unlocked <= not lo_ld_sync;
source_unlocked <= not source_ld_sync;

46
FPGA/WindowCoefficientGenerator.py Normal file
View file

@ -0,0 +1,46 @@
#!/usr/bin/env python3
import math
# Adapt these constants to your window requirements
NUMBER_OF_COEFFICIENTS = 128
BITS_PER_COEFFICIENT = 16
# If set to true, the coefficients will be scaled to include the window amplitude correction factor.
# They will also be scaled to 1/8 to have enough headroom for the correction.
INCLUDE_AMPLITUDE_CORRECTION = True
# Don't change anything below this line
class Window:
def __init__(self, name, function, correction):
self.name = name
self.function = function
self.correction = correction
def StartFile(self):
self.file = open(self.name+".txt", "w")
def AddCoefficient(self, normalized_index):
if not hasattr(self, 'file'):
self.StartFile()
value = self.function(normalized_index)
if INCLUDE_AMPLITUDE_CORRECTION:
value = value * self.correction / 8.0
value = int(value * (2 ** (BITS_PER_COEFFICIENT-1)))
# prevent overflow
if value >= (2 ** (BITS_PER_COEFFICIENT-1)):
value = value - 1
output = "{0:b}".format(value)
self.file.write(output.zfill(BITS_PER_COEFFICIENT)+"\n")
def calc_hann(i):
return math.sin(math.pi * i) ** 2
WindowList = []
WindowList.append(Window("Hann", calc_hann, 2.0))
for i in range(NUMBER_OF_COEFFICIENTS):
norm_i = (i+0.5) / NUMBER_OF_COEFFICIENTS
for w in WindowList:
w.AddCoefficient(norm_i)