From 468871dd6408fd7640662e1a1f79aa064063922d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jan=20K=C3=A4berich?= Date: Wed, 8 Jun 2022 02:06:08 +0200 Subject: [PATCH] Untested generator FPGA image --- FPGA/Generator/Generator.gise | 364 ++++++++++++ FPGA/Generator/Generator.xise | 485 ++++++++++++++++ FPGA/Generator/MAX2871.vhd | 117 ++++ FPGA/Generator/MAX2871_Calc.vhd | 183 ++++++ FPGA/Generator/Modulator.vhd | 240 ++++++++ FPGA/Generator/RationalApproximation.vhd | 160 ++++++ FPGA/Generator/ResetDelay.vhd | 61 ++ FPGA/Generator/SPIConfig.vhd | 220 ++++++++ FPGA/Generator/Synchronizer.vhd | 53 ++ FPGA/Generator/Test_MAX2871.vhd | 127 +++++ FPGA/Generator/Test_PLL.vhd | 99 ++++ FPGA/Generator/Test_RationalApproximation.vhd | 116 ++++ FPGA/Generator/Test_SPI.vhd | 230 ++++++++ FPGA/Generator/Test_SPICommands.vhd | 309 ++++++++++ FPGA/Generator/Test_SinCos.vhd | 104 ++++ FPGA/Generator/Test_Window.vhd | 106 ++++ FPGA/Generator/ipcore_dir/.gitignore | 6 + FPGA/Generator/ipcore_dir/AMMult.xco | 68 +++ FPGA/Generator/ipcore_dir/AMMult.xise | 73 +++ FPGA/Generator/ipcore_dir/DSP48.xco | 136 +++++ FPGA/Generator/ipcore_dir/PLL.xco | 269 +++++++++ FPGA/Generator/ipcore_dir/PLL.xise | 74 +++ FPGA/Generator/ipcore_dir/SampleMemory.xco | 108 ++++ FPGA/Generator/ipcore_dir/SampleMemory.xise | 73 +++ FPGA/Generator/ipcore_dir/VCO_Mem.xco | 108 ++++ FPGA/Generator/ipcore_dir/VCO_Mem.xise | 73 +++ FPGA/Generator/ipcore_dir/wide_mult.xco | 68 +++ FPGA/Generator/ipcore_dir/wide_mult.xise | 73 +++ FPGA/Generator/spi_slave.vhd | 116 ++++ FPGA/Generator/test_modulator.vhd | 195 +++++++ FPGA/Generator/top.bin | Bin 0 -> 340884 bytes FPGA/Generator/top.ucf | 148 +++++ FPGA/Generator/top.vhd | 526 ++++++++++++++++++ 33 files changed, 5088 insertions(+) create mode 100644 FPGA/Generator/Generator.gise create mode 100644 FPGA/Generator/Generator.xise create mode 100644 FPGA/Generator/MAX2871.vhd create mode 100644 FPGA/Generator/MAX2871_Calc.vhd create mode 100644 FPGA/Generator/Modulator.vhd create mode 100644 FPGA/Generator/RationalApproximation.vhd create mode 100644 FPGA/Generator/ResetDelay.vhd create mode 100644 FPGA/Generator/SPIConfig.vhd create mode 100644 FPGA/Generator/Synchronizer.vhd create mode 100644 FPGA/Generator/Test_MAX2871.vhd create mode 100644 FPGA/Generator/Test_PLL.vhd create mode 100644 FPGA/Generator/Test_RationalApproximation.vhd create mode 100644 FPGA/Generator/Test_SPI.vhd create mode 100644 FPGA/Generator/Test_SPICommands.vhd create mode 100644 FPGA/Generator/Test_SinCos.vhd create mode 100644 FPGA/Generator/Test_Window.vhd create mode 100644 FPGA/Generator/ipcore_dir/.gitignore create mode 100644 FPGA/Generator/ipcore_dir/AMMult.xco create mode 100644 FPGA/Generator/ipcore_dir/AMMult.xise create mode 100644 FPGA/Generator/ipcore_dir/DSP48.xco create mode 100644 FPGA/Generator/ipcore_dir/PLL.xco create mode 100644 FPGA/Generator/ipcore_dir/PLL.xise create mode 100644 FPGA/Generator/ipcore_dir/SampleMemory.xco create mode 100644 FPGA/Generator/ipcore_dir/SampleMemory.xise create mode 100644 FPGA/Generator/ipcore_dir/VCO_Mem.xco create mode 100644 FPGA/Generator/ipcore_dir/VCO_Mem.xise create mode 100644 FPGA/Generator/ipcore_dir/wide_mult.xco create mode 100644 FPGA/Generator/ipcore_dir/wide_mult.xise create mode 100644 FPGA/Generator/spi_slave.vhd create mode 100644 FPGA/Generator/test_modulator.vhd create mode 100644 FPGA/Generator/top.bin create mode 100644 FPGA/Generator/top.ucf create mode 100644 FPGA/Generator/top.vhd diff --git a/FPGA/Generator/Generator.gise b/FPGA/Generator/Generator.gise new file mode 100644 index 0000000..b5bd382 --- /dev/null +++ b/FPGA/Generator/Generator.gise @@ -0,0 +1,364 @@ + + + + + + + + + + + + + + + + + + + + 11.1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FPGA/Generator/Generator.xise b/FPGA/Generator/Generator.xise new file mode 100644 index 0000000..7f787f9 --- /dev/null +++ b/FPGA/Generator/Generator.xise @@ -0,0 +1,485 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FPGA/Generator/MAX2871.vhd b/FPGA/Generator/MAX2871.vhd new file mode 100644 index 0000000..b7b9f13 --- /dev/null +++ b/FPGA/Generator/MAX2871.vhd @@ -0,0 +1,117 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 16:59:45 05/05/2020 +-- Design Name: +-- Module Name: MAX2871 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity MAX2871 is + Generic (CLK_DIV : integer); + Port ( CLK : in STD_LOGIC; + RESET : in STD_LOGIC; + REG4 : in STD_LOGIC_VECTOR (31 downto 0); + REG3 : in STD_LOGIC_VECTOR (31 downto 0); + REG1 : in STD_LOGIC_VECTOR (31 downto 0); + REG0 : in STD_LOGIC_VECTOR (31 downto 0); + RELOAD : in STD_LOGIC; + CLK_OUT : out STD_LOGIC; + MOSI : out STD_LOGIC; + LE : out STD_LOGIC; + DONE : out STD_LOGIC); +end MAX2871; + +architecture Behavioral of MAX2871 is + signal clk_cnt : integer range 0 to (CLK_DIV/2)-1; + signal reg_cnt : integer range 0 to 3; + signal bit_cnt : integer range 0 to 32; + signal latched_regs : std_logic_vector(127 downto 0); + + signal sclk : std_logic; + signal latch : std_logic; + signal done_int : std_logic; +begin + + CLK_OUT <= sclk; + MOSI <= latched_regs(127); + LE <= latch; + DONE <= done_int; + + process(CLK, RESET) + begin + if rising_edge(CLK) then + if RESET = '1' then + sclk <= '0'; + latch <= '0'; + done_int <= '1'; + else + if done_int = '1' then + -- can start a new reload process + if RELOAD = '1' then + done_int <= '0'; + latched_regs <= REG4 & REG3 & REG1 & REG0; + reg_cnt <= 0; + bit_cnt <= 0; + clk_cnt <= 0; + end if; + else + if clk_cnt < (CLK_DIV/2) - 1 then + clk_cnt <= clk_cnt + 1; + else + clk_cnt <= 0; + -- advance SPI state machine + if bit_cnt < 32 then + if sclk = '0' then + sclk <= '1'; + else + -- falling edge of clk, shift out new bit + sclk <= '0'; + latched_regs <= latched_regs(126 downto 0) & "0"; + bit_cnt <= bit_cnt + 1; + end if; + else + -- shifted out one register, strobe latch + if latch = '0' then + latch <= '1'; + else + latch <= '0'; + -- move on to next register + if reg_cnt < 3 then + reg_cnt <= reg_cnt + 1; + bit_cnt <= 0; + else + -- all done + done_int <= '1'; + end if; + end if; + end if; + end if; + end if; + end if; + end if; + end process; +end Behavioral; + diff --git a/FPGA/Generator/MAX2871_Calc.vhd b/FPGA/Generator/MAX2871_Calc.vhd new file mode 100644 index 0000000..5d2eb2b --- /dev/null +++ b/FPGA/Generator/MAX2871_Calc.vhd @@ -0,0 +1,183 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 23:02:23 05/17/2022 +-- Design Name: +-- Module Name: MAX2871_Calc - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity MAX2871_Calc is + Port ( CLK : in STD_LOGIC; + RESET : in STD_LOGIC; + -- set to 1 to start calculation + CALC : in STD_LOGIC; + -- desired frequency in terms of reference frequency, fixed point with 27 digits after decimal point + FREQ : in STD_LOGIC_VECTOR (32 downto 0); + -- minimum possible VCO frequency, fixed point with 27 digits after decimal point + VCO_MIN : in STD_LOGIC_VECTOR (31 downto 0); + -- outputs 1 for one clk cycle when calculation has finished + DONE : out STD_LOGIC; + -- MAX2871 register values + REG0 : out STD_LOGIC_VECTOR (31 downto 0); + REG1 : out STD_LOGIC_VECTOR (31 downto 0); + REG3 : out STD_LOGIC_VECTOR (31 downto 0); + REG4 : out STD_LOGIC_VECTOR (31 downto 0); + -- power selection for RFOUT A + POWER : in STD_LOGIC_VECTOR (1 downto 0); + -- currently selected VCO + VCO_SELECT : out STD_LOGIC_VECTOR (5 downto 0); + -- maximum frequency (in terms of reference frequency) up to which the currently selected VCO can be used + -- fixed point with 10 digits after decimal point + VCO_MAX_FREQ : in STD_LOGIC_VECTOR (15 downto 0) + ); +end MAX2871_Calc; + +architecture Behavioral of MAX2871_Calc is + COMPONENT RationalApproximation + PORT( + CLK : IN std_logic; + RESET : IN std_logic; + RATIO : IN std_logic_vector(26 downto 0); + START : IN std_logic; + NUM : OUT std_logic_vector(11 downto 0); + DENOM : OUT std_logic_vector(11 downto 0); + READY : OUT std_logic + ); + END COMPONENT; + + signal vco_div : integer range 0 to 7; + signal freq_buf : std_logic_vector(32 downto 0); + signal vco_min_buf : std_logic_vector(31 downto 0); + signal power_buf : std_logic_vector(1 downto 0); + + signal vco_cnt : integer range 0 to 63; + + signal approx_start : std_logic; + signal approx_ready : std_logic; + + type States is (Idle, VCODiv, VCO, CalcDone); + signal state : States; +begin + Approx: RationalApproximation PORT MAP( + CLK => CLK, + RESET => RESET, + NUM => REG0(14 downto 3), + DENOM => REG1(14 downto 3), + RATIO => freq_buf(26 downto 0), + START => approx_start, + READY => approx_ready + ); + + VCO_SELECT <= std_logic_vector(to_unsigned(vco_cnt, 6)); + + REG0(31) <= '0'; -- always use FRAC mode + REG0(30 downto 21) <= (others => '0'); -- higher bits of N divider are not used + REG0(20 downto 15) <= freq_buf(32 downto 27); -- take integer part of freq for N divider + REG0(2 downto 0) <= "000"; -- select register 0 + + REG1(31) <= '0'; -- reserved + REG1(30 downto 29) <= "10"; -- Charge pump linearity: 20% + REG1(28 downto 27) <= "00"; -- Charge pump: Normal mode + REG1(26 downto 15) <= (others => '0'); -- phase value is unused + REG1(2 downto 0) <= "001"; -- select register 1 + + REG3(31 downto 26) <= std_logic_vector(to_unsigned(vco_cnt, 6)); -- VCO selection + REG3(25) <= '1'; -- disable VAS + REG3(24) <= '0'; -- disable VAS temp + REG3(23 downto 19) <= (others => '0'); -- reserved + REG3(18) <= '0'; -- enable cycle slip reduction + REG3(17) <= '0'; -- Do not delay LD + REG3(16 downto 15) <= "00"; -- Clock divider mode: Mute until lock delay + REG3(14 downto 3) <= (others => '0'); -- CDIV unused + REG3(2 downto 0) <= "011"; -- select register 3 + + REG4(31 downto 29) <= "011"; -- reserved + REG4(28 downto 26) <= "000"; -- enable LDO, VCO and reference input + REG4(25 downto 24) <= "11"; -- BS = 1023 (bits 8-9) + REG4(23) <= '0'; -- divided N counter feedback + REG4(22 downto 20) <= std_logic_vector(to_unsigned(vco_div, 3)); -- VCO divider selection + REG4(19 downto 12) <= (others => '1'); -- BS = 1023 (bits 0-7) + REG4(11) <= '0'; -- enable VCO + REG4(10) <= '0'; -- disable RFOUT mute + REG4(9) <= '0'; -- RFOUTB divided output + REG4(8) <= '0'; -- RFOUTB disabled + REG4(7 downto 6) <= "00"; -- RFOUTB -4dBm + REG4(5) <= '1'; -- RFOUTA enabled + REG4(4 downto 3) <= power_buf; -- RFOUTA power + REG4(2 downto 0) <= "100"; -- select register 4 + + process(CLK, RESET) + begin + if(rising_edge(CLK)) then + if(RESET = '1') then + state <= Idle; + DONE <= '0'; + approx_start <= '0'; + else + case state is + when Idle => + DONE <= '0'; + freq_buf <= FREQ; + vco_min_buf <= VCO_MIN; + power_buf <= POWER; + vco_div <= 0; + vco_cnt <= 0; + approx_start <= '0'; + if CALC = '1' then + state <= VCODiv; + end if; + when VCODiv => + DONE <= '0'; + if unsigned(freq_buf) < unsigned(vco_min_buf) then + vco_div <= vco_div + 1; + freq_buf <= freq_buf(32 downto 1) & "0"; + else + state <= VCO; + end if; + approx_start <= '0'; + when VCO => + approx_start <= '1'; + DONE <= '0'; + if unsigned(VCO_MAX_FREQ) < unsigned(freq_buf(15 downto 0)) then + -- select next VCO + vco_cnt <= vco_cnt + 1; + else + -- correct VCO selected, check if divider calculation has finished + if approx_ready = '1' then + state <= CalcDone; + end if; + end if; + when CalcDone => + approx_start <= '0'; + DONE <= '1'; + state <= Idle; + end case; + end if; + end if; + end process; + +end Behavioral; + diff --git a/FPGA/Generator/Modulator.vhd b/FPGA/Generator/Modulator.vhd new file mode 100644 index 0000000..5504a15 --- /dev/null +++ b/FPGA/Generator/Modulator.vhd @@ -0,0 +1,240 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 23:19:57 06/06/2022 +-- Design Name: +-- Module Name: Modulator - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use std.textio.all; +use ieee.std_logic_textio.all; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Modulator is + Port ( CLK : in STD_LOGIC; + RESET : in STD_LOGIC; + -- Determines sample rate + SAMPLE_FREQ_WORD : in STD_LOGIC_VECTOR (15 downto 0); + -- Input data, latched when SAMPLE_LATCH goes high + SAMPLE_DATA : in STD_LOGIC_VECTOR (7 downto 0); + SAMPLE_LATCH : in STD_LOGIC; + -- internal FIFO overflows, previous sample has been overwritten, active until reset + OVERFLOW : out STD_LOGIC; + -- internal FIFO empty, reset when the next sample is added + UNDERFLOW : out STD_LOGIC; + -- number of internally stored samples after which THRESHOLD_CROSSED gets asserted + THRESHOLD_LEVEL : in STD_LOGIC_VECTOR (10 downto 0); + -- high when the FIFO contains at least THRESHOLD_LEVEL number of samples + THRESHOLD_CROSSED : out STD_LOGIC; + -- center frequency of the FM (in terms of PLL reference frequency, fixed point with 27 digits after decimal point) + FREQ_CENTER : in STD_LOGIC_VECTOR (32 downto 0); + -- frequency deviation from center at maximum modulation + -- (in terms of PLL reference frequency, fixed point with 27 digits after decimal point -> maximum value ~0.5) + FREQ_DEVIATION : in STD_LOGIC_VECTOR (25 downto 0); + -- attenuator setting for "no modulation" + MIN_ATTENUATION : in STD_LOGIC_VECTOR (6 downto 0); + -- AM depth in percent + AMPLITUDE_DEPTH : in STD_LOGIC_VECTOR (6 downto 0); + -- modulated frequency (in terms of PLL reference frequency, fixed point with 27 digits after decimal point) + FREQUENCY : out STD_LOGIC_VECTOR (32 downto 0); + -- modulated attenuator setting + ATTENUATOR : out STD_LOGIC_VECTOR (6 downto 0); + -- signals that a new output has been generated + NEW_OUTPUT : out STD_LOGIC); +end Modulator; + +architecture Behavioral of Modulator is + COMPONENT SampleMemory + PORT ( + clka : IN STD_LOGIC; + wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0); + dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + clkb : IN STD_LOGIC; + addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0); + doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT wide_mult + PORT ( + clk : IN STD_LOGIC; + a : IN STD_LOGIC_VECTOR(12 DOWNTO 0); + b : IN STD_LOGIC_VECTOR(26 DOWNTO 0); + ce : IN STD_LOGIC; + p : OUT STD_LOGIC_VECTOR(39 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT AMMult + PORT ( + clk : IN STD_LOGIC; + a : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + b : IN STD_LOGIC_VECTOR(6 DOWNTO 0); + ce : IN STD_LOGIC; + p : OUT STD_LOGIC_VECTOR(14 DOWNTO 0) + ); + END COMPONENT; + + signal fm_mult_a : STD_LOGIC_VECTOR(12 DOWNTO 0); + signal fm_mult_b : STD_LOGIC_VECTOR(26 DOWNTO 0); + signal fm_mult_p : STD_LOGIC_VECTOR(39 DOWNTO 0); + + signal am_mult_a : STD_LOGIC_VECTOR(7 DOWNTO 0); + signal am_mult_b : STD_LOGIC_VECTOR(6 DOWNTO 0); + signal am_mult_p : STD_LOGIC_VECTOR(14 DOWNTO 0); + + signal mult_ce : STD_LOGIC; + + signal mult_pipe : integer range 0 to 9; + + signal write_pos : unsigned(10 downto 0); + signal read_pos : unsigned(10 downto 0); + + signal sample : std_logic_vector(7 downto 0); + + signal clk_sample_cnt : unsigned(27 downto 0); + + type AMdepthTable is array(0 to 127) of std_logic_vector(6 downto 0); + + impure function InitWindowDataFromFile (RomFileName : in string) return AMdepthTable is + FILE romfile : text is in RomFileName; + variable RomFileLine : line; + variable rom : AMdepthTable; + begin + for i in AMdepthTable'range loop + readline(romfile, RomFileLine); + read(RomFileLine, rom(i)); + end loop; + return rom; + end function; + + constant AMdepth : AMdepthTable := InitWindowDataFromFile("AMdepth.dat"); + + signal am_attenuation : unsigned(6 downto 0); + +begin + Mem : SampleMemory + PORT MAP ( + clka => CLK, + wea(0) => SAMPLE_LATCH, + addra => std_logic_vector(write_pos), + dina => SAMPLE_DATA, + clkb => CLK, + addrb => std_logic_vector(read_pos), + doutb => sample + ); + + fm_mult_b <= "0" & FREQ_DEVIATION; + am_mult_b <= AMPLITUDE_DEPTH; + + FM_Mult: wide_mult + PORT MAP ( + clk => CLK, + a => fm_mult_a, + b => fm_mult_b, + ce => mult_ce, + p => fm_mult_p + ); + + AM_Mult : AMMult + PORT MAP ( + clk => CLK, + a => am_mult_a, + b => am_mult_b, + ce => mult_ce, + p => am_mult_p + ); + + process(CLK, RESET) + begin + if(rising_edge(CLK)) then + if RESET = '1' then + write_pos <= (others => '0'); + read_pos <= (others => '1'); + OVERFLOW <= '0'; + UNDERFLOW <= '0'; + THRESHOLD_CROSSED <= '0'; + clk_sample_cnt <= (others => '0'); + mult_pipe <= 0; + else + -- update threshold + if write_pos - read_pos >= unsigned(THRESHOLD_LEVEL) then + THRESHOLD_CROSSED <= '1'; + else + THRESHOLD_CROSSED <= '0'; + end if; + if SAMPLE_LATCH = '1' then + UNDERFLOW <= '0'; + -- adding new input sample, advance write position + if write_pos = read_pos then + -- some data has been overwritten + OVERFLOW <= '1'; + end if; + write_pos <= write_pos + 1; + end if; + clk_sample_cnt <= clk_sample_cnt + unsigned(SAMPLE_FREQ_WORD); + if clk_sample_cnt(26) = '1' then + -- take the next sample + clk_sample_cnt(26) <= '0'; + if read_pos + 1 = write_pos then + UNDERFLOW <= '1'; + else + read_pos <= read_pos + 1; + end if; + mult_pipe <= 9; + mult_ce <= '1'; + fm_mult_a <= "00000" & sample; + am_mult_a <= sample; + end if; + if mult_pipe > 0 then + mult_pipe <= mult_pipe - 1; + end if; + if mult_pipe = 4 then + -- multiplier result is ready + mult_ce <= '0'; + FREQUENCY <= std_logic_vector(unsigned(FREQ_CENTER) + unsigned(fm_mult_p(33 downto 8))); + am_attenuation <= unsigned(AMdepth(to_integer(unsigned(am_mult_p(14 downto 8))))); + end if; + if mult_pipe = 3 then + am_attenuation <= unsigned(MIN_ATTENUATION) + am_attenuation; + end if; + if mult_pipe = 2 then + if am_attenuation < unsigned(MIN_ATTENUATION) then + -- attenuator overflowed, use maximum values instead + ATTENUATOR <= (others => '1'); + else + ATTENUATOR <= std_logic_vector(am_attenuation); + end if; + NEW_OUTPUT <= '1'; + end if; + if mult_pipe = 1 then + NEW_OUTPUT <= '0'; + end if; + end if; + end if; + end process; + +end Behavioral; + diff --git a/FPGA/Generator/RationalApproximation.vhd b/FPGA/Generator/RationalApproximation.vhd new file mode 100644 index 0000000..383f86c --- /dev/null +++ b/FPGA/Generator/RationalApproximation.vhd @@ -0,0 +1,160 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 00:02:23 05/10/2022 +-- Design Name: +-- Module Name: RationalApproximation - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity RationalApproximation is + Port ( CLK : in STD_LOGIC; + RESET : in STD_LOGIC; + NUM : out STD_LOGIC_VECTOR (11 downto 0); + DENOM : out STD_LOGIC_VECTOR (11 downto 0); + RATIO : in STD_LOGIC_VECTOR (26 downto 0); + START : in STD_LOGIC; + READY : out STD_LOGIC); +end RationalApproximation; + +architecture Behavioral of RationalApproximation is + COMPONENT wide_mult + PORT ( + clk : IN STD_LOGIC; + a : IN STD_LOGIC_VECTOR(12 DOWNTO 0); + b : IN STD_LOGIC_VECTOR(26 DOWNTO 0); + ce : IN STD_LOGIC; + p : OUT STD_LOGIC_VECTOR(39 DOWNTO 0) + ); + END COMPONENT; + + signal a : integer range 0 to 8192; + signal b : integer range 0 to 8192; + signal c : integer range 0 to 8192; + signal d : integer range 0 to 8192; + + signal compare_ratio : unsigned(39 downto 0); + signal compare_median : unsigned(39 downto 0); + + signal mult_a : std_logic_vector(12 downto 0); + signal mult_p : std_logic_vector(39 downto 0); + signal mult_ce : std_logic; + signal mult_pipe : integer range 0 to 5; + + type States is (Idle, StartMultiplier, WaitMultiplier, CheckResult, Done); + signal state : States; +begin + + Mult : wide_mult + PORT MAP ( + clk => CLK, + a => mult_a, + b => RATIO, + ce => mult_ce, + p => mult_p + ); + + compare_ratio <= unsigned(mult_p); + + READY <= '1' when state = Done else '0'; + process(CLK, RESET) + begin + if(rising_edge(CLK)) then + if(RESET = '1') then + a <= 0; + b <= 1; + c <= 1; + d <= 1; + NUM <= (others => '0'); + DENOM <= (others => '0'); + state <= Idle; + mult_ce <= '0'; + else + if start = '0' then + state <= Idle; + mult_ce <= '0'; + else + -- start is active + case state is + when Idle => + a <= 0; + b <= 1; + c <= 1; + d <= 1; + state <= StartMultiplier; + when StartMultiplier => + mult_a <= std_logic_vector(to_unsigned(b + d, 13)); + compare_median <= unsigned(std_logic_vector(to_unsigned(a + c, 13)) & b"000_0000_0000_0000_0000_0000_0000"); + mult_ce <= '1'; + mult_pipe <= 5; + state <= WaitMultiplier; + when WaitMultiplier => + if unsigned(mult_a) < 4096 then + if mult_pipe = 0 then + state <= CheckResult; + mult_ce <= '0'; + else + mult_pipe <= mult_pipe - 1; + end if; + else + -- got too far, return best approximation + NUM <= std_logic_vector(to_unsigned(a, 12)); + DENOM <= std_logic_vector(to_unsigned(b, 12)); + state <= Done; + mult_ce <= '0'; + end if; + when CheckResult => + if compare_ratio = compare_median then + -- mult_a still contains b + d + if unsigned(mult_a) < 4096 then + NUM <= std_logic_vector(to_unsigned(a + c, 12)); + DENOM <= mult_a(11 downto 0); + elsif d > b then + NUM <= std_logic_vector(to_unsigned(c, 12)); + DENOM <= std_logic_vector(to_unsigned(d, 12)); + else + NUM <= std_logic_vector(to_unsigned(a, 12)); + DENOM <= std_logic_vector(to_unsigned(b, 12)); + end if; + state <= Done; + else + if compare_ratio > compare_median then + a <= a + c; + b <= b + d; + else + c <= a + c; + d <= b + d; + end if; + state <= StartMultiplier; + end if; + when others => + end case; + end if; + end if; + end if; + end process; + +end Behavioral; + diff --git a/FPGA/Generator/ResetDelay.vhd b/FPGA/Generator/ResetDelay.vhd new file mode 100644 index 0000000..bb8c1d0 --- /dev/null +++ b/FPGA/Generator/ResetDelay.vhd @@ -0,0 +1,61 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 20:06:31 05/12/2020 +-- Design Name: +-- Module Name: ResetDelay - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity ResetDelay is + Generic(CLK_DELAY : integer); + Port ( CLK : in STD_LOGIC; + IN_RESET : in STD_LOGIC; + OUT_RESET : out STD_LOGIC); +end ResetDelay; + +architecture Behavioral of ResetDelay is + signal clk_cnt : integer range 0 to CLK_DELAY-1; +begin + + process(CLK, IN_RESET) + begin + if rising_edge(CLK) then + if IN_RESET = '1' then + clk_cnt <= 0; + OUT_RESET <= '1'; + else + if clk_cnt < CLK_DELAY-1 then + clk_cnt <= clk_cnt + 1; + else + OUT_RESET <= '0'; + end if; + end if; + end if; + end process; + + +end Behavioral; + diff --git a/FPGA/Generator/SPIConfig.vhd b/FPGA/Generator/SPIConfig.vhd new file mode 100644 index 0000000..13fd122 --- /dev/null +++ b/FPGA/Generator/SPIConfig.vhd @@ -0,0 +1,220 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 19:51:11 05/05/2020 +-- Design Name: +-- Module Name: SPICommands - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity SPICommands is + Port ( CLK : in STD_LOGIC; + RESET : in STD_LOGIC; + SCLK : in STD_LOGIC; + MOSI : in STD_LOGIC; + MISO : out STD_LOGIC; + NSS : in STD_LOGIC; + SOURCE_FILTER : out STD_LOGIC_VECTOR(1 downto 0); + SOURCE_POWER : out STD_LOGIC_VECTOR(1 downto 0); + SOURCE_ATTENUATION : out STD_LOGIC_VECTOR(6 downto 0); + SOURCE_BANDSELECT : out STD_LOGIC; -- 0: highband, 1: lowband + SOURCE_PORTSELECT : out STD_LOGIC; -- 0: Port 1, 1: Port 2 + SOURCE_UNLOCKED : in STD_LOGIC; + + -- SOURCE VCO lookup table + SOURCE_VCO_INDEX : out STD_LOGIC_VECTOR (5 downto 0); + SOURCE_VCO_MAXFREQ : out STD_LOGIC_VECTOR (15 downto 0); + SOURCE_VCO_WRITE : out STD_LOGIC; + + -- Modulation FIFO signals + MOD_FIFO_DATA : out STD_LOGIC_VECTOR (7 downto 0); + MOD_FIFO_WRITE : out STD_LOGIC; + MOD_FIFO_UNDERFLOW : in STD_LOGIC; + MOD_FIFO_OVERFLOW : in STD_LOGIC; + MOD_FIFO_THRESHOLD_CROSSED : in STD_LOGIC; + MOD_FIFO_THRESHOLD : out STD_LOGIC_VECTOR (10 downto 0); + + -- Modulation control signals + MOD_ENABLE : out STD_LOGIC; + MOD_PHASE_INC : out STD_LOGIC_VECTOR (15 downto 0); + MOD_CENTER_FREQ : out STD_LOGIC_VECTOR (32 downto 0); + MOD_DEVIATION_FREQ : out STD_LOGIC_VECTOR (25 downto 0); + MOD_AM_DEPTH : out STD_LOGIC_VECTOR (6 downto 0); + MOD_VCO_MIN : out STD_LOGIC_VECTOR (31 downto 0); + + AMP_SHDN : out STD_LOGIC; + SOURCE_RF_EN : out STD_LOGIC; + SOURCE_CE_EN : out STD_LOGIC; + PORTSWITCH_EN : out STD_LOGIC; + LEDS : out STD_LOGIC_VECTOR(2 downto 0); + INTERRUPT_ASSERTED : out STD_LOGIC); +end SPICommands; + +architecture Behavioral of SPICommands is + COMPONENT spi_slave + Generic(W : integer); + PORT( + SPI_CLK : in STD_LOGIC; + MISO : out STD_LOGIC; + MOSI : in STD_LOGIC; + CS : in STD_LOGIC; + BUF_OUT : out STD_LOGIC_VECTOR (W-1 downto 0) := (others => '0'); + BUF_IN : in STD_LOGIC_VECTOR (W-1 downto 0); + CLK : in STD_LOGIC; + COMPLETE : out STD_LOGIC + ); + END COMPONENT; + + -- SPI control signals + signal spi_buf_out : std_logic_vector(15 downto 0); + signal spi_buf_in : std_logic_vector(15 downto 0); + signal spi_complete : std_logic; + signal word_cnt : integer range 0 to 19; + type SPI_states is (FirstWord, WriteVCOTable, WriteModulationData, WriteRegister); + signal state : SPI_states; + signal selected_register : integer range 0 to 31; + + signal last_NSS : std_logic; + + signal VCO_table_write : std_logic; + signal mod_first_byte : std_logic; + signal mod_second_byte : std_logic; + signal mod_data_LSB : std_logic_vector(7 downto 0); + + -- Configuration registers + signal interrupt_mask : std_logic_vector(15 downto 0); + signal interrupt_status : std_logic_vector(15 downto 0); + +begin + SPI: spi_slave + GENERIC MAP(w => 16) + PORT MAP( + SPI_CLK => SCLK, + MISO => MISO, + MOSI => MOSI, + CS => NSS, + BUF_OUT => spi_buf_out, + BUF_IN => spi_buf_in, + CLK => CLK, + COMPLETE =>spi_complete + ); + + MOD_FIFO_WRITE <= mod_first_byte or mod_second_byte; + SOURCE_VCO_WRITE <= VCO_table_write; + + process(CLK, RESET) + begin + if rising_edge(CLK) then + if RESET = '1' then + AMP_SHDN <= '1'; + SOURCE_RF_EN <= '0'; + SOURCE_CE_EN <= '0'; + PORTSWITCH_EN <= '0'; + LEDS <= (others => '1'); + interrupt_status <= (others => '0'); + interrupt_mask <= (others => '0'); + INTERRUPT_ASSERTED <= '0'; + last_NSS <= '1'; + else + interrupt_status <= "00000000000" & MOD_FIFO_THRESHOLD_CROSSED & MOD_FIFO_UNDERFLOW & MOD_FIFO_OVERFLOW & SOURCE_UNLOCKED & "0"; + if (interrupt_status and interrupt_mask) = "0000000000000000" then + INTERRUPT_ASSERTED <= '0'; + else + INTERRUPT_ASSERTED <= '1'; + end if; + if mod_first_byte = '1' then + mod_first_byte <= '0'; + mod_second_byte <= '1'; + MOD_FIFO_DATA <= mod_data_LSB; + end if; + if mod_second_byte = '1' then + mod_second_byte <= '0'; + end if; + if VCO_table_write = '1' then + VCO_table_write <= '0'; + end if; + last_NSS <= NSS; + if NSS = '0' and last_NSS = '1' then + word_cnt <= 0; + spi_buf_in <= interrupt_status; + state <= FirstWord; + elsif spi_complete = '1' then + word_cnt <= word_cnt + 1; + case state is + when FirstWord => + -- initial word determines action + case spi_buf_out(15 downto 13) is + when "000" => state <= WriteVCOTable; + -- also extract the point number + SOURCE_VCO_INDEX <= spi_buf_out(5 downto 0); + when "010" => state <= FirstWord; + spi_buf_in <= "1111000010100101"; + when "100" => state <= WriteRegister; + selected_register <= to_integer(unsigned(spi_buf_out(4 downto 0))); + when others => state <= FirstWord; + end case; + when WriteRegister => + -- write received data into previously selected register + case selected_register is + when 0 => interrupt_mask <= spi_buf_out; + when 1 => SOURCE_FILTER <= spi_buf_out(1 downto 0); + SOURCE_POWER <= spi_buf_out(3 downto 2); + SOURCE_ATTENUATION <= spi_buf_out(10 downto 4); + SOURCE_BANDSELECT <= spi_buf_out(11); + SOURCE_PORTSELECT <= spi_buf_out(12); + SOURCE_CE_EN <= spi_buf_out(13); + SOURCE_RF_EN <= spi_buf_out(14); + AMP_SHDN <= spi_buf_out(15); + when 2 => MOD_ENABLE <= spi_buf_out(0); + MOD_AM_DEPTH <= spi_buf_out(7 downto 1); + LEDS <= not spi_buf_out(15 downto 13); + when 3 => MOD_PHASE_INC <= spi_buf_out; + when 4 => MOD_CENTER_FREQ(15 downto 0) <= spi_buf_out; + when 5 => MOD_CENTER_FREQ(31 downto 16) <= spi_buf_out; + when 6 => MOD_DEVIATION_FREQ(15 downto 0) <= spi_buf_out; + when 7 => MOD_CENTER_FREQ(32) <= spi_buf_out(15); + MOD_DEVIATION_FREQ(25 downto 16) <= spi_buf_out(9 downto 0); + when 8 => MOD_VCO_MIN(15 downto 0) <= spi_buf_out; + when 9 => MOD_VCO_MIN(31 downto 16) <= spi_buf_out; + when 10 => MOD_FIFO_THRESHOLD <= spi_buf_out(10 downto 0); + when others => + end case; + selected_register <= selected_register + 1; + when WriteVCOTable => + SOURCE_VCO_MAXFREQ <= spi_buf_out; + VCO_table_write <= '1'; + when WriteModulationData => + -- add two new bytes to the modulation data + MOD_FIFO_DATA <= spi_buf_out(15 downto 8); + mod_first_byte <= '1'; + mod_data_LSB <= spi_buf_out(7 downto 0); + end case; + end if; + end if; + end if; + end process; + +end Behavioral; + diff --git a/FPGA/Generator/Synchronizer.vhd b/FPGA/Generator/Synchronizer.vhd new file mode 100644 index 0000000..bc1a010 --- /dev/null +++ b/FPGA/Generator/Synchronizer.vhd @@ -0,0 +1,53 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 23:31:10 05/15/2020 +-- Design Name: +-- Module Name: Synchronizer - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Synchronizer is + Generic(stages : integer); + Port ( CLK : in STD_LOGIC; + SYNC_IN : in STD_LOGIC; + SYNC_OUT : out STD_LOGIC); +end Synchronizer; + +architecture Behavioral of Synchronizer is + signal sync_line : std_logic_vector(stages downto 0); +begin + + SYNC_OUT <= sync_line(stages); + + process(CLK) + begin + if rising_edge(CLK) then + sync_line <= sync_line(stages-1 downto 0) & SYNC_IN; + end if; + end process; + +end Behavioral; + diff --git a/FPGA/Generator/Test_MAX2871.vhd b/FPGA/Generator/Test_MAX2871.vhd new file mode 100644 index 0000000..4180408 --- /dev/null +++ b/FPGA/Generator/Test_MAX2871.vhd @@ -0,0 +1,127 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 10:46:34 05/07/2020 +-- Design Name: +-- Module Name: /home/jan/Projekte/VNA/FPGA/VNA/Test_MAX2871.vhd +-- Project Name: VNA +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: MAX2871 +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--USE ieee.numeric_std.ALL; + +ENTITY Test_MAX2871 IS +END Test_MAX2871; + +ARCHITECTURE behavior OF Test_MAX2871 IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT MAX2871 + Generic (CLK_DIV : integer); + PORT( + CLK : IN std_logic; + RESET : IN std_logic; + REG4 : IN std_logic_vector(31 downto 0); + REG3 : IN std_logic_vector(31 downto 0); + REG1 : IN std_logic_vector(31 downto 0); + REG0 : IN std_logic_vector(31 downto 0); + RELOAD : IN std_logic; + CLK_OUT : OUT std_logic; + MOSI : OUT std_logic; + LE : OUT std_logic; + DONE : OUT std_logic + ); + END COMPONENT; + + + --Inputs + signal CLK : std_logic := '0'; + signal RESET : std_logic := '0'; + signal REG4 : std_logic_vector(31 downto 0) := (others => '0'); + signal REG3 : std_logic_vector(31 downto 0) := (others => '0'); + signal REG1 : std_logic_vector(31 downto 0) := (others => '0'); + signal REG0 : std_logic_vector(31 downto 0) := (others => '0'); + signal RELOAD : std_logic := '0'; + + --Outputs + signal CLK_OUT : std_logic; + signal MOSI : std_logic; + signal LE : std_logic; + signal DONE : std_logic; + + -- Clock period definitions + constant CLK_period : time := 6.25 ns; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: MAX2871 + GENERIC MAP(CLK_DIV => 10) + PORT MAP ( + CLK => CLK, + RESET => RESET, + REG4 => REG4, + REG3 => REG3, + REG1 => REG1, + REG0 => REG0, + RELOAD => RELOAD, + CLK_OUT => CLK_OUT, + MOSI => MOSI, + LE => LE, + DONE => DONE + ); + + -- Clock process definitions + CLK_process :process + begin + CLK <= '0'; + wait for CLK_period/2; + CLK <= '1'; + wait for CLK_period/2; + end process; + + + -- Stimulus process + stim_proc: process + begin + -- hold reset state for 100 ns. + RESET <= '1'; + wait for 100 ns; + RESET <= '0'; + wait for CLK_period*10; + + -- insert stimulus here + REG4 <= "11111111000000001111111100000000"; + REG3 <= "11110000111100001111000011110000"; + REG1 <= "11001100110011001100110011001100"; + REG0 <= "10101010101010101010101010101010"; + RELOAD <= '1'; + wait for CLK_period; + RELOAD <= '0'; + wait; + end process; + +END; diff --git a/FPGA/Generator/Test_PLL.vhd b/FPGA/Generator/Test_PLL.vhd new file mode 100644 index 0000000..642f15a --- /dev/null +++ b/FPGA/Generator/Test_PLL.vhd @@ -0,0 +1,99 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 12:58:50 05/08/2020 +-- Design Name: +-- Module Name: /home/jan/Projekte/VNA/FPGA/VNA/Test_PLL.vhd +-- Project Name: VNA +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: PLL +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--USE ieee.numeric_std.ALL; + +ENTITY Test_PLL IS +END Test_PLL; + +ARCHITECTURE behavior OF Test_PLL IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT PLL + PORT( + CLK_IN1 : IN std_logic; + CLK_OUT1 : OUT std_logic; + RESET : IN std_logic; + LOCKED : OUT std_logic + ); + END COMPONENT; + + + --Inputs + signal CLK_IN1 : std_logic := '0'; + signal RESET : std_logic := '0'; + + --Outputs + signal CLK_OUT1 : std_logic; + signal LOCKED : std_logic; + + -- Clock period definitions + constant CLK_IN1_period : time := 20 ns; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: PLL PORT MAP ( + CLK_IN1 => CLK_IN1, + CLK_OUT1 => CLK_OUT1, + RESET => RESET, + LOCKED => LOCKED + ); + + -- Clock process definitions + CLK_IN1_process :process + begin + CLK_IN1 <= '0'; + wait for CLK_IN1_period/2; + CLK_IN1 <= '1'; + wait for CLK_IN1_period/2; + end process; + + + + -- Stimulus process + stim_proc: process + begin + -- hold reset state for 100 ns. + RESET <= '1'; + wait for 100 ns; + RESET <= '0'; + + wait for CLK_IN1_period*10; + + -- insert stimulus here + + wait; + end process; + +END; diff --git a/FPGA/Generator/Test_RationalApproximation.vhd b/FPGA/Generator/Test_RationalApproximation.vhd new file mode 100644 index 0000000..64505ff --- /dev/null +++ b/FPGA/Generator/Test_RationalApproximation.vhd @@ -0,0 +1,116 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 00:51:28 05/10/2022 +-- Design Name: +-- Module Name: /home/jan/Projekte/LibreVNA/FPGA/Generator/Test_RationalApproximation.vhd +-- Project Name: VNA +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: RationalApproximation +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--USE ieee.numeric_std.ALL; + +ENTITY Test_RationalApproximation IS +END Test_RationalApproximation; + +ARCHITECTURE behavior OF Test_RationalApproximation IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT RationalApproximation + PORT( + CLK : IN std_logic; + RESET : IN std_logic; + NUM : OUT std_logic_vector(11 downto 0); + DENOM : OUT std_logic_vector(11 downto 0); + RATIO : IN std_logic_vector(26 downto 0); + START : IN std_logic; + READY : OUT std_logic + ); + END COMPONENT; + + + --Inputs + signal CLK : std_logic := '0'; + signal RESET : std_logic := '0'; + signal RATIO : std_logic_vector(26 downto 0) := (others => '0'); + signal START : std_logic := '0'; + + --Outputs + signal NUM : std_logic_vector(11 downto 0); + signal DENOM : std_logic_vector(11 downto 0); + signal READY : std_logic; + + -- Clock period definitions + constant CLK_period : time := 10 ns; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: RationalApproximation PORT MAP ( + CLK => CLK, + RESET => RESET, + NUM => NUM, + DENOM => DENOM, + RATIO => RATIO, + START => START, + READY => READY + ); + + -- Clock process definitions + CLK_process :process + begin + CLK <= '0'; + wait for CLK_period/2; + CLK <= '1'; + wait for CLK_period/2; + end process; + + + -- Stimulus process + stim_proc: process + begin + -- hold reset state for 100 ns. + RESET <= '1'; + wait for 100 ns; + RESET <= '0'; + wait for CLK_period*10; + + -- insert stimulus here + RATIO <= b"001_0000_0000_0000_0000_0000_0000"; + START <= '1'; + + wait until READY = '1'; + + wait for CLK_period*10; + START <= '0'; + wait for CLK_period*10; + RATIO <= b"001_1011_1110_1010_0101_0000_0000"; + START <= '1'; + + wait; + end process; + +END; diff --git a/FPGA/Generator/Test_SPI.vhd b/FPGA/Generator/Test_SPI.vhd new file mode 100644 index 0000000..7b73d0e --- /dev/null +++ b/FPGA/Generator/Test_SPI.vhd @@ -0,0 +1,230 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 15:32:41 05/15/2020 +-- Design Name: +-- Module Name: /home/jan/Projekte/VNA/FPGA/VNA/Test_SPI.vhd +-- Project Name: VNA +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: spi_slave +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--USE ieee.numeric_std.ALL; + +ENTITY Test_SPI IS +END Test_SPI; + +ARCHITECTURE behavior OF Test_SPI IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT spi_slave + GENERIC(W : integer); + PORT( + SPI_CLK : IN std_logic; + MISO : OUT std_logic; + MOSI : IN std_logic; + CS : IN std_logic; + BUF_OUT : OUT std_logic_vector(W-1 downto 0); + BUF_IN : IN std_logic_vector(W-1 downto 0); + CLK : IN std_logic; + COMPLETE : OUT std_logic + ); + END COMPONENT; + + + --Inputs + signal SPI_CLK : std_logic := '0'; + signal MOSI : std_logic := '0'; + signal CS : std_logic := '0'; + signal BUF_IN : std_logic_vector(15 downto 0) := (others => '0'); + signal CLK : std_logic := '0'; + + --Outputs + signal MISO : std_logic; + signal BUF_OUT : std_logic_vector(15 downto 0); + signal COMPLETE : std_logic; + + -- Clock period definitions + constant CLK_period : time := 10 ns; + constant SPI_CLK_period : time := 100 ns; + + signal data_signal : std_logic_vector(15 downto 0); + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: spi_slave + GENERIC MAP(W => 16) + PORT MAP ( + SPI_CLK => SPI_CLK, + MISO => MISO, + MOSI => MOSI, + CS => CS, + BUF_OUT => BUF_OUT, + BUF_IN => BUF_IN, + CLK => CLK, + COMPLETE => COMPLETE + ); + + -- Clock process definitions + + CLK_process :process + begin + CLK <= '0'; + wait for CLK_period/2; + CLK <= '1'; + wait for CLK_period/2; + end process; + + + -- Stimulus process + stim_proc: process + procedure SPI(data : std_logic_vector(15 downto 0)) is + begin + MOSI <= data(15); + data_signal <= data(14 downto 0) & "0"; + wait for SPI_CLK_period/2; + SPI_CLK <= '1'; + wait for SPI_CLK_period/2; + SPI_CLK <= '0'; + MOSI <= data_signal(15); + data_signal <= data_signal(14 downto 0) & '0'; + wait for SPI_CLK_period/2; + SPI_CLK <= '1'; + wait for SPI_CLK_period/2; + SPI_CLK <= '0'; + MOSI <= data_signal(15); + data_signal <= data_signal(14 downto 0) & '0'; + wait for SPI_CLK_period/2; + SPI_CLK <= '1'; + wait for SPI_CLK_period/2; + SPI_CLK <= '0'; + MOSI <= data_signal(15); + data_signal <= data_signal(14 downto 0) & '0'; + wait for SPI_CLK_period/2; + SPI_CLK <= '1'; + wait for SPI_CLK_period/2; + SPI_CLK <= '0'; + MOSI <= data_signal(15); + data_signal <= data_signal(14 downto 0) & '0'; + wait for SPI_CLK_period/2; + SPI_CLK <= '1'; + wait for SPI_CLK_period/2; + SPI_CLK <= '0'; + MOSI <= data_signal(15); + data_signal <= data_signal(14 downto 0) & '0'; + wait for SPI_CLK_period/2; + SPI_CLK <= '1'; + wait for SPI_CLK_period/2; + SPI_CLK <= '0'; + MOSI <= data_signal(15); + data_signal <= data_signal(14 downto 0) & '0'; + wait for SPI_CLK_period/2; + SPI_CLK <= '1'; + wait for SPI_CLK_period/2; + SPI_CLK <= '0'; + MOSI <= data_signal(15); + data_signal <= data_signal(14 downto 0) & '0'; + wait for SPI_CLK_period/2; + SPI_CLK <= '1'; + wait for SPI_CLK_period/2; + SPI_CLK <= '0'; + MOSI <= data_signal(15); + data_signal <= data_signal(14 downto 0) & '0'; + wait for SPI_CLK_period/2; + SPI_CLK <= '1'; + wait for SPI_CLK_period/2; + SPI_CLK <= '0'; + MOSI <= data_signal(15); + data_signal <= data_signal(14 downto 0) & '0'; + wait for SPI_CLK_period/2; + SPI_CLK <= '1'; + wait for SPI_CLK_period/2; + SPI_CLK <= '0'; + MOSI <= data_signal(15); + data_signal <= data_signal(14 downto 0) & '0'; + wait for SPI_CLK_period/2; + SPI_CLK <= '1'; + wait for SPI_CLK_period/2; + SPI_CLK <= '0'; + MOSI <= data_signal(15); + data_signal <= data_signal(14 downto 0) & '0'; + wait for SPI_CLK_period/2; + SPI_CLK <= '1'; + wait for SPI_CLK_period/2; + SPI_CLK <= '0'; + MOSI <= data_signal(15); + data_signal <= data_signal(14 downto 0) & '0'; + wait for SPI_CLK_period/2; + SPI_CLK <= '1'; + wait for SPI_CLK_period/2; + SPI_CLK <= '0'; + MOSI <= data_signal(15); + data_signal <= data_signal(14 downto 0) & '0'; + wait for SPI_CLK_period/2; + SPI_CLK <= '1'; + wait for SPI_CLK_period/2; + SPI_CLK <= '0'; + MOSI <= data_signal(15); + data_signal <= data_signal(14 downto 0) & '0'; + wait for SPI_CLK_period/2; + SPI_CLK <= '1'; + wait for SPI_CLK_period/2; + SPI_CLK <= '0'; + MOSI <= data_signal(15); + data_signal <= data_signal(14 downto 0) & '0'; + wait for SPI_CLK_period/2; + SPI_CLK <= '1'; + wait for SPI_CLK_period/2; + SPI_CLK <= '0'; + end procedure SPI; + + begin + -- hold reset state for 100 ns. + CS <= '1'; + wait for 100 ns; + + wait for CLK_period*10; + BUF_IN <= "1111000010100101"; + -- insert stimulus here + wait for CLK_period*10; + CS <= '0'; + SPI("0101010101010101"); + CS <= '1'; + + wait for CLK_period*10; + BUF_IN <= "0000111100001111"; + wait for CLK_period*10; + CS <= '0'; + SPI("0101010101010101"); + BUF_IN <= "1010101010101010"; + wait for SPI_CLK_period/2; + SPI("1100110011001100"); + CS <= '1'; + + wait; + end process; + +END; diff --git a/FPGA/Generator/Test_SPICommands.vhd b/FPGA/Generator/Test_SPICommands.vhd new file mode 100644 index 0000000..957a524 --- /dev/null +++ b/FPGA/Generator/Test_SPICommands.vhd @@ -0,0 +1,309 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 18:42:26 05/07/2020 +-- Design Name: +-- Module Name: /home/jan/Projekte/VNA/FPGA/VNA/Test_SPICommands.vhd +-- Project Name: VNA +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: SPICommands +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--USE ieee.numeric_std.ALL; + +ENTITY Test_SPICommands IS +END Test_SPICommands; + +ARCHITECTURE behavior OF Test_SPICommands IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT SPICommands + PORT( + CLK : IN std_logic; + RESET : IN std_logic; + SCLK : IN std_logic; + MOSI : IN std_logic; + MISO : OUT std_logic; + NSS : IN std_logic; + NEW_SAMPLING_DATA : IN std_logic; + SAMPLING_RESULT : IN std_logic_vector(303 downto 0); + SOURCE_UNLOCKED : IN std_logic; + LO_UNLOCKED : IN std_logic; + MAX2871_DEF_4 : OUT std_logic_vector(31 downto 0); + MAX2871_DEF_3 : OUT std_logic_vector(31 downto 0); + MAX2871_DEF_1 : OUT std_logic_vector(31 downto 0); + MAX2871_DEF_0 : OUT std_logic_vector(31 downto 0); + SWEEP_DATA : OUT std_logic_vector(95 downto 0); + SWEEP_ADDRESS : OUT std_logic_vector(12 downto 0); + SWEEP_WRITE : OUT std_logic_vector(0 downto 0); + SWEEP_POINTS : OUT std_logic_vector(12 downto 0); + NSAMPLES : OUT std_logic_vector(12 downto 0); + PORT1_EN : OUT std_logic; + PORT2_EN : OUT std_logic; + REF_EN : OUT std_logic; + AMP_SHDN : OUT std_logic; + SOURCE_RF_EN : OUT std_logic; + LO_RF_EN : OUT std_logic; + LEDS : OUT std_logic_vector(2 downto 0); + INTERRUPT_ASSERTED : OUT std_logic + ); + END COMPONENT; + + + --Inputs + signal CLK : std_logic := '0'; + signal RESET : std_logic := '0'; + signal SCLK : std_logic := '0'; + signal MOSI : std_logic := '0'; + signal NSS : std_logic := '0'; + signal NEW_SAMPLING_DATA : std_logic := '0'; + signal SAMPLING_RESULT : std_logic_vector(303 downto 0) := (others => '0'); + signal SOURCE_UNLOCKED : std_logic := '1'; + signal LO_UNLOCKED : std_logic := '1'; + + --Outputs + signal MISO : std_logic; + signal MAX2871_DEF_4 : std_logic_vector(31 downto 0); + signal MAX2871_DEF_3 : std_logic_vector(31 downto 0); + signal MAX2871_DEF_1 : std_logic_vector(31 downto 0); + signal MAX2871_DEF_0 : std_logic_vector(31 downto 0); + signal SWEEP_DATA : std_logic_vector(95 downto 0); + signal SWEEP_ADDRESS : std_logic_vector(12 downto 0); + signal SWEEP_WRITE : std_logic_vector(0 downto 0); + signal SWEEP_POINTS : std_logic_vector(12 downto 0); + signal NSAMPLES : std_logic_vector(12 downto 0); + signal PORT1_EN : std_logic; + signal PORT2_EN : std_logic; + signal REF_EN : std_logic; + signal AMP_SHDN : std_logic; + signal SOURCE_RF_EN : std_logic; + signal LO_RF_EN : std_logic; + signal LEDS : std_logic_vector(2 downto 0); + signal INTERRUPT_ASSERTED : std_logic; + + -- Clock period definitions + constant CLK_period : time := 6.25 ns; + constant SPI_CLK_period : time := 100 ns; + + signal data_signal : std_logic_vector(15 downto 0); +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: SPICommands PORT MAP ( + CLK => CLK, + RESET => RESET, + SCLK => SCLK, + MOSI => MOSI, + MISO => MISO, + NSS => NSS, + NEW_SAMPLING_DATA => NEW_SAMPLING_DATA, + SAMPLING_RESULT => SAMPLING_RESULT, + SOURCE_UNLOCKED => SOURCE_UNLOCKED, + LO_UNLOCKED => LO_UNLOCKED, + MAX2871_DEF_4 => MAX2871_DEF_4, + MAX2871_DEF_3 => MAX2871_DEF_3, + MAX2871_DEF_1 => MAX2871_DEF_1, + MAX2871_DEF_0 => MAX2871_DEF_0, + SWEEP_DATA => SWEEP_DATA, + SWEEP_ADDRESS => SWEEP_ADDRESS, + SWEEP_WRITE => SWEEP_WRITE, + SWEEP_POINTS => SWEEP_POINTS, + NSAMPLES => NSAMPLES, + PORT1_EN => PORT1_EN, + PORT2_EN => PORT2_EN, + REF_EN => REF_EN, + AMP_SHDN => AMP_SHDN, + SOURCE_RF_EN => SOURCE_RF_EN, + LO_RF_EN => LO_RF_EN, + LEDS => LEDS, + INTERRUPT_ASSERTED => INTERRUPT_ASSERTED + ); + + -- Clock process definitions + CLK_process :process + begin + CLK <= '0'; + wait for CLK_period/2; + CLK <= '1'; + wait for CLK_period/2; + end process; + + -- Stimulus process + stim_proc: process + procedure SPI(data : std_logic_vector(15 downto 0)) is + begin + MOSI <= data(15); + data_signal <= data(14 downto 0) & "0"; + wait for SPI_CLK_period/2; + SCLK <= '1'; + wait for SPI_CLK_period/2; + SCLK <= '0'; + MOSI <= data_signal(15); + data_signal <= data_signal(14 downto 0) & '0'; + wait for SPI_CLK_period/2; + SCLK <= '1'; + wait for SPI_CLK_period/2; + SCLK <= '0'; + MOSI <= data_signal(15); + data_signal <= data_signal(14 downto 0) & '0'; + wait for SPI_CLK_period/2; + SCLK <= '1'; + wait for SPI_CLK_period/2; + SCLK <= '0'; + MOSI <= data_signal(15); + data_signal <= data_signal(14 downto 0) & '0'; + wait for SPI_CLK_period/2; + SCLK <= '1'; + wait for SPI_CLK_period/2; + SCLK <= '0'; + MOSI <= data_signal(15); + data_signal <= data_signal(14 downto 0) & '0'; + wait for SPI_CLK_period/2; + SCLK <= '1'; + wait for SPI_CLK_period/2; + SCLK <= '0'; + MOSI <= data_signal(15); + data_signal <= data_signal(14 downto 0) & '0'; + wait for SPI_CLK_period/2; + SCLK <= '1'; + wait for SPI_CLK_period/2; + SCLK <= '0'; + MOSI <= data_signal(15); + data_signal <= data_signal(14 downto 0) & '0'; + wait for SPI_CLK_period/2; + SCLK <= '1'; + wait for SPI_CLK_period/2; + SCLK <= '0'; + MOSI <= data_signal(15); + data_signal <= data_signal(14 downto 0) & '0'; + wait for SPI_CLK_period/2; + SCLK <= '1'; + wait for SPI_CLK_period/2; + SCLK <= '0'; + MOSI <= data_signal(15); + data_signal <= data_signal(14 downto 0) & '0'; + wait for SPI_CLK_period/2; + SCLK <= '1'; + wait for SPI_CLK_period/2; + SCLK <= '0'; + MOSI <= data_signal(15); + data_signal <= data_signal(14 downto 0) & '0'; + wait for SPI_CLK_period/2; + SCLK <= '1'; + wait for SPI_CLK_period/2; + SCLK <= '0'; + MOSI <= data_signal(15); + data_signal <= data_signal(14 downto 0) & '0'; + wait for SPI_CLK_period/2; + SCLK <= '1'; + wait for SPI_CLK_period/2; + SCLK <= '0'; + MOSI <= data_signal(15); + data_signal <= data_signal(14 downto 0) & '0'; + wait for SPI_CLK_period/2; + SCLK <= '1'; + wait for SPI_CLK_period/2; + SCLK <= '0'; + MOSI <= data_signal(15); + data_signal <= data_signal(14 downto 0) & '0'; + wait for SPI_CLK_period/2; + SCLK <= '1'; + wait for SPI_CLK_period/2; + SCLK <= '0'; + MOSI <= data_signal(15); + data_signal <= data_signal(14 downto 0) & '0'; + wait for SPI_CLK_period/2; + SCLK <= '1'; + wait for SPI_CLK_period/2; + SCLK <= '0'; + MOSI <= data_signal(15); + data_signal <= data_signal(14 downto 0) & '0'; + wait for SPI_CLK_period/2; + SCLK <= '1'; + wait for SPI_CLK_period/2; + SCLK <= '0'; + MOSI <= data_signal(15); + data_signal <= data_signal(14 downto 0) & '0'; + wait for SPI_CLK_period/2; + SCLK <= '1'; + wait for SPI_CLK_period/2; + SCLK <= '0'; + end procedure SPI; + begin + -- hold reset state for 100 ns. + RESET <= '1'; + NSS <= '1'; + wait for 100 ns; + RESET <= '0'; + wait for CLK_period*10; + NSS <= '0'; + SPI("1100000000000000"); + SPI("0000000000000000"); + NSS <= '1'; + + wait for CLK_period*50; + -- insert stimulus here + -- write number of points + NSS <= '0'; + SPI("1000000000000001"); + SPI("1111000011110000"); + NSS <= '1'; + + wait for CLK_period*100; + -- Write sweep config + NSS <= '0'; + SPI("0000000000001011"); + SPI("1111111100000000"); + SPI("1111000011110000"); + SPI("1100110011001100"); + SPI("1010101010101010"); + SPI("1101101101101101"); + SPI("1110111011101110"); + SPI("1111101111101111"); + NSS <= '1'; + + wait for CLK_period*50; + NEW_SAMPLING_DATA <= '1'; + wait for CLK_period; + NEW_SAMPLING_DATA <= '0'; + wait for CLK_period*20; + NSS <= '0'; + SPI("1100000000000000"); + NSS <= '1'; + + wait for CLK_period*50; + NEW_SAMPLING_DATA <= '1'; + wait for CLK_period; + NEW_SAMPLING_DATA <= '0'; + wait for CLK_period*20; + NSS <= '0'; + SPI("1100000000000000"); + NSS <= '1'; + + + wait; + end process; + +END; diff --git a/FPGA/Generator/Test_SinCos.vhd b/FPGA/Generator/Test_SinCos.vhd new file mode 100644 index 0000000..6457c8d --- /dev/null +++ b/FPGA/Generator/Test_SinCos.vhd @@ -0,0 +1,104 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 09:16:15 05/14/2020 +-- Design Name: +-- Module Name: /home/jan/Projekte/VNA/FPGA/VNA/Test_SinCos.vhd +-- Project Name: VNA +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: SinCos +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--USE ieee.numeric_std.ALL; + +ENTITY Test_SinCos IS +END Test_SinCos; + +ARCHITECTURE behavior OF Test_SinCos IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT SinCos + PORT( + clk : IN std_logic; + phase_in : IN std_logic_vector(11 downto 0); + cosine : OUT std_logic_vector(15 downto 0); + sine : OUT std_logic_vector(15 downto 0) + ); + END COMPONENT; + + + --Inputs + signal clk : std_logic := '0'; + signal phase_in : std_logic_vector(11 downto 0) := (others => '0'); + + --Outputs + signal cosine : std_logic_vector(15 downto 0); + signal sine : std_logic_vector(15 downto 0); + + -- Clock period definitions + constant clk_period : time := 10 ns; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: SinCos PORT MAP ( + clk => clk, + phase_in => phase_in, + cosine => cosine, + sine => sine + ); + + -- Clock process definitions + clk_process :process + begin + clk <= '0'; + wait for clk_period/2; + clk <= '1'; + wait for clk_period/2; + end process; + + + -- Stimulus process + stim_proc: process + begin + -- hold reset state for 100 ns. + wait for 100 ns; + + wait for clk_period*10; + + -- insert stimulus here + phase_in <= "000000000000"; + wait for clk_period*10; + phase_in <= "000000000001"; + wait for clk_period*10; + phase_in <= "000000000010"; + wait for clk_period*10; + phase_in <= "000000000011"; + wait for clk_period*10; + phase_in <= "000000000100"; + wait; + end process; + +END; diff --git a/FPGA/Generator/Test_Window.vhd b/FPGA/Generator/Test_Window.vhd new file mode 100644 index 0000000..fc53c7f --- /dev/null +++ b/FPGA/Generator/Test_Window.vhd @@ -0,0 +1,106 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 13:39:25 09/16/2020 +-- Design Name: +-- Module Name: /home/jan/Projekte/VNA2/FPGA/VNA/Test_Window.vhd +-- Project Name: VNA +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: window +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--USE ieee.numeric_std.ALL; + +ENTITY Test_Window IS +END Test_Window; + +ARCHITECTURE behavior OF Test_Window IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT window + PORT( + CLK : IN std_logic; + INDEX : IN std_logic_vector(6 downto 0); + WINDOW_TYPE : IN std_logic_vector(1 downto 0); + VALUE : OUT std_logic_vector(15 downto 0) + ); + END COMPONENT; + + + --Inputs + signal CLK : std_logic := '0'; + signal INDEX : std_logic_vector(6 downto 0) := (others => '0'); + signal WINDOW_TYPE : std_logic_vector(1 downto 0) := (others => '0'); + + --Outputs + signal VALUE : std_logic_vector(15 downto 0); + + -- Clock period definitions + constant CLK_period : time := 10 ns; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: window PORT MAP ( + CLK => CLK, + INDEX => INDEX, + WINDOW_TYPE => WINDOW_TYPE, + VALUE => VALUE + ); + + -- Clock process definitions + CLK_process :process + begin + CLK <= '0'; + wait for CLK_period/2; + CLK <= '1'; + wait for CLK_period/2; + end process; + + + -- Stimulus process + stim_proc: process + begin + -- hold reset state for 100 ns. + wait for 100 ns; + WINDOW_TYPE <= "00"; + INDEX <= "0000000"; + wait for CLK_period*10; + + WINDOW_TYPE <= "10"; + -- insert stimulus here + wait for CLK_period*10; + INDEX <= "0000001"; + wait for CLK_period*10; + INDEX <= "0000010"; + wait for CLK_period*10; + INDEX <= "0000011"; + wait for CLK_period*10; + INDEX <= "0000100"; + + wait; + end process; + +END; diff --git a/FPGA/Generator/ipcore_dir/.gitignore b/FPGA/Generator/ipcore_dir/.gitignore new file mode 100644 index 0000000..68f8144 --- /dev/null +++ b/FPGA/Generator/ipcore_dir/.gitignore @@ -0,0 +1,6 @@ +* +*/* +!.gitignore +!*.xco +!*.xise + diff --git a/FPGA/Generator/ipcore_dir/AMMult.xco b/FPGA/Generator/ipcore_dir/AMMult.xco new file mode 100644 index 0000000..68522dc --- /dev/null +++ b/FPGA/Generator/ipcore_dir/AMMult.xco @@ -0,0 +1,68 @@ +############################################################## +# +# Xilinx Core Generator version 14.7 +# Date: Tue Jun 7 10:30:52 2022 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:mult_gen:11.2 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = VHDL +SET device = xc6slx9 +SET devicefamily = spartan6 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = tqg144 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -2 +SET verilogsim = false +SET vhdlsim = true +# END Project Options +# BEGIN Select +SELECT Multiplier xilinx.com:ip:mult_gen:11.2 +# END Select +# BEGIN Parameters +CSET ccmimp=Distributed_Memory +CSET clockenable=true +CSET component_name=AMMult +CSET constvalue=129 +CSET internaluser=0 +CSET multiplier_construction=Use_Mults +CSET multtype=Parallel_Multiplier +CSET optgoal=Speed +CSET outputwidthhigh=14 +CSET outputwidthlow=0 +CSET pipestages=1 +CSET portatype=Unsigned +CSET portawidth=8 +CSET portbtype=Unsigned +CSET portbwidth=7 +CSET roundpoint=0 +CSET sclrcepriority=SCLR_Overrides_CE +CSET syncclear=false +CSET use_custom_output_width=false +CSET userounding=false +CSET zerodetect=false +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2013-07-22T11:36:26Z +# END Extra information +GENERATE +# CRC: b879ca8e diff --git a/FPGA/Generator/ipcore_dir/AMMult.xise b/FPGA/Generator/ipcore_dir/AMMult.xise new file mode 100644 index 0000000..ace3623 --- /dev/null +++ b/FPGA/Generator/ipcore_dir/AMMult.xise @@ -0,0 +1,73 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FPGA/Generator/ipcore_dir/DSP48.xco b/FPGA/Generator/ipcore_dir/DSP48.xco new file mode 100644 index 0000000..face7fc --- /dev/null +++ b/FPGA/Generator/ipcore_dir/DSP48.xco @@ -0,0 +1,136 @@ +############################################################## +# +# Xilinx Core Generator version 14.6 +# Date: Fri Nov 6 13:56:17 2020 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:xbip_dsp48_macro:2.1 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = VHDL +SET device = xc6slx9 +SET devicefamily = spartan6 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = tqg144 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -2 +SET verilogsim = false +SET vhdlsim = true +# END Project Options +# BEGIN Select +SELECT DSP48_Macro xilinx.com:ip:xbip_dsp48_macro:2.1 +# END Select +# BEGIN Parameters +CSET a_binarywidth=0 +CSET a_width=18 +CSET areg_1=false +CSET areg_2=false +CSET areg_3=true +CSET areg_4=true +CSET b_binarywidth=0 +CSET b_width=18 +CSET breg_1=false +CSET breg_2=false +CSET breg_3=true +CSET breg_4=true +CSET c_binarywidth=0 +CSET c_width=48 +CSET cinreg_1=false +CSET cinreg_2=false +CSET cinreg_3=false +CSET cinreg_4=false +CSET cinreg_5=false +CSET component_name=DSP48 +CSET concat_binarywidth=0 +CSET concat_width=48 +CSET concatreg_3=false +CSET concatreg_4=false +CSET concatreg_5=false +CSET creg_1=false +CSET creg_2=false +CSET creg_3=true +CSET creg_4=true +CSET creg_5=true +CSET d_binarywidth=0 +CSET d_width=18 +CSET dreg_1=false +CSET dreg_2=false +CSET dreg_3=false +CSET gui_behaviour=Coregen +CSET has_a_ce=false +CSET has_a_sclr=false +CSET has_acout=false +CSET has_b_ce=false +CSET has_b_sclr=false +CSET has_bcout=false +CSET has_c_ce=false +CSET has_c_sclr=false +CSET has_carrycascout=false +CSET has_carryout=false +CSET has_ce=true +CSET has_concat_ce=false +CSET has_concat_sclr=false +CSET has_d_ce=false +CSET has_d_sclr=false +CSET has_m_ce=false +CSET has_m_sclr=false +CSET has_p_ce=false +CSET has_p_sclr=false +CSET has_pcout=false +CSET has_sclr=false +CSET has_sel_ce=false +CSET has_sel_sclr=false +CSET instruction1=A*B +CSET instruction2=A*B+C +CSET instruction3=# +CSET instruction4=# +CSET instruction5=# +CSET instruction6=# +CSET instruction7=# +CSET instruction8=# +CSET instruction_list=# +CSET mreg_5=true +CSET opreg_1=false +CSET opreg_2=false +CSET opreg_3=true +CSET opreg_4=true +CSET opreg_5=true +CSET output_properties=Full_Precision +CSET p_binarywidth=0 +CSET p_full_width=48 +CSET p_width=48 +CSET pcin_binarywidth=0 +CSET pipeline_options=Automatic +CSET preg_6=true +CSET show_filtered=false +CSET tier_1=false +CSET tier_2=false +CSET tier_3=false +CSET tier_4=false +CSET tier_5=false +CSET tier_6=false +CSET use_dsp48=true +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2012-11-05T14:23:53Z +# END Extra information +GENERATE +# CRC: 2ca4f824 diff --git a/FPGA/Generator/ipcore_dir/PLL.xco b/FPGA/Generator/ipcore_dir/PLL.xco new file mode 100644 index 0000000..709503d --- /dev/null +++ b/FPGA/Generator/ipcore_dir/PLL.xco @@ -0,0 +1,269 @@ +############################################################## +# +# Xilinx Core Generator version 14.6 +# Date: Thu May 14 06:56:00 2020 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:clk_wiz:3.6 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = VHDL +SET device = xc6slx9 +SET devicefamily = spartan6 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = tqg144 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -2 +SET verilogsim = false +SET vhdlsim = true +# END Project Options +# BEGIN Select +SELECT Clocking_Wizard xilinx.com:ip:clk_wiz:3.6 +# END Select +# BEGIN Parameters +CSET calc_done=DONE +CSET clk_in_sel_port=CLK_IN_SEL +CSET clk_out1_port=CLK_OUT1 +CSET clk_out1_use_fine_ps_gui=false +CSET clk_out2_port=CLK_OUT2 +CSET clk_out2_use_fine_ps_gui=false +CSET clk_out3_port=CLK_OUT3 +CSET clk_out3_use_fine_ps_gui=false +CSET clk_out4_port=CLK_OUT4 +CSET clk_out4_use_fine_ps_gui=false +CSET clk_out5_port=CLK_OUT5 +CSET clk_out5_use_fine_ps_gui=false +CSET clk_out6_port=CLK_OUT6 +CSET clk_out6_use_fine_ps_gui=false +CSET clk_out7_port=CLK_OUT7 +CSET clk_out7_use_fine_ps_gui=false +CSET clk_valid_port=CLK_VALID +CSET clkfb_in_n_port=CLKFB_IN_N +CSET clkfb_in_p_port=CLKFB_IN_P +CSET clkfb_in_port=CLKFB_IN +CSET clkfb_in_signaling=SINGLE +CSET clkfb_out_n_port=CLKFB_OUT_N +CSET clkfb_out_p_port=CLKFB_OUT_P +CSET clkfb_out_port=CLKFB_OUT +CSET clkfb_stopped_port=CLKFB_STOPPED +CSET clkin1_jitter_ps=625.0 +CSET clkin1_ui_jitter=0.010 +CSET clkin2_jitter_ps=100.0 +CSET clkin2_ui_jitter=0.010 +CSET clkout1_drives=BUFG +CSET clkout1_requested_duty_cycle=50.000 +CSET clkout1_requested_out_freq=102.4 +CSET clkout1_requested_phase=0.000 +CSET clkout2_drives=BUFG +CSET clkout2_requested_duty_cycle=50.000 +CSET clkout2_requested_out_freq=100.000 +CSET clkout2_requested_phase=0.000 +CSET clkout2_used=false +CSET clkout3_drives=BUFG +CSET clkout3_requested_duty_cycle=50.000 +CSET clkout3_requested_out_freq=100.000 +CSET clkout3_requested_phase=0.000 +CSET clkout3_used=false +CSET clkout4_drives=BUFG +CSET clkout4_requested_duty_cycle=50.000 +CSET clkout4_requested_out_freq=100.000 +CSET clkout4_requested_phase=0.000 +CSET clkout4_used=false +CSET clkout5_drives=BUFG +CSET clkout5_requested_duty_cycle=50.000 +CSET clkout5_requested_out_freq=100.000 +CSET clkout5_requested_phase=0.000 +CSET clkout5_used=false +CSET clkout6_drives=BUFG +CSET clkout6_requested_duty_cycle=50.000 +CSET clkout6_requested_out_freq=100.000 +CSET clkout6_requested_phase=0.000 +CSET clkout6_used=false +CSET clkout7_drives=BUFG +CSET clkout7_requested_duty_cycle=50.000 +CSET clkout7_requested_out_freq=100.000 +CSET clkout7_requested_phase=0.000 +CSET clkout7_used=false +CSET clock_mgr_type=AUTO +CSET component_name=PLL +CSET daddr_port=DADDR +CSET dclk_port=DCLK +CSET dcm_clk_feedback=1X +CSET dcm_clk_out1_port=CLKFX +CSET dcm_clk_out2_port=CLK0 +CSET dcm_clk_out3_port=CLK0 +CSET dcm_clk_out4_port=CLK0 +CSET dcm_clk_out5_port=CLK0 +CSET dcm_clk_out6_port=CLK0 +CSET dcm_clkdv_divide=2.0 +CSET dcm_clkfx_divide=5 +CSET dcm_clkfx_multiply=32 +CSET dcm_clkgen_clk_out1_port=CLKFX +CSET dcm_clkgen_clk_out2_port=CLKFX +CSET dcm_clkgen_clk_out3_port=CLKFX +CSET dcm_clkgen_clkfx_divide=1 +CSET dcm_clkgen_clkfx_md_max=0.000 +CSET dcm_clkgen_clkfx_multiply=4 +CSET dcm_clkgen_clkfxdv_divide=2 +CSET dcm_clkgen_clkin_period=10.000 +CSET dcm_clkgen_notes=None +CSET dcm_clkgen_spread_spectrum=NONE +CSET dcm_clkgen_startup_wait=false +CSET dcm_clkin_divide_by_2=false +CSET dcm_clkin_period=62.500 +CSET dcm_clkout_phase_shift=NONE +CSET dcm_deskew_adjust=SYSTEM_SYNCHRONOUS +CSET dcm_notes=None +CSET dcm_phase_shift=0 +CSET dcm_pll_cascade=NONE +CSET dcm_startup_wait=false +CSET den_port=DEN +CSET din_port=DIN +CSET dout_port=DOUT +CSET drdy_port=DRDY +CSET dwe_port=DWE +CSET feedback_source=FDBK_AUTO +CSET in_freq_units=Units_MHz +CSET in_jitter_units=Units_UI +CSET input_clk_stopped_port=INPUT_CLK_STOPPED +CSET jitter_options=UI +CSET jitter_sel=No_Jitter +CSET locked_port=LOCKED +CSET mmcm_bandwidth=OPTIMIZED +CSET mmcm_clkfbout_mult_f=4.000 +CSET mmcm_clkfbout_phase=0.000 +CSET mmcm_clkfbout_use_fine_ps=false +CSET mmcm_clkin1_period=10.000 +CSET mmcm_clkin2_period=10.000 +CSET mmcm_clkout0_divide_f=4.000 +CSET mmcm_clkout0_duty_cycle=0.500 +CSET mmcm_clkout0_phase=0.000 +CSET mmcm_clkout0_use_fine_ps=false +CSET mmcm_clkout1_divide=1 +CSET mmcm_clkout1_duty_cycle=0.500 +CSET mmcm_clkout1_phase=0.000 +CSET mmcm_clkout1_use_fine_ps=false +CSET mmcm_clkout2_divide=1 +CSET mmcm_clkout2_duty_cycle=0.500 +CSET mmcm_clkout2_phase=0.000 +CSET mmcm_clkout2_use_fine_ps=false +CSET mmcm_clkout3_divide=1 +CSET mmcm_clkout3_duty_cycle=0.500 +CSET mmcm_clkout3_phase=0.000 +CSET mmcm_clkout3_use_fine_ps=false +CSET mmcm_clkout4_cascade=false +CSET mmcm_clkout4_divide=1 +CSET mmcm_clkout4_duty_cycle=0.500 +CSET mmcm_clkout4_phase=0.000 +CSET mmcm_clkout4_use_fine_ps=false +CSET mmcm_clkout5_divide=1 +CSET mmcm_clkout5_duty_cycle=0.500 +CSET mmcm_clkout5_phase=0.000 +CSET mmcm_clkout5_use_fine_ps=false +CSET mmcm_clkout6_divide=1 +CSET mmcm_clkout6_duty_cycle=0.500 +CSET mmcm_clkout6_phase=0.000 +CSET mmcm_clkout6_use_fine_ps=false +CSET mmcm_clock_hold=false +CSET mmcm_compensation=ZHOLD +CSET mmcm_divclk_divide=1 +CSET mmcm_notes=None +CSET mmcm_ref_jitter1=0.010 +CSET mmcm_ref_jitter2=0.010 +CSET mmcm_startup_wait=false +CSET num_out_clks=1 +CSET override_dcm=false +CSET override_dcm_clkgen=false +CSET override_mmcm=false +CSET override_pll=false +CSET platform=lin64 +CSET pll_bandwidth=OPTIMIZED +CSET pll_clk_feedback=CLKFBOUT +CSET pll_clkfbout_mult=16 +CSET pll_clkfbout_phase=0.000 +CSET pll_clkin_period=31.250 +CSET pll_clkout0_divide=5 +CSET pll_clkout0_duty_cycle=0.500 +CSET pll_clkout0_phase=0.000 +CSET pll_clkout1_divide=1 +CSET pll_clkout1_duty_cycle=0.500 +CSET pll_clkout1_phase=0.000 +CSET pll_clkout2_divide=1 +CSET pll_clkout2_duty_cycle=0.500 +CSET pll_clkout2_phase=0.000 +CSET pll_clkout3_divide=1 +CSET pll_clkout3_duty_cycle=0.500 +CSET pll_clkout3_phase=0.000 +CSET pll_clkout4_divide=1 +CSET pll_clkout4_duty_cycle=0.500 +CSET pll_clkout4_phase=0.000 +CSET pll_clkout5_divide=1 +CSET pll_clkout5_duty_cycle=0.500 +CSET pll_clkout5_phase=0.000 +CSET pll_compensation=SYSTEM_SYNCHRONOUS +CSET pll_divclk_divide=1 +CSET pll_notes=None +CSET pll_ref_jitter=0.010 +CSET power_down_port=POWER_DOWN +CSET prim_in_freq=16 +CSET prim_in_jitter=0.010 +CSET prim_source=Single_ended_clock_capable_pin +CSET primary_port=CLK_IN1 +CSET primitive=MMCM +CSET primtype_sel=PLL_BASE +CSET psclk_port=PSCLK +CSET psdone_port=PSDONE +CSET psen_port=PSEN +CSET psincdec_port=PSINCDEC +CSET relative_inclk=REL_PRIMARY +CSET reset_port=RESET +CSET secondary_in_freq=100.000 +CSET secondary_in_jitter=0.010 +CSET secondary_port=CLK_IN2 +CSET secondary_source=Single_ended_clock_capable_pin +CSET ss_mod_freq=250 +CSET ss_mode=CENTER_HIGH +CSET status_port=STATUS +CSET summary_strings=empty +CSET use_clk_valid=false +CSET use_clkfb_stopped=false +CSET use_dyn_phase_shift=false +CSET use_dyn_reconfig=false +CSET use_freeze=false +CSET use_freq_synth=true +CSET use_inclk_stopped=false +CSET use_inclk_switchover=false +CSET use_locked=true +CSET use_max_i_jitter=false +CSET use_min_o_jitter=false +CSET use_min_power=false +CSET use_phase_alignment=true +CSET use_power_down=false +CSET use_reset=true +CSET use_spread_spectrum=false +CSET use_spread_spectrum_1=false +CSET use_status=false +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2012-05-10T12:44:55Z +# END Extra information +GENERATE +# CRC: 2c6bfa8c diff --git a/FPGA/Generator/ipcore_dir/PLL.xise b/FPGA/Generator/ipcore_dir/PLL.xise new file mode 100644 index 0000000..b0b1f74 --- /dev/null +++ b/FPGA/Generator/ipcore_dir/PLL.xise @@ -0,0 +1,74 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FPGA/Generator/ipcore_dir/SampleMemory.xco b/FPGA/Generator/ipcore_dir/SampleMemory.xco new file mode 100644 index 0000000..dadf69d --- /dev/null +++ b/FPGA/Generator/ipcore_dir/SampleMemory.xco @@ -0,0 +1,108 @@ +############################################################## +# +# Xilinx Core Generator version 14.7 +# Date: Mon Jun 6 21:28:52 2022 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:blk_mem_gen:7.3 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = VHDL +SET device = xc6slx9 +SET devicefamily = spartan6 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = tqg144 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -2 +SET verilogsim = false +SET vhdlsim = true +# END Project Options +# BEGIN Select +SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:7.3 +# END Select +# BEGIN Parameters +CSET additional_inputs_for_power_estimation=false +CSET algorithm=Minimum_Area +CSET assume_synchronous_clk=false +CSET axi_id_width=4 +CSET axi_slave_type=Memory_Slave +CSET axi_type=AXI4_Full +CSET byte_size=9 +CSET coe_file=no_coe_file_loaded +CSET collision_warnings=ALL +CSET component_name=SampleMemory +CSET disable_collision_warnings=false +CSET disable_out_of_range_warnings=false +CSET ecc=false +CSET ecctype=No_ECC +CSET enable_32bit_address=false +CSET enable_a=Always_Enabled +CSET enable_b=Always_Enabled +CSET error_injection_type=Single_Bit_Error_Injection +CSET fill_remaining_memory_locations=false +CSET interface_type=Native +CSET load_init_file=false +CSET mem_file=no_Mem_file_loaded +CSET memory_type=Simple_Dual_Port_RAM +CSET operating_mode_a=WRITE_FIRST +CSET operating_mode_b=WRITE_FIRST +CSET output_reset_value_a=0 +CSET output_reset_value_b=0 +CSET pipeline_stages=0 +CSET port_a_clock=100 +CSET port_a_enable_rate=100 +CSET port_a_write_rate=50 +CSET port_b_clock=100 +CSET port_b_enable_rate=100 +CSET port_b_write_rate=0 +CSET primitive=8kx2 +CSET read_width_a=8 +CSET read_width_b=8 +CSET register_porta_input_of_softecc=false +CSET register_porta_output_of_memory_core=false +CSET register_porta_output_of_memory_primitives=false +CSET register_portb_output_of_memory_core=false +CSET register_portb_output_of_memory_primitives=false +CSET register_portb_output_of_softecc=false +CSET remaining_memory_locations=0 +CSET reset_memory_latch_a=false +CSET reset_memory_latch_b=false +CSET reset_priority_a=CE +CSET reset_priority_b=CE +CSET reset_type=SYNC +CSET softecc=false +CSET use_axi_id=false +CSET use_bram_block=Stand_Alone +CSET use_byte_write_enable=false +CSET use_error_injection_pins=false +CSET use_regcea_pin=false +CSET use_regceb_pin=false +CSET use_rsta_pin=false +CSET use_rstb_pin=false +CSET write_depth_a=2048 +CSET write_width_a=8 +CSET write_width_b=8 +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2012-11-19T16:22:25Z +# END Extra information +GENERATE +# CRC: a300d92a diff --git a/FPGA/Generator/ipcore_dir/SampleMemory.xise b/FPGA/Generator/ipcore_dir/SampleMemory.xise new file mode 100644 index 0000000..75132eb --- /dev/null +++ b/FPGA/Generator/ipcore_dir/SampleMemory.xise @@ -0,0 +1,73 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FPGA/Generator/ipcore_dir/VCO_Mem.xco b/FPGA/Generator/ipcore_dir/VCO_Mem.xco new file mode 100644 index 0000000..439981c --- /dev/null +++ b/FPGA/Generator/ipcore_dir/VCO_Mem.xco @@ -0,0 +1,108 @@ +############################################################## +# +# Xilinx Core Generator version 14.7 +# Date: Tue May 17 21:35:59 2022 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:blk_mem_gen:7.3 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = VHDL +SET device = xc6slx9 +SET devicefamily = spartan6 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = tqg144 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -2 +SET verilogsim = false +SET vhdlsim = true +# END Project Options +# BEGIN Select +SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:7.3 +# END Select +# BEGIN Parameters +CSET additional_inputs_for_power_estimation=false +CSET algorithm=Minimum_Area +CSET assume_synchronous_clk=false +CSET axi_id_width=4 +CSET axi_slave_type=Memory_Slave +CSET axi_type=AXI4_Full +CSET byte_size=9 +CSET coe_file=no_coe_file_loaded +CSET collision_warnings=ALL +CSET component_name=VCO_Mem +CSET disable_collision_warnings=false +CSET disable_out_of_range_warnings=false +CSET ecc=false +CSET ecctype=No_ECC +CSET enable_32bit_address=false +CSET enable_a=Always_Enabled +CSET enable_b=Always_Enabled +CSET error_injection_type=Single_Bit_Error_Injection +CSET fill_remaining_memory_locations=false +CSET interface_type=Native +CSET load_init_file=false +CSET mem_file=no_Mem_file_loaded +CSET memory_type=Simple_Dual_Port_RAM +CSET operating_mode_a=WRITE_FIRST +CSET operating_mode_b=WRITE_FIRST +CSET output_reset_value_a=0 +CSET output_reset_value_b=0 +CSET pipeline_stages=0 +CSET port_a_clock=100 +CSET port_a_enable_rate=100 +CSET port_a_write_rate=50 +CSET port_b_clock=100 +CSET port_b_enable_rate=100 +CSET port_b_write_rate=0 +CSET primitive=8kx2 +CSET read_width_a=16 +CSET read_width_b=16 +CSET register_porta_input_of_softecc=false +CSET register_porta_output_of_memory_core=false +CSET register_porta_output_of_memory_primitives=false +CSET register_portb_output_of_memory_core=false +CSET register_portb_output_of_memory_primitives=false +CSET register_portb_output_of_softecc=false +CSET remaining_memory_locations=0 +CSET reset_memory_latch_a=false +CSET reset_memory_latch_b=false +CSET reset_priority_a=CE +CSET reset_priority_b=CE +CSET reset_type=SYNC +CSET softecc=false +CSET use_axi_id=false +CSET use_bram_block=Stand_Alone +CSET use_byte_write_enable=false +CSET use_error_injection_pins=false +CSET use_regcea_pin=false +CSET use_regceb_pin=false +CSET use_rsta_pin=false +CSET use_rstb_pin=false +CSET write_depth_a=64 +CSET write_width_a=16 +CSET write_width_b=16 +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2012-11-19T16:22:25Z +# END Extra information +GENERATE +# CRC: 13dade03 diff --git a/FPGA/Generator/ipcore_dir/VCO_Mem.xise b/FPGA/Generator/ipcore_dir/VCO_Mem.xise new file mode 100644 index 0000000..b9f453c --- /dev/null +++ b/FPGA/Generator/ipcore_dir/VCO_Mem.xise @@ -0,0 +1,73 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FPGA/Generator/ipcore_dir/wide_mult.xco b/FPGA/Generator/ipcore_dir/wide_mult.xco new file mode 100644 index 0000000..f07ce96 --- /dev/null +++ b/FPGA/Generator/ipcore_dir/wide_mult.xco @@ -0,0 +1,68 @@ +############################################################## +# +# Xilinx Core Generator version 14.7 +# Date: Mon May 9 22:25:28 2022 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:mult_gen:11.2 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = VHDL +SET device = xc6slx9 +SET devicefamily = spartan6 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = tqg144 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -2 +SET verilogsim = false +SET vhdlsim = true +# END Project Options +# BEGIN Select +SELECT Multiplier xilinx.com:ip:mult_gen:11.2 +# END Select +# BEGIN Parameters +CSET ccmimp=Distributed_Memory +CSET clockenable=true +CSET component_name=wide_mult +CSET constvalue=129 +CSET internaluser=0 +CSET multiplier_construction=Use_Mults +CSET multtype=Parallel_Multiplier +CSET optgoal=Speed +CSET outputwidthhigh=39 +CSET outputwidthlow=0 +CSET pipestages=5 +CSET portatype=Unsigned +CSET portawidth=13 +CSET portbtype=Unsigned +CSET portbwidth=27 +CSET roundpoint=0 +CSET sclrcepriority=SCLR_Overrides_CE +CSET syncclear=false +CSET use_custom_output_width=false +CSET userounding=false +CSET zerodetect=false +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2013-07-22T11:36:26Z +# END Extra information +GENERATE +# CRC: c45229f4 diff --git a/FPGA/Generator/ipcore_dir/wide_mult.xise b/FPGA/Generator/ipcore_dir/wide_mult.xise new file mode 100644 index 0000000..7df2009 --- /dev/null +++ b/FPGA/Generator/ipcore_dir/wide_mult.xise @@ -0,0 +1,73 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FPGA/Generator/spi_slave.vhd b/FPGA/Generator/spi_slave.vhd new file mode 100644 index 0000000..7d293e1 --- /dev/null +++ b/FPGA/Generator/spi_slave.vhd @@ -0,0 +1,116 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 22:14:17 03/05/2019 +-- Design Name: +-- Module Name: spi_slave - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.all; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity spi_slave is + generic ( W : integer); + Port ( SPI_CLK : in STD_LOGIC; + MISO : out STD_LOGIC; + MOSI : in STD_LOGIC; + CS : in STD_LOGIC; + BUF_OUT : out STD_LOGIC_VECTOR (W-1 downto 0) := (others => '0'); + BUF_IN : in STD_LOGIC_VECTOR (W-1 downto 0); + CLK : in STD_LOGIC; + COMPLETE : out STD_LOGIC +-- RISING_TOGGLE : inout STD_LOGIC; +-- FALLING_TOGGLE : inout STD_LOGIC + ); +end spi_slave; + +architecture Behavioral of spi_slave is + signal miso_buffer : STD_LOGIC_VECTOR (W-1 downto 0); + signal mosi_buffer : STD_LOGIC_VECTOR (W-2 downto 0); + + signal data_valid : STD_LOGIC_VECTOR(2 downto 0); + signal data_synced : STD_LOGIC_VECTOR(2 downto 0); + signal data : STD_LOGIC_VECTOR(W-1 downto 0); + + signal bit_cnt : integer range 0 to W-1; +begin + + process(CLK) + begin + if rising_edge(CLK) then + data_valid(2 downto 1) <= data_valid(1 downto 0); + COMPLETE <= '0'; + if data_valid(1) = '1' then + if data_synced(0) = '0' then + BUF_OUT <= data; + COMPLETE <= '1'; + data_synced(0) <= '1'; + end if; + else + data_synced(0) <= '0'; + end if; + end if; + end process; + + --MISO <= BUF_IN(W - 1 - bit_cnt);-- when bit_cnt = 0 else miso_buffer(W-2); + MISO <= BUF_IN(15) when bit_cnt = 0 else miso_buffer(W-2); + + slave_in: process(SPI_CLK) + begin + if rising_edge(SPI_CLK) then +-- FALLING_TOGGLE <= not FALLING_TOGGLE; + data_synced(2 downto 1) <= data_synced(1 downto 0); + if bit_cnt = W-1 then + -- this was the last bit + data_valid(0) <= '1'; + data <= mosi_buffer(W-2 downto 0) & MOSI; + else + if data_valid(0) = '1' and data_synced(2) = '1' then + data_valid(0) <= '0'; + end if; + mosi_buffer <= mosi_buffer(W-3 downto 0) & MOSI; + end if; + end if; + end process; + + slave_out: process(SPI_CLK, CS, BUF_IN, bit_cnt) + begin + if CS = '1' then + bit_cnt <= 0; + elsif falling_edge(SPI_CLK) then + if bit_cnt < W-1 then + bit_cnt <= bit_cnt + 1; + if bit_cnt = 0 then + miso_buffer <= BUF_IN; + else + miso_buffer <= miso_buffer(W-2 downto 0) & '0'; + end if; + else + bit_cnt <= 0; + --miso_buffer <= BUF_IN; + end if; + end if; + end process; + +end Behavioral; \ No newline at end of file diff --git a/FPGA/Generator/test_modulator.vhd b/FPGA/Generator/test_modulator.vhd new file mode 100644 index 0000000..bcfbf5f --- /dev/null +++ b/FPGA/Generator/test_modulator.vhd @@ -0,0 +1,195 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 12:41:17 06/07/2022 +-- Design Name: +-- Module Name: /home/jan/Projekte/LibreVNA/FPGA/Generator/test_modulator.vhd +-- Project Name: VNA +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: Modulator +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +USE ieee.numeric_std.ALL; + +ENTITY test_modulator IS +END test_modulator; + +ARCHITECTURE behavior OF test_modulator IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT Modulator + PORT( + CLK : IN std_logic; + RESET : IN std_logic; + SAMPLE_FREQ_WORD : IN std_logic_vector(15 downto 0); + SAMPLE_DATA : IN std_logic_vector(7 downto 0); + SAMPLE_LATCH : IN std_logic; + OVERFLOW : OUT std_logic; + UNDERFLOW : OUT std_logic; + THRESHOLD_LEVEL : IN std_logic_vector(10 downto 0); + THRESHOLD_CROSSED : OUT std_logic; + FREQ_CENTER : IN std_logic_vector(32 downto 0); + FREQ_DEVIATION : IN std_logic_vector(25 downto 0); + MIN_ATTENUATION : IN std_logic_vector(6 downto 0); + AMPLITUDE_DEPTH : IN std_logic_vector(6 downto 0); + FREQUENCY : OUT std_logic_vector(32 downto 0); + ATTENUATOR : OUT std_logic_vector(6 downto 0); + NEW_OUTPUT : OUT std_logic + ); + END COMPONENT; + + + --Inputs + signal CLK : std_logic := '0'; + signal RESET : std_logic := '0'; + signal SAMPLE_FREQ_WORD : std_logic_vector(15 downto 0) := (others => '0'); + signal SAMPLE_DATA : std_logic_vector(7 downto 0) := (others => '0'); + signal SAMPLE_LATCH : std_logic := '0'; + signal THRESHOLD_LEVEL : std_logic_vector(10 downto 0) := (others => '0'); + signal FREQ_CENTER : std_logic_vector(32 downto 0) := (others => '0'); + signal FREQ_DEVIATION : std_logic_vector(25 downto 0) := (others => '0'); + signal MIN_ATTENUATION : std_logic_vector(6 downto 0) := (others => '0'); + signal AMPLITUDE_DEPTH : std_logic_vector(6 downto 0) := (others => '0'); + + --Outputs + signal OVERFLOW : std_logic; + signal UNDERFLOW : std_logic; + signal THRESHOLD_CROSSED : std_logic; + signal FREQUENCY : std_logic_vector(32 downto 0); + signal ATTENUATOR : std_logic_vector(6 downto 0); + signal NEW_OUTPUT : std_logic; + + -- Clock period definitions + constant CLK_period : time := 10 ns; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: Modulator PORT MAP ( + CLK => CLK, + RESET => RESET, + SAMPLE_FREQ_WORD => SAMPLE_FREQ_WORD, + SAMPLE_DATA => SAMPLE_DATA, + SAMPLE_LATCH => SAMPLE_LATCH, + OVERFLOW => OVERFLOW, + UNDERFLOW => UNDERFLOW, + THRESHOLD_LEVEL => THRESHOLD_LEVEL, + THRESHOLD_CROSSED => THRESHOLD_CROSSED, + FREQ_CENTER => FREQ_CENTER, + FREQ_DEVIATION => FREQ_DEVIATION, + MIN_ATTENUATION => MIN_ATTENUATION, + AMPLITUDE_DEPTH => AMPLITUDE_DEPTH, + FREQUENCY => FREQUENCY, + ATTENUATOR => ATTENUATOR, + NEW_OUTPUT => NEW_OUTPUT + ); + + -- Clock process definitions + CLK_process :process + begin + CLK <= '0'; + wait for CLK_period/2; + CLK <= '1'; + wait for CLK_period/2; + end process; + + + -- Stimulus process + stim_proc: process + begin + RESET <= '1'; + -- hold reset state for 100 ns. + wait for 100 ns; + + SAMPLE_FREQ_WORD <= std_logic_vector(to_unsigned(32768, 16)); + THRESHOLD_LEVEL <= std_logic_vector(to_unsigned(5, 11)); + FREQ_CENTER <= std_logic_vector(to_unsigned(134217728, 33)); + FREQ_DEVIATION <= std_logic_vector(to_unsigned(16777216, 26)); + MIN_ATTENUATION <= std_logic_vector(to_unsigned(64, 7)); + AMPLITUDE_DEPTH <= std_logic_vector(to_unsigned(127, 7)); + wait for CLK_period*10; + -- release reset + RESET <= '0'; + -- add samples + wait for CLK_period; + SAMPLE_DATA <= std_logic_vector(to_unsigned(0, 8)); + SAMPLE_LATCH <= '1'; + wait for CLK_period; + SAMPLE_DATA <= std_logic_vector(to_unsigned(10, 8)); + wait for CLK_period; + SAMPLE_DATA <= std_logic_vector(to_unsigned(20, 8)); + wait for CLK_period; + SAMPLE_DATA <= std_logic_vector(to_unsigned(30, 8)); + wait for CLK_period; + SAMPLE_DATA <= std_logic_vector(to_unsigned(40, 8)); + wait for CLK_period; + SAMPLE_DATA <= std_logic_vector(to_unsigned(50, 8)); + wait for CLK_period; + SAMPLE_DATA <= std_logic_vector(to_unsigned(60, 8)); + wait for CLK_period; + SAMPLE_DATA <= std_logic_vector(to_unsigned(70, 8)); + wait for CLK_period; + SAMPLE_DATA <= std_logic_vector(to_unsigned(80, 8)); + wait for CLK_period; + SAMPLE_DATA <= std_logic_vector(to_unsigned(90, 8)); + wait for CLK_period; + SAMPLE_DATA <= std_logic_vector(to_unsigned(100, 8)); + wait for CLK_period; + SAMPLE_DATA <= std_logic_vector(to_unsigned(110, 8)); + wait for CLK_period; + SAMPLE_DATA <= std_logic_vector(to_unsigned(120, 8)); + wait for CLK_period; + SAMPLE_DATA <= std_logic_vector(to_unsigned(130, 8)); + wait for CLK_period; + SAMPLE_DATA <= std_logic_vector(to_unsigned(140, 8)); + wait for CLK_period; + SAMPLE_DATA <= std_logic_vector(to_unsigned(150, 8)); + wait for CLK_period; + SAMPLE_DATA <= std_logic_vector(to_unsigned(160, 8)); + wait for CLK_period; + SAMPLE_DATA <= std_logic_vector(to_unsigned(170, 8)); + wait for CLK_period; + SAMPLE_DATA <= std_logic_vector(to_unsigned(180, 8)); + wait for CLK_period; + SAMPLE_DATA <= std_logic_vector(to_unsigned(190, 8)); + wait for CLK_period; + SAMPLE_DATA <= std_logic_vector(to_unsigned(200, 8)); + wait for CLK_period; + SAMPLE_DATA <= std_logic_vector(to_unsigned(210, 8)); + wait for CLK_period; + SAMPLE_DATA <= std_logic_vector(to_unsigned(220, 8)); + wait for CLK_period; + SAMPLE_DATA <= std_logic_vector(to_unsigned(230, 8)); + wait for CLK_period; + SAMPLE_DATA <= std_logic_vector(to_unsigned(240, 8)); + wait for CLK_period; + SAMPLE_DATA <= std_logic_vector(to_unsigned(250, 8)); + wait for CLK_period; + SAMPLE_LATCH <= '0'; + + wait; + end process; + +END; diff --git a/FPGA/Generator/top.bin b/FPGA/Generator/top.bin new file mode 100644 index 0000000000000000000000000000000000000000..15e0a04098e59a16ab17912f3d5c7a208f5489e2 GIT binary patch literal 340884 zcmeFaeT*c@btm>BKW4Iqz3eP{bhkLmWE8Q`tp$BFMVVR?B~9c|F!liRZlKdZhCp~{ zbaE3k1Q8JAgM8MKG1=AUY8kMrXh85De7Nkx>C9`_Y(ONlIIwVr7FZo%Vg1Je z9GPcG25qx_8v@>OTPh!-#3d+{PNG9n`~yWby$i&yR+ADz=p zNgq1*^@oz5jXw0S_Wyq9s{zIT_0gZw8%I5QBx%v_!;hN({6mkTM?c*l`YAyl_|TvB z`yXyl_~C?t4+}v*^$_$&IL>kOaQrFJhtL1b|Kr17B>+o5`XGm3iMaQGy#MCE=h%iI zke`pI8G`K;{-10|jFl45d%_Ln$p!g2Jzl_5C69YR6$FRJ({~@&g$jpvud&iV6je^B zJWzO`+!oTO+$&qUd2ZlEy+PhBX7vkMo8Gq9H|c2~$F1+VDre<^A3P7JqDT%G(GL~4 zLQjVWbWu!)_gZSN(B|-7l^4pQVwUUh0vqIN=~M2yizF;iP$gF$cqe&4Z{HXD=M5|--QJdO<{T1g#|=8wU;(wCl=f!y1TRm72~cvpyhSWE_PL_cbD8}cWCa| zB4uZXs+JOs+p}JZaYsz1wW}Qouf$d!Sk(h+)eQUO=Z!OahKXV8p7ldrgOdF#y?%|@ zk%eI)Lm(}p0Kb|EU(adzG3xc$w*{?gj*RQM7UDMM1~T@5C3!LK*w+JETfGI^s}Y)X zR*Y0mpm>iaI8`2by||NO?@W|OUX;U%J%Ow6T8BD$lyK z%)xy_%v$k>(rdP1?;t6XxEQI!m!!JB$=Zv>Y~A7gI->r;=ZNrkT~PlZ(Ifl`7{JH= zArP@5wST=sjgcpD9hx|wZOBCTdwO4?Zt|)3e(l)5Hobq9qZ)(J==H?Z^{B11Rvvgq zdO#AkO$Hbsba3V|`!&qk-zko%zf%lhJLEo%sZkizf*RE@aWJa6H9XyrKHbHyN?&=P z@<8Q*$^(@LMm-=$qszsv=dlOdrj|2sH(VG@6+`Ofhf|z~!C@Plcb0P!HPUqPo5Qwb zlEgG2E=pu33fkk}lDW6amKM^a=HFIDFDq>H8B(O#q#^C3bs}35<7j2&3F6;&#?_6& zL_FUw>5SCqnorOOL}b)rjtAfxliPU&$?JMNT~fAm!it7)2dyFy0JC2J9-k1GjF$z@ z#4>_nb#a)l20>U{=x^pgm#2|p%KM+ z%_DCsEIGBuCHkIH9SQ50za2zzqLPjp=UOYSi(K$2FS5iIPl)Q~@D4W^PRCzfhsA1w zZ4Ckh^7;9^5(sr8>nFHmVFNmEO-WbP+vG=^Tad%)?Kp+oRTRZ7%7qjvZ+DD2 zrIQk}k)RhudK^VNh)lcuivJ;5Gc1HcUg2JwQtCOSH}b3iwakBRzy zd(037j%R=C*=Mh=KK-D1*{4^)cK0{#-krg{0y+2lhg5@hQ5-Y!UIN&Hg9EmJh~wL_ zU|iwHB1P0{{QYtI?&3#R^t$su<5_@ux}@mwA3gVHZ@h7Q+-!2Z`D6WW&f;I5es%Ra zT7VuLvvP7vu@)R093E1i1-~M3S0={mVfbCl#iGK=$ZDU-hVU01$e3=?;L>m@+ zp3lA8R9t!%LbyXCsNoz2>n3YxfH)r-$JU@cdN)G3?Mic4qxg<2j2)(jKp4XZ9P5I{ zG(clprbgeSgAn)K21aB6s}3b>AR?J!Xp+p;gi`Zw7N}VXQ|OXv7=1-rLW^Wm@Cz{~ z=nPw8K)$d;0?9@o46vLgIOSw{CK7@P3JA(md}PFcjGA<(CQXc$VE1lAQX^xHSuN{g zC}n;bX1p=A&Ro~+I`A2)jl3BrOaMvfVrMKIEJ-Su!Jrvuj9U$|WtRr~gdw8=$*BzX z?Cde5y9`G(%P*s3(0)M&MmSyl{=srnbDqQxd+w5su1hn9+d5*~5&7DGJ9L&=XNa=Z#uQ zS=1wv5MgWFJk-%eOj8{x_7AinbUCPPTv)W~Sx_6Jf1b8NF`nk+6r?ARg((EL|2TGy z?p)N&^@+J-Do{(Ah~OE3=!p*dK=gu6`$X}KkK@WDE^+cuf*$y~HLp=e?dvf0Gk8^V zUd=N!2xpLS_tb}>(Rm~EVN5MN%|q5x>&55M2_{uNecr}YhI8S!G=vc0Q-aIUJD2rS zonS)lc_%Q+2m(EV+7onHKEn0WI+}=wo}f;lh5T6n(2l`F75FXCR5aV1I776cz;Img+3s4$OuX2^GHFgMJ6=^?eL@Y!i(EFmd35Azu&;i*j3`PhxBvY^ep;|*ChCozUoNpj}ZGTE)usaNZI+H?yy~Wwq}wwrNUmu?LeP( zPf!s(*skfc-ZQzlB9?^2^TJR|S*y#it^H0X^>RGf_K^M5Nbx9SoXIGxlM4N|3KfO% zNjLOD@)arq&vv?auGFh{G2hC4%;X10FI@+TN6+c@)?P#M$B6)ZReT;j*@y8vp^WtJTsvA|omK6;BW(=Wkd4#SNc zh?@yNrjr;jA08Z-1Kfi+XI%n#7S0wh+JXgrh;bGzq1~|b$vnCEWdJ|HxKH=#@GuPj z;18P33wkxQVlX?vA6xqPG3Xcf@4L8pl7NhK==+Zi^U={Id;&2`0vo`y54M0YTR;?s zUosY47%5D58YeAazXOZ~_wV;A>e&QGJ z!Gf{*V4v=zg=E?D#1_c^BLbU$-Lks9~T?^R4=btB3c!<8QulrZu`Szbbx%&2~ z^@~|2EMlK7rQXzqm9l@$hX>RtL7gToSP0 zJ&{lOlmBhh0wmrCT;9HX&9utf^nTbF;Ic!1u?-6#%fT=tNjljg=olj@6dH`t zn~QJ54op=D_j-(R1W6niCJNvC&7%i<)U&z%Z`8<&hR85vh zTMMEFAS+MuLZT`#sbTxXV-8z-msa2s$5_e=(WsFI!pCSZfafh>#3?w0xv6Bldk`4j z@t9BGK>^w!$p-FpL=Dj(ZkG(0RKQO-+O zI~snCmBc*3Y&R%0QNx;`7Dy{4d!_K)Al@!S`^F9aL}8W+fFHEbDMrIs`&Mv*1LFnQ zR{-bR3gj4FLr}^t#-te2=A7$44bA20gT8Cf3Fc=+8WYe2e#^< zy%6nz<0sI}7~@Y)+AVl!0U7%mxOajx%;}wIo(DHjKYF*?Svq{KdzqhSKAPdF-%HRS zP7+`19+LQ;wR`B1r!X{3q->l7c>a(p5ekv3Uc0Wgu)AP!0Uo`Nd0xERdLKPu+%Dpd zzF5K!49C&6mn3>{eI`g&Er$BhBjabNj+hq#T&R;!$~u|26vapghO7#Gkt~}uO!9`o z>kFA1`1PqbnzwI5D5b>u3Kh?5g7cum3kCxSR5A#2K( z^?*q${LmB)*z)q(gp84bkXoc$u5FwluvBW4u?#^uQiNf~2)MG35LbyvE*GG~Co^ZW z0i5L^R1Sb@=MU4&D>E(=)?k7h_#k2SvM)GpVW>!G!Ihw0$`&vS@7ks9LRvPE+QMwX z#Iz-~;1jIw_83w4B2Y}cB-TljYOs=>8a!29Ctlx=s*uNDy=mU zAER)liGNg2gNANl9Jw{9lh+8by5J1w z)y4DYAwO+wfok>qR;$NK4CF!z)l->`nRCm`?S*Vhi7HCNR!a?Cu(<_f*4Fq5^$S~fc|Wr1hWqj7V!R9wg3xSkLU5PnD&rf7+g^pk7CVkxKq}OdVvw>b`9?#BElwY z>x?zCzShf1yPz-Mj-o&Mqh;M2*Cz_(VH~mJ7_m*c(=)+Lt3oSy@7>n17gOwWG;JY*^&RNV$aygQ9W`q|goW*4(-d34oAUXyf+JZB$fjNsd^OiBDEk${n=B8@nBFE|JIK$TC ztkLJ%GmtE93(9hC;oLB@S0hMhv*=@mDvM@1sYsrW78eAiE`eF-b8*u%xQO%3AU-sE zNLnYv28_3KQyJKU$JN3!`q4J5Iz*UU;peTRaM?WE{>Nd|TjQzQiQCq%2un=7bKOQE z+SX-@LcVgdz|oWKXe~?8MMUz;q*MA#X&D^b!d|`*HxGr=5{-g}CN`oBCdzb2T)_gH zXOPoLn1U5aI3I0|TJ4-s0U2r{M>t0+V*{htila`&ym^&#F9ht?WfdK~)tq7T?|>iw zEC*p$k2a9!1N!y@>|*|T*dLmeEU=nv8X#mQft%5rf**o}CE9e1NG?)L2m4=(B8D2|_dZfeG@ z5ic>LKcbILSn!*_S*u+g`T1}EHue;64)JUe{g*E9@h-r}V^gE>)&>21`}aM@>p>Gw zKZZG#>)VHto}=R3NSWwTR%08;cjqzr1R9k}NnnftEz7>VGY-Jt*V zpMMY^tM~`;v!ebV{Eg2(34Wn;O${Z?xxj}^D}-9i%h!T7p^2Q*QjDcVc!Fn)pvU6N zL|MLEhH)t#wUBG-{h067+k-&|GYCL-Ic!z62O7C*1UWbKz0 znn(G!A43B;V=I!gT7vhR>-yAK#80L71i19t9hF5QV1?MU+a^yb(E_Uis9g`h9D`EB#l# zJBxK^^cP5B@R8j6XkL?)J)oQT7QxIubY&|-WN?P;h|E9uQ=nQK--zRu4HI}NqntdLq+h%v65@Bp!m>uoA;5SAzVv65S?)ww2k08 zEWjg_GfbX~?=I|d?(7;%a$Yy;6MP&i!7Sd<_lHGdbP0i~KuugjEj+@koo#3rn8OuR z9=HY%H0Wl|qk;#7Z>(Q~etPL8OciDSYu^p}pWVgWd2yMH1!nTxf9ZNG$aCs{?aepe z{BA#>{!7_Qi*4REN1pfTYj1w-O;i5tIxN_Bi6-PN`xs#&Te=-vp6^(G zCBE`N<$=lrl?N&hR34~2P-i(=-{ODs}wp{=Gbzdc| z^i&?GJWzR{@<8Q*$^$>h9$36=Bwhk>1y^oG#Q8R) zv=<1G3(}WOR?9M0e3b|GWLlYnHDI`W7`U=aGu5@<8Q*$^(@Lmh=GbMw(e2 zUNYMfY_lYe(#Vvg^SV`e>-ilgasy4 z$-DD_X3?$P$zLqF7$`1gd>T38wF|vW&Twt%MaGT)(=0mZ3Rd?(x_XvbIW}$svjlHO zmz!m;a#tRxJWzR{@<8Q*t$E-f-JoZ-Can^*mIodK*2=iGOxJJ0+C`aodOuy#^*>7A z*SuhvSrYq54h-76Z;Hn^dZ2j23G<*N)9aq8BP?n*-;&K~wt$%_dP)jgHDcKmo*5*C zd{PAF(1Wk4NRr^^V`)GoC@`zc;-&Kue@#XN!W(KfW~>u~ z)h3Zjc_=#nf;tZSTcJ8o{yET?leV3tklT(V?VKkOk&%0V!PHeiuENZ`Euxe(*PW7x z@}c=BGK3fciX;wW0C4D# zG;!ZsPij$=@D<6FRh~th=sL^NCphq18o(OsQ{?oKOThvtuTx^*7e(R>Ssqfxpi2$v z(z)g=T0-KIpipvomb2p}+JmH+y8%=MgT&F|z!Z=LZLmFsjXI@XCnJx4d6B*l#Sy8F z*Ukmy_(8Ez&la!|i^OofIgnnv1~0ZFwn;|0qc4HsFs)<4nX5mNel4meMEC<`K9tjS zSJ#XXo28sIR|uMqD~Q2~mi35yX)?K#aS4t-+8Vml2II;%!(7M{&yxckqHU{UK$sTb z3Sw~B#&SBd0a(JetN=GH?~|K!mpj8J!>l*yf$JWJL{LnQMuCfz2gnJ2$9LBS7U7S6 zl=>IV%gaT4%cY|~8}-W)*)A@Q?p$14HkV*sf~C|jo?n99ur!-5-TTBR-dd&en<2Un zKR)i?e!l>Ra^KSb*K?v66aOLFf_DCs7nWymc5p zLmBcFH5t;a2(DquIJ^KthQnc-{_x&=^AKH%*Fn5Jf1ejx?yyE>2gEOPiyw|JwDZA!Bpy&h`9OzxY1&az={yhfJX1{B?}@X&W4cl zqdkXPZqxI%&bDVfrF_-7G)s#yJ}*OTW)3`ZUmvV*r{|Z`$s^Qdct$d86tQ(@2j*;f z#J9G&Fncf>wu+2Pj}%86++4M*C3=h56USmo%w^|VH#P53TNSB^Y1U+f~Yl5{z;AeM3 zD2IpCWkXh0%Hv&(X;~Hyg!Tt^F{aR`7wAo0x^#gpU|S1?pvkgNQY@=xBrv!ywE?&> z4q^-$6Gu$JF}0a6nSsZ7G2}Gx3^pcZRt5&eG#s-|v8<6Cw7|x&S3}}nUM<0BOs}6C_ zY`PfJe&EZ7;h7<=$j?PW{sFL(S2`e(Q!S8E^76)6yEC|+hiu~^tu>sBGhuOtu+Bp@Psh~ld2K(Tb0S`~ zgCR=*FYZ8sJ9mQsg5;cxa45KAU8ggRRX&6jBuE_~tkDEQteC+9QWQ{vlm$>jBdO!i z`ixGf2lMl|(>SeKG$^*9BQh-c1mI-8lTj`|0nt(+Sxiop$<5?Jy$Wz@ZFGU zB7ZDo8e^d~7jZkYl`POC5YO=7LQ=2YKIi_LDUv!7UttR%x9R9axHluXzu}=2^WdgU z#M&Hg>O@b79xw&i=mRcb7;=;;_>sxkVo{Et@r^00hSVqiedgKAX7l(v!8gCj#OIUF z|8$g7^HbF69~~UhbI(5hGoqsdx_r?2M+^GnQ9b>?==VSP!S8_(xX+6LSB~!QDr67qtM&joK@tDi*}}lT7t`w|n=|U6kRS3daDYKKt3@ zPdBfA<=3zJhw%2*k$>QMKmYS|M6drXFAF~qWg*cUKGy?|l^~+y8xL-L`bKSLJNTP_ z^Z1yk-#>oPJouGgC-^+~o0K1Y@{{fMQU7%sT5xFUA)nd1&N8h3=}xVG+<7o79dz6m za2tFm59#9w|DDcFdggO{Q@cqA1`7&-iM|fXGrz;3`GDQPIdd@n{O9Pw*Kti+2~1r9 z4i9;)uzCOf;R=}w)+BkYPac~8B-@Soeel z-(Fb=L_iK5{?#}8{W}+5STX;t)R=uqhyBCD!w)o@*@^;~-C1xOozbcm+`skaz=EFy zumuv$fqxj6o3k~^_SWTrEDvTHX67xy!Ut{=jByR{ja=f)-90D+;BfgEBou)bk>+3z zhyz_4Wl~{FV8VQ|n`baaL0FF+j>1wnZ9d4+WJJX%r5rC2bFq+BK2}+(3Z^Kh) zc5R8C(j1)AHeS97~;{k9D z4hldOB*E8!tP_YxO#x7Bg&{1=isDEy$+ZxcJK_{Y3dt5ijBRrSm5sU@*3jdwN|wcO z4IIGn8b4`b+}b3Y%m;%DL$yYfC3s8+Bo^Te57?&bD0cDgq!md}B*xDMH>iP`I%XqL zC>x+RgeNJ&H6QCn9_vJru4jP`b*_6lKgl!^9s#663!Ndz2PU)op zqwP~lJ&a#9;^PNMq_a9{Pn{yI1rwqS9gYO&Q zWu2L2igVS$G>zR>fQU{|J@syOhDSv;3|zf>jl6o4o!fZZ>mrUzOgAunttV%-vxH|| zwb;Y77r2p{#dyra8WFn4bFCrSoN)D8D4Szbh?y)TejPT~GjP}IUK_YqtDp2bz=(G< zwEkM%KP9btb@I-lkmue>O;Q>%uA{lwy}G{cQ9bURK`i!-=|cQegi0Nz*L0M5wQe^7 zs}P+Nh4x0mHyD0R5tm3vb3DWoxH=mhl7hNj%6yA+}Ra2C1f34#5x9(GW(5fF6>D}*9`AR}-;aCCm|cY^Yv4+U5pTJ@Zb0Z6De z0-Y>ZKuY2?25}p$s^jGYa!u3{&e@I6wCC58n9@!SxLd1n92b46IbKJXkj8c8tJ)b_ zK^)=*b-m6P~SmOp|Bx}-qd7FWY!J#=1PFiahu6JauU9WjPI#Xzfs8>&+ zoAeUgfe=5#gDQoF=p}hwCAb`tc1_jE_mXxOd{C|HQ0hr|M%R0203nnoniw?OH38V| z+XfHQO+#&;`REUzfN;$ffa=Fj@D+#}=tw4uxWR}7+NuN+ZCggcl}_epi!)rs=#?@N z!&Y3rOrC&Tc(F27WmU$JsZ-{Ca?^4HKX{*wKVV9kJ{IRFJuzn!x=D$N+%%1lbKW)d z0Y?!iG!f$$Apv|Tg8kP4{9fDT<>4X5^2Bi-)HCM!Glwq^FAskg!0~2t`dfHDJ%1aM z8Dua=q17RtD;(W<^;H)iXeun=U6X79t1DXoS@;bt;MjBve8BV1Q`2Z?E5_gwk0Orl zWZ95xH8Jbs$1KwxtnE_(jvL&3Y|_{Vh6izL=};2pFa7(?uk?TJ%Lth=@IKITI*0qs z!~1WAckXcb;{L^bmdNGZk_B|X`Q@)Pf6iLKIwmb3W5Ll;*#cJYf8DPgh&cBj&cKQP zj7cY?6Zi}^1CC*fui>JIGSe#){m{c7Jq$lipT`^-b86OS0k;lZwA{1t5r6e#4^L{Z zH{!4M`?$LDK4x)E>ysZ*RkNGPyFqBS@t}AuMcPT>ev`}oYWVWYU;gsFw_i@~-1+jCbJ+RPy*qa}W!bVjzVC_eiT-Q-FFOm2 zFQ!<49u5{z|L{IFx$LioTw=Ds_tVr`aCF2ePV%z2e~2o4jc&(06f>aAxkVC$f@Bj$ z&H>VSG(G6deT1h%KA;XmhJ>2~kFA9cwZs9MF!bV-3?lZfCW|;)vI&jd>x$G_NKH#n z7^2EJ_M%p-@mSsz*D~5$lrlG$X*rq3H=b<+d%$|Zoq2Re%0Fj%#?5C>(jbey>x zw=gZ_(#n_@Vu!rtlyX=j(nZ70fLo1LaPGq_KU0YEi)Jz|wFJ=Cf~?3D!Fwsni^}wK zrk#sM>s;!nL71baz68k^3NthC2t))(4UGUw!Zi(tdt6nLI=1a#SS&*%u)l^r^A(~2 zjsnVFXc(IG;A@tsAWv$j<5)e1Wntt;T11!$a5hZ;DL>Uo#O9R1iZO(;^b$uAgvkZ4 z65D9l6)EmZluPg zoS-R?T4K!%Yh{SSik$E)z1wo;|`#Vn^cY}7bha`DY!osswV}ePsV{8T9JD>BnYLr zJSUX*a@IhKANl~3GBr;mf$?n1#7|ITOji^j@222!8v`g@;WY$-d#8nl7Br%M+Sb=e z??h=-5A{wozf;^meQ4y|9O@_bBC2=!R$w%sscVWm=bnx@F1?d38p4V4dkNzNTO2Sy z?`7L)2WZXRZtkC+_MrT%-m9OXwc`;bT3WAz79o0A$i|ii<)w`ig;=i88W8WvbA^fY z<_>`0^Ejt8@|D696KKfM&O`?qOq+Yevt@emZtHzK7dF_$9i3A*gLa_-5})iw!)Epk zavu#sy9&IZ=1Yzq%unAu^@aHwq|p$R^q@O3KTAToE+yKa0+LkRpi@I*304Z9`8LGB zHzZ57@xc_uMS+tdJQz$75108j0KR)z$Sn%^I$85t(N@G}XH6`Ik8MKvw$I}g>)N4) z)-VYFOT_rt5JZTfiNZ)}ta8}B+!AbE!W1n*X%rYY3`rUEGtod+;Q2^$vgQ*5R)Zoe zk5JGAh zM9uXeS*(WvXO2iV!Z(Q63}707UDgF%tu20Sh<6-t${BFpBMTH zcFZCJj%Y3<1n7hsVS_2NK#wG7*bYiW8P08)5#l7J!~k4T9inTds%mc5N27o_pqadI zBl0?Imc-8sBtiv1#stWMk^ytr@Tj!NJu8ApIon?hpIhT3=rvoz$rb{7uxM6U~t z9XhR1r+uEcFjhLtWzq4Jq=lLbfIkOV(2)FerCzUN(TlH4{B()IF_y6^MRYG~p}l!n z59xLiO<1Qnk0UJ;l&sq}D`ke;2*zL$m`C;6iGXUat|^uv)Tz-xy3Z!K^l2E04RDyo z%$|c*jDmCO;tNq21Y^1o!3@HJ?`fM?$}I3qvnBFeVcn)}E>cT}^Lb~Z;Oh`gKwwXR z2+~q575RsV=j_-OFsMh>PSMx)x}jM+?qN0Q6chPw-o|!Z(Z#aT2ngy)k}W0j5*bFY z9b6h*7yOu{BV|D{^l2xXgHxh2UKtX-I0h~7dRatCCli=M%Cp*Ow>O&Gqm1AtE%kt2 zulZP+#UdEhx@Z&dF8`cS1Ge!%G9X|9wX3{ZPje;kY(R%6r?q<0>z?Hq`CKdqJeNR! zqm@2|o&tE|EU&$hmZ(j?#w%ywnr}hsax=z6fw!J}y{?XZ-3g>gjIml9VJ9*>W&i@6 zv&x0UDGnT!R~F2eNm*8;pGj#Ng=3k-XXR_GCuH1eVXw3=QHf`!MHROJtayzA;&+*H z6Z3~s%9DZ&Y+*c~qYp4kP6jdJwY3KvWxB%&?}WWN_{c{rY5DUXe&q4vH;#B0<+70H zkIC`7PiEe|yvqw<%UJ-2m*FpN@G^{(SWcN0W(!!I{j$ts%XUeZQ~9;@KE~URT8+Oy zHGQkZ&wS=_|I?qoG;2Mp2!8f6zxDoCUis9g=I8m$XZ$+@4!FMd=`VeWT+a+SoF<2<=uewiF8%077q1fa^FICg z<>loc{O}+AFb#T%DSBs;-gx8Xn{I5=Pn=+IiwYz{0aRx)RrUL<_BudoVOEE5AS;-5_a_{aNAx_|q29~!^#g~R?! zFI^qn@4x-FTgjZvF-lXkIQoEr1$24u-qitJy#2P5!%a%z z$Z#xx@`z61W>Eq`EyVE1ma-B(2aOK~Y0iU_R)gR+0;*`D8p1-pZWe=D%(4N;yeoBi zv3A_hUOvMLoMj8KFTf2^*m=u2aGI{+WvWJ#Wht5r!pel~v=+POOf29AR5s2~k;XK0 z7$qQJ=+CE7(1YkO#4WP~SYqRuyU}r4qHh>f$e*DQh4*-`#ax&u<6Q1ViRBU&wP5cc zi!v^eF7y&i6D-CG39`h`g2N_e28bHLhT#m+g(y@h4u*1hP*;PfXHwz2qL3y!9xI4r z$S!JHV#Wx=ZGuk72F@ETrWvqGTxVD3rJOhrrM{kGec#5SRNM<|<*!^u%V``P3 z(o8b0LgCIZGs<%;DPpZK#d;Fqnww$*KWxlAZUvY>0&fRw&%w^sutO4F12%#=J`RSW zZOWEw0jeOKMY9q<+}Q++6KWqX1%Sunr%}3`w2d%2B6e@=DaLKt4ko1LLc;raLz?hl zGic+yHNg1M&B_aND z<4kMEA>3Gir)KFa3wWn(e${MVTwvZ=Oybv8I5p#q&htO?a>>> zd#K3pI}@2OcQ!j_9iCv=3gHj>{Jo0n1ZBRMah(=ax;OEFTs<>d+;IM3^Ye6pZ`ZER zA4(mDki0E`1$r&Vxs;`BQXt016pI(xgiLe5RKze{ zmNnS446o2ac_2vQpb@)<8J7%Y13qa(Qoyq~%3w>RGuJ|_@5>xh!)rQ1C|qhdGW>W) zDT6&rP^76MdofPcx+&4E@hb`%0cxFFP~>}I6hwR_*dNz`8q>7&-M0Lwa7;!K)inGO z*D>Om*-L?#`6<$wLJKe%l(N`x8p`--W>w5gC?rU3`B5uGG;D=EoS_pxufZ4PL^XiA z8nEEG5MYHcfI_YYEYkAOf2cUfcz?^z0FNhPAw=wXzAsa_D(>NRh={j*@&g&fGpxv` zd4MHj*oH~uwjqfcI;zL|?5rNvHP)+jyWTxH<4~7Qp-pSeIp1Y4p}O`7yMKv%sD>T*l~(V!Xi5%QqNVVUf*M_ks}Uc2itykBL=SJmb~4ID zi-L~g27*<5aBml&NkJm^Qg~hiFN6y`af1n7E|3Bfu)&o7hfyAYEzM!VcGW{WnqbC@ z;CRW^i{WaaPvu#1qPq!RK*p?Cf(HL{6_D248nz6z0Q<-Ar06WI`&~3byewWjJK-gL zIGq7cXc&wEq$3+Mq-~wxYrYS3lqd1}FMC}^ohZiU23!pQcDt9S9%kp<4)BigwgDZt zSwT(1oHH00U_#MFG<4+#*JC%4l)U2agHJ6u1M_3X( z+JVv$k^S$HIzIkYSb#OipKj9eua=XWAKkqLWqs4biCw+-rl)RB<*!)ro0nV{d^A7I zGC6*y|C78Ty2hI5@>cP4m|sO3kn|Pk`H|xshkdh_Ex^4ACdJ=eUfyb)_^&u0!GFc! zHTeG-V^P-kP@csJK2Y%R)_?ayxK^{(1g^}D;y0f;I5@Zuu$d9~6J8IuG3$ku#jcQn zYXAnY1%K6yNeH1Idf{iS1&Y4E)B0yaC2q|O(0l&^U|Zksn-JdRF0f(Q@d>W~q0e9Z zK3nivQlBq0e;%f+r#O(ZB?J6)po0vJDI+OS-XXZ|UGPn(oG|5i5qMSx%`e{a>$icH znn%HnF%g;5iaOwLIudVRF)+mfX;Y@2aiz`%dqZuZjI^K>;2bxRa}9tm(gNmcbW9Eh z#J>hgiz$#LN|y%W@W*^@#7Cgq`-+j2`H@1CDM83(FPT4?6C6<^qDG^EG*)A>CkXH{ z0&);r(hEg~V8odNAw|Hd(PUqgWLtHaWkl6TN||eRcqEG`ro)b%%gT>dGE2}F%{|X` z=G2_BL~WHLB|3t}?`o8WMQoR16Ii<#=b0DhkHwgDDK&5)`3l2>XPm8Y)V=*N0q;O( z%qK#^*+8$r6KDl9EURsZLbD`{K_>(nf~Kr-5@3nQP8^u#+Vg0Jj!BrFHp+?EKpB_b zx7))(RgMwwT^Pu4#$ukIb1aGK!gfm-y>1F}RDcXk95bK+3~Ql1aQ@H<1GbF`OG>T3K|b#5fbj_ck+2(IzXGEY7UM- z%Wr8-fv!uus;_fSQzRKVkbZz!UAd2RDYG%R>Ig>y7Kd$UA`doh``vC2Mv&5HI8OlX zuXv2;sfmPn1fepxpRLBm1ax`!u{gh#JOw;)UaLnQN}inuQ_{`jJ|Rw~B+VchcM0C8 zZT>we&Jt!w!#%|WyrqsQV&Ekr2oiifjDc%in2?Q%bF_tFd{Ib)0fi#QiP6l}!IvdB zh6$+Q(^Y;~>C6jHl_!x7r^6x1fHSH4S)kUrLW?1XF{03|2Vw_-b3+SphLI*bNU{O` z#zaWzIu?vb$`Lc~J&jPYvhHVb;AN;Ys6p{3;XLCi>59pe8I<~PANzYK<+oyaR(^xI z&76EJ+oQV$zsdK&rvC95)046ITG6k4P0Cpruds5Srkpyxpl%~9VnSKbqy7K0@ z4F<3UYtEsUwYxoJoZcx7(>bID(P3yn+BmR`1sf}20n+@OsJ*Fm3W2rxIfCggd7I%P zSj1t6Kzb;~lx<|-J4{r`5@CeC_jasvrODR)^aHZ6xgT|i) zcTu~#c&D}`112s9Yxqx>Bug6xD%(|Jm>QhIJB2hgt0Tg0vlw#%f<{FU7Ry}PJj|SY zYzjF9v^2l`!f!zb#L62%3+MUm*#3*%Ii^a8SP~iqpFeQEy|?lQ)wp4gK*x+w(JmxL zsQq}U6C%e6Z4m4fm_sw6h1os&W41>z)Akw!OT%3uF?hjA^TWQP3O2T& zv{gbCdY2n%yWU`93vwah&AEOr3@f3Q30vJ8Tfnm3!(Us*oS9Dy#T?p3it~%)Ju$(% z#qM;6N4WMC`Sx?)er{j7rt8_R1&XgJJzditsgGCNL*K+Fh_`Irsuncux2m^gg`KzMnB4!I0F9>i5w4@07u*%f$xQ>d?T5*8QJH0?sU7a-vYdF^4NR{d%A&p zpzhuRyWl#zD3bUW6bz;Nh&MaWHKnBH)|x_lJ{ac=Lwhl*e6uWvms9S%JkC9fKF-JS za<#0IZu@JmO4tapQa89R!5Prdt_cEftrvSg)-M5cdy%O81#d1|Fwag(hS$qi}*Fz zv(C!%cFnwg3wST@cFVN7wCk|I&AQFnIsQMBTSH&n`YK1|fi*nf**v2+VWCMIx;FoV z4?$_7`#VWV)-q|n+??%CbEV07K=3NI=9tilBkmQO>9Uza#6fG1noG}?u5*Y|lvwYv z+$^GHK2JDBK44qtgSZwG{d!`{Qr9+Zp;G`3EiF2I;)t7(D>~l}?U@fR@C+ zR3MQsZP#G>9GnvFgldVO*UuBB@s@9b*a>KR0Q&%g=p4H6>cMG(fBuAjzN1bOn6=#c z>4sLidXSKViF1w@l6xt_4StxHBd}M9_@Bk&A7>k@@Q;R^b$c@+)c8+d8E71dP83kq(>cE9PH2f}kp4b;M|L!;7E+u7B|RA`Sbz!;DiRq&dw~}VEic~X z|HCx=Qv1jk+xKG0Q>w%?`x#{y|Ka~IBV|YA2Zh|h7Vi8%yRn(7U`BRcLwJ{hx(2&P zb;@h7;F?sXQxFw4b7{vZ^;9j*YoBQwp5gNxEQq~ z`_hGS?K7!e>0hY6VyHY&d7$z@<$=lrl?N&hR36x}2V(5ny=GAFzFEMy#p5ft9g`JqMHVzitm2_ z&jQCcD}5t+r^xN_EMbe%C-N=z77hQ;siz$#JhwW5M=jSsaw$5%)y=PRZ0Z4ik*R_$ zdcghTAAU;X4t#8Bpdmn*V|;MC=c9smpa=4WHkCPA3%TD-3_3#Ar%eTNrj*gAu|g%tPl>mSc;y@Zv( z$^(@LDi2g1SkVLS36#StX5X0I+?v$lCsi9OnkT?LfpT~r@8Yz@GiJF!$fEQG*-0;A zsM2S9zzvpWb1a*p!N|urxCzoYeI&l-AWfBow9Qm(?edgGm84d|^*qp6FWYtJQrB%j zrN8pP50VFL$G&Fwz7l`2KuxvXNz4knJX`7zTvCqc;>*ZQ6 zrll))2}V34y%xx>MQf$B^1u`i=qa>)ks^|Kq?zwaU8U!p>wymbsXzsl2dLS+j{m|{ zc6^@>56kgu3Gd@S3S3LUDy8o#4_wz6`Ca9t%GlW+P_vVkNZI{EfF+EmSl%%nsAI-Z z!O#QMFk$G6DpYx(@<8Q*$^%ca2Q0EhR0Erd= z&_N?;pzgVb`Mp&>lsR+i6p;2U?wZNY!)rB#X%&*xq%HqMd8dm3_mZ5`^E;{$!osv@ zz~2-9qK^5%qfK47Ocrb88KqdSjMK_-SGOga$6-YzJ)By^5V6WK1V}E&i*OW2)5ude z=aFK(){I4_cJ9Zr(>9%KXN13$X%#U^7(t{0K&cx~vL z0MQbgTVSPXN@J2b&N`?LZV0AD4m6?)CTjuz>o{)L>dAm>{Q#~|O*QRxp*BV^gQ#*p zPt=zQ(WPvf3VLoJ-OC3Hs=!}a{Xt3BKoO0|HzXJbAw;>4Lnvt_TAlBC{~ zn?dV_%{A`Yn{fFQc*6gOd{g-AfBm`VoQ!YLzi`1Ze0BAiyJMuSMIS#NTJSGsuD$2^ z?kw0^QPvjp?SK7;|K%@#>6gFqXMc9^1|1(Cv!MQQv$X1mNdMPO-1w0n zIsVeGeCfI8h8EDc1@vpbMwbf&ZIFD#c}4i2{_>sw6pqvF(%p9q|}Ns>2iK+R7(r;lQH9LQkl6F z=CMaeJU6lPa1u3)_RL(|%s(gNQI=jf=hA_L_nDH+0E#csVFCd zQ!GS;NzEppjbI}|z}vVqbxk7#$j!M^I21IaiA!xN)ueJAoSUoH&?@ ze2J(n1Jkwn4MW<{Y@E-o%5L( zqqJT_NrzA`GCSNWl1#jXX`)Z(P##d!KGU&Ig0S0z50Vg)!$kXZ;-AJnBSbfxC7Kc~ z{dTukkN5;`Dq!0xwh>7+-~kE>WE$^D+MOA z4a#I!p(@A|T!9^AhA>=$UB4#;qTsWYgcMGOC=MCO%{e9oY?}fT;-ZnocsxUAu@|=> zC(V(!9du*SIU5Qfc?Q)d5jRJ+JjY=`!Ts%;dDMU@q!0y}5t}%WpqT;>THGx#Pmviw z_tC49)~ZgYa2|TBt`2pVn^qk@<95sQ`SY5Ss5u`4>OpqGdKcY>AI7Cwe2r2(Ss64= zNH_ePgO5R+E6%hxoa+>~PHG++VbV+MC~2KbY->W1rz5R3m)}BQMfP;PUe_v4vKU6d zN8Fj+{cXCp3JD{F%dY64#)NDs(Fwh9( z>zaYHQm=h3a_&A1A7=o7EjIz%^i0s4?hb<^@x;V#61|TDH|at8i0BF801g#_g2Egl zfOK#V&@BpYUA`6GDtJn0 z)PmN7fAtSJvGpJSqYpFw#J~E#4jBK)=l-q#g7MpLz5UkX$Ia%^ojXU2uMS>%>FVmh z@NhcOb3`vT3B>}S*E0CI=Wg9PIHH3Czeq4t%(@v69yki&^!!i$Pfq?jf93eEF#hC| z|Jz9a(@*~8FLL}=cq`;LG}(gtfUARh_a-cO?&{K7;7oY*=qG-{&zpCS@`F1pr3~X1 z5FHiCGw?(Iy$8?4xoIo=plWCoKKWV!RdWBa8cnx_#L7Lt^u-x zAnEIV?Ld4kcbv=MBLMh*xEpSz!LgoI5;?fHxAx>lMXNYO67FF|69N1 z5}M6_r%CyU43{($I|~l`w=P~zQ`F`->(NvTZr^qm(8ZVq)SsxGahap>zkIuhhv-zi ze*gD=&&Ks!x%!||~FxTpp`arF84(pkWr8hyW?6&6ro z0s7?$0eF0HKg$lTxcMI)4K29pAFN@)gm`-&1i6JH9wrAQiwn}wa_*iP_&#EI(Kw4+ z8dG)vtY8R*`XPbGRXpt0`0WT-^v;COu(>rt=kbCxjU^qSmm}Pi)`js~YB9qIhVnd8 z!w84uFxtRqEkZS!HW4gmM^?0|7Wy|XD-RzAR^Y-!o8mJdz{snGb7wP?jHW)%*yzA)gA|3Im>6=^dj*&3gL64gDf*OtQAhtlm3lFxelZ!0z<6dSu zm`6E*bB!z>_OwlofHUI{cx}+gsqvc)CRI2Nhb=$4kl7iROu=I{l);tIWqQ_@qnJl=ln96A}4q^B4|@0Q!WlE{%gb$a8QpttqA8>#6BK6dT1(q z21q^y=#4o8&ZRLw;;Vrt4L_e*wl+@ITzsxk^ycdoW|z@G;m_WxiOl<$g(1EnHU&r%D5~A zDB}lN#D;tYVSG>-4CreG_%Sx`yOa$)g~Ne*)lh*7ISFtE_M=FLR12hWIHz)biO37B zUjl9(8-VcuYFaxP+}KE;6G>1RF!n%i#LwmfYGjE-3Z8RDElrf^wj`Y;BwI3P^VfkE zXKHv@{^dZ5@mGeyP8y}q1MoV0#+WFmMevk^2rZKt0&FCS6YYH8Pus8n%6#$# zR(hDiaaf@FY{ML~+=y#Xb%|~gS31G^m{(oxh5|HrY>!1H(78BAim$Mpm*oL7!i6bQ zPay?0pUIZpQ7dT^&?rW|Q#(JirE;!NXOWLN>IsEBRAlv0$XF*h15ROPj;w%CGhtoO z$f(JKTv_j7y2?$OdmgjMLtY3v)f7_dsAqe*H#i3$tR1@~r0!}atOmUnm$09OU*>j9>MB%ly#1WXtR$*C=V?y#B;~;<;2tnmZ9CXRr6R9$mJf2S8c@_i8{_?;wJr;rC2#ew)NNXB z<5w;LAY)Cgi6uE+)uQ7g9p-QrSPI7+lr7*@DYoG75Ze3J0_Fqz z@g?23;qtuuFt0U|{Vom)Xm`w-#XI^v03P6_TyFgF5(;X7Jz?YAJ$~dP2Uo}a{^6%T z%@wpB%(p;dpf*rHu%JI!kunyb01qBeX_xPcmORuq=*K_jsXx>r|KJyKxv8%+1^W{o z(#@Pl14`e_e?0aS>6`RpvG?M`)_c8wJ3_j;g;l{QR`QVk{o;tOTn$?bZr>j6{bUQi!Bv0p z+H04Ww{If|jU@{d#~o~L0ZU>P{R_9q`?&eoEcYHBe#`8Ly>kb))t+T$s)V zb8WiF+88QEEZ}_-{g2aCj1Y{_3t=Y~k6)GBP&GwHCu3rc z*;yHz$bL?k8Zl`6%Gg9kPp-;Fshh?m1ZXrjq z!7P0plSR};D`4oD$0&?#+z{PqTF>gzHo^%W*qob3S-g_R{T^3~HhAPTg*1}BZUn81 z$Le^*qyv@#JpB^nsmrcFa9hZQG<^XuO$FCeOikQ~c(>RA>o9u6Vn^(V*hl0&86j*t z!t;XhW7|6B%Ny6u@jU@%Fq4HhbEiESVDyhWz)s@#WdS|(f9~L!&*j(wYjNtoa6oB3 zp`Yj2yt9^JT2r+tYn%@c%}n_LXDz~ONZBMyq1DV!uEzqlo_BLI{xE>?{^9y9*ngR! z5jUhVj75h@+6Lu-Vs2l9*p34&$Y+J=j`b7+RI}(ZR5cimzyuj2Maj#PiXrbBp;ZKF z!XOe03sAGm5kjdHm>g3O^KwT4A@S6nVNVuVz0#u5^R6tArnNa;7&R6@M`4U=C`D&p zI3=D{f<+@k7F$Lhwhw1-eA&iaF{_ANnYZw+EHVPKJ~V`mS&2s6KGoufH?I5+7kO4j z{M@sP}X!cJ5N8Vm9MlR|TOo_O!dV-@- z#DVq&-@&Z)`0rv}_}A%}b$%9cyJEX93j!!Q{`X)3{{TEz`t9Zqn;8wqp9VO*dH8|i zk%B2MK5g~MOaeFOIfdL@1n*T$Vmd&ODy zg>0`1CzNG?31UT9(gTBG?ri?y)KSl7nn=M-qTa%O!d7EJE;*5Pf-oGfPmX^lDW&Y4 zP*YaxaMyWFz^l}lQt6$mZw)l?k~DvAw3yY&Kt__{ZTTRC+>nO=_;HBi_KwW)#Kf#- z%fW<5wuF}LB5iZTW#fiBY`nG=WT0{BEm&-=z?XgENN;%nKU806oQWh4+;#wi=Oty? zSvf+aOjHv|6IkO^XyLbIZOtYH#nnB(0lNS?E?ovLv;x)>ypxoICBwi7TV)Z;@ndXP z-c7)qgdT=xhiuung}JL z#L}7B{n=97dGVmqVGrOhP@W zo#RVQHEd!($47s8*TYi4>*J`TxvdszGz%NUpfMc>&jqpfsHUO*44b%hpn7M>upC6B zqhvnoU2z;xF>xuEQAh3y=>vJC9?NF2KR?vZwM|3*E2WI{7 zAsV9SG6n6S+ZCL!6yP;begR-UoEBf=LNyphV0;zI*J<(UtfANIk$=V%6{Y9rrLR!U zmyHdpEHqibh1#w&UkRItQC*nTYkBpW_M;ve;kk|#Gt7m-y@=mFS`4|6hRI>Bcxu^8 z(Kh2Qe`&ha6=pj;*LWI^@>#%9dlwi!~)_p26}uv+>xTEO3dnotkx?Y>~%DqQ%1Y`HCkcM-2v z#M#{QEHGL|EO34#+x^+#T>VI@8Fj}EAWANoIY5aAnB#Pm4lN9F#9ID~h~K6J3m zKj6l

xcsL%MYs9xS>)PIu{WuQvPe&e2)8d%Vxt&xs zA|^mglBJo&f5e$K0&Z-`6CF>_AEk_B9E(f5^g<7_9?SDm4%_nm8a&1SIJR+8P9W zw+kR`PGyma&8P#*Vb10YLZ$d#gF?uL*sI2IWwk`N)Hrd!am=0Zv_4-LTNQf_P zD%^ORt|wAH!xJYCb%wlZUzE_ylY4?Xzu`Q^AP zuHATGudjDZErNL%HZ`RpRvxH4u&D=@ovLlBXIlQjvI!DlhcdP(Qqy=V8a%-B+}vOe z@v$MOb@MO1I=e`L5rm3w@FN6OHwM*nZUgw3o_VaWNJ5ofd7$z@<$=lrl?N&hR34~2 zuyqfZf%#Oab{#95nzkPz_ApBGNv8d%tF%n>fcXa;(-QVZLqptyF1ZIC?=lt1z+Shj z+7ZU%j{XCM+y8%i_pjtO5eEQRzW9>xCmE>dn1ta0E;E!A(i>1whl-Alibk9n2HwKF zK%U{$)9?aJXm|;VV^`Mt>^*xXUu4EXf=0dOcehOyh?A7RRBD z&zGiYp-{#%+G9;OojH6DnsCc-Gi!f*ySh4$x9NvbUoIE<7Ub|D*ISIE@;qwhad4(; z{`;(+{!)eOi1jq&&u8^|*+Ftu@j(@To2&}MITY2j`m}iw#>oi-MHQiE&7q%D*|G_f z*n?tH#oM>T_)Jas(fL_1FUqj|@&MlxZHaobxGciZK#Od1IiJN#$;JrFgf~vI!5^ zxA!qzO{y?HQ+fV0j@;GW)L*u5&D(W`SQ73sZ>M%#rngVR_)IB3L^N&Y0zdwgFImn1 z{bn^c%=~x%E*~^~^|lM~aSC3ueCf#fO~=RZYgG?^8hJMe zN8r8+q_e+M+P-++IPAIOdh5w(F^br#)S}#a>DBe-@2|jkdwsk}oA*|F{l8pU9Y+<5 z)9SL7)n?x_f%b{nz53LSI2CH98=X=*!uLj9s4$B6Vw!hp>Oz;55FkK+zzGV}`}H|} zKeR3F*XsTUlD1~q9ThjE{o=Q!_CGYI?}xUfJ9I)(0yhHn&Fqop_J30xs>2NSkeuvM z=de}Mxx!&v)!IW6s23ZX{svX!Z~Ijjvg^X}-&W%jh)93{f%i-xKi3+)d-)mf*d55v ze8-M29)Z&oNS`N%?)_MCZg0m`cU|7+)!R0f5FjvuKpkV8FRxdJ&r4%ZWem6&aeM60 z;t?P~fWSt9boPFA2oNAZfB*pk1PBlyK!5-N0t5&U zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7 z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+ z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly zK!Ctb0@tSNoxl_(K!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+ z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs z0RjXF5FkK+009C72oNAZfB*pk1PBlykPA$@1zq|ire78xrL@S_*D?RRc$}|K%kwm^ ze^)-Wo7%~{yUdsM)8cZOTh65VDZMM+uIp33?n<}C5B2_xeyM(u`KEeleV)(DziU3l z*_Q6w{gs*@3_AX z-v4{vpZs;T+z&lx^7?r`-ye6aPp{vU=Jkipr?@E%43B?!^`hAA-^CY`=f!6ie-x8% zUWXPo9EW=H_A55|{LNhjua7 port 1 switch + PORT_SELECT2 : out STD_LOGIC; -- Enable source -> port 2 switch + BAND_SELECT_HIGH : out STD_LOGIC; + BAND_SELECT_LOW : out STD_LOGIC; + FILT_OUT_C1 : out STD_LOGIC; + FILT_OUT_C2 : out STD_LOGIC; + FILT_IN_C1 : out STD_LOGIC; + FILT_IN_C2 : out STD_LOGIC; + SOURCE_RF_EN : out STD_LOGIC; + SOURCE_LD : in STD_LOGIC; + SOURCE_MUX : in STD_LOGIC; + SOURCE_CLK : out STD_LOGIC; + SOURCE_MOSI : out STD_LOGIC; + SOURCE_LE : out STD_LOGIC; + SOURCE_CE : out STD_LOGIC; + REF_CONVSTART : out STD_LOGIC; + REF_SDO : in STD_LOGIC; + REF_SCLK : out STD_LOGIC); +end top; + +architecture Behavioral of top is + component PLL + port + (-- Clock in ports + CLK_IN1 : in std_logic; + -- Clock out ports + CLK_OUT1 : out std_logic; + -- Status and control signals + RESET : in std_logic; + LOCKED : out std_logic + ); + end component; + + COMPONENT ResetDelay + GENERIC(CLK_DELAY : integer); + PORT( + CLK : IN std_logic; + IN_RESET : IN std_logic; + OUT_RESET : OUT std_logic + ); + END COMPONENT; + + COMPONENT MAX2871 + Generic (CLK_DIV : integer); + PORT( + CLK : IN std_logic; + RESET : IN std_logic; + REG4 : IN std_logic_vector(31 downto 0); + REG3 : IN std_logic_vector(31 downto 0); + REG1 : IN std_logic_vector(31 downto 0); + REG0 : IN std_logic_vector(31 downto 0); + RELOAD : IN std_logic; + CLK_OUT : OUT std_logic; + MOSI : OUT std_logic; + LE : OUT std_logic; + DONE : OUT std_logic + ); + END COMPONENT; + COMPONENT SPICommands + PORT( + CLK : IN std_logic; + RESET : IN std_logic; + SCLK : IN std_logic; + MOSI : IN std_logic; + NSS : IN std_logic; + SOURCE_UNLOCKED : IN std_logic; + MOD_FIFO_UNDERFLOW : IN std_logic; + MOD_FIFO_OVERFLOW : IN std_logic; + MOD_FIFO_THRESHOLD_CROSSED : IN std_logic; + MISO : OUT std_logic; + SOURCE_FILTER : OUT std_logic_vector(1 downto 0); + SOURCE_POWER : out STD_LOGIC_VECTOR(1 downto 0); + SOURCE_ATTENUATION : OUT std_logic_vector(6 downto 0); + SOURCE_BANDSELECT : OUT std_logic; + SOURCE_PORTSELECT : OUT std_logic; + SOURCE_VCO_INDEX : OUT std_logic_vector(5 downto 0); + SOURCE_VCO_MAXFREQ : OUT std_logic_vector(15 downto 0); + SOURCE_VCO_WRITE : OUT std_logic; + MOD_FIFO_DATA : OUT std_logic_vector(7 downto 0); + MOD_FIFO_WRITE : OUT std_logic; + MOD_FIFO_THRESHOLD : OUT std_logic_vector(10 downto 0); + MOD_ENABLE : OUT std_logic; + MOD_PHASE_INC : OUT std_logic_vector(15 downto 0); + MOD_CENTER_FREQ : OUT std_logic_vector(32 downto 0); + MOD_DEVIATION_FREQ : OUT std_logic_vector(25 downto 0); + MOD_AM_DEPTH : OUT std_logic_vector(6 downto 0); + MOD_VCO_MIN : out STD_LOGIC_VECTOR (31 downto 0); + AMP_SHDN : OUT std_logic; + SOURCE_RF_EN : OUT std_logic; + SOURCE_CE_EN : OUT std_logic; + PORTSWITCH_EN : OUT std_logic; + LEDS : OUT std_logic_vector(2 downto 0); + INTERRUPT_ASSERTED : OUT std_logic + ); + END COMPONENT; + + COMPONENT Synchronizer + GENERIC(stages : integer); + PORT( + CLK : IN std_logic; + SYNC_IN : IN std_logic; + SYNC_OUT : OUT std_logic + ); + END COMPONENT; + + COMPONENT VCO_Mem + PORT ( + clka : IN STD_LOGIC; + wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addra : IN STD_LOGIC_VECTOR(5 DOWNTO 0); + dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + clkb : IN STD_LOGIC; + addrb : IN STD_LOGIC_VECTOR(5 DOWNTO 0); + doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT Modulator + PORT( + CLK : IN std_logic; + RESET : IN std_logic; + SAMPLE_FREQ_WORD : IN std_logic_vector(15 downto 0); + SAMPLE_DATA : IN std_logic_vector(7 downto 0); + SAMPLE_LATCH : IN std_logic; + THRESHOLD_LEVEL : IN std_logic_vector(10 downto 0); + FREQ_CENTER : IN std_logic_vector(32 downto 0); + FREQ_DEVIATION : IN std_logic_vector(25 downto 0); + MIN_ATTENUATION : IN std_logic_vector(6 downto 0); + AMPLITUDE_DEPTH : IN std_logic_vector(6 downto 0); + OVERFLOW : OUT std_logic; + UNDERFLOW : OUT std_logic; + THRESHOLD_CROSSED : OUT std_logic; + FREQUENCY : OUT std_logic_vector(32 downto 0); + ATTENUATOR : OUT std_logic_vector(6 downto 0); + NEW_OUTPUT : OUT std_logic + ); + END COMPONENT; + + COMPONENT MAX2871_Calc + PORT( + CLK : IN std_logic; + RESET : IN std_logic; + CALC : IN std_logic; + FREQ : IN std_logic_vector(32 downto 0); + VCO_MIN : IN std_logic_vector(31 downto 0); + POWER : IN std_logic_vector(1 downto 0); + VCO_MAX_FREQ : IN std_logic_vector(15 downto 0); + DONE : OUT std_logic; + REG0 : OUT std_logic_vector(31 downto 0); + REG1 : OUT std_logic_vector(31 downto 0); + REG3 : OUT std_logic_vector(31 downto 0); + REG4 : OUT std_logic_vector(31 downto 0); + VCO_SELECT : OUT std_logic_vector(5 downto 0) + ); + END COMPONENT; + + signal clk_pll : std_logic; + signal clk_locked : std_logic; + signal inv_clk_locked : std_logic; + signal int_reset : std_logic; + + -- PLL signals + signal source_reg_4 : std_logic_vector(31 downto 0); + signal source_reg_3 : std_logic_vector(31 downto 0); + signal source_reg_1 : std_logic_vector(31 downto 0); + signal source_reg_0 : std_logic_vector(31 downto 0); + signal reload_plls : std_logic; + signal source_reloaded : std_logic; + signal source_unlocked : std_logic; + + signal source_power : std_logic_vector(1 downto 0); + signal source_filter : std_logic_vector(1 downto 0); + signal band_select : std_logic; + signal attenuator : std_logic_vector(6 downto 0); + signal port_select : std_logic; + signal amp_shutdown : std_logic; + + -- Configuration signals + signal user_leds : std_logic_vector(2 downto 0); + signal portswitch_en : std_logic; + + -- PLL/SPI internal mux + signal fpga_select : std_logic; + signal fpga_source_SCK : std_logic; + signal fpga_source_MOSI : std_logic; + signal fpga_source_LE : std_logic; + signal fpga_LO1_SCK : std_logic; + signal fpga_LO1_MOSI : std_logic; + signal fpga_LO1_LE : std_logic; + signal fpga_miso : std_logic; + + -- synchronized asynchronous inputs + signal aux1_sync : std_logic; + signal aux2_sync : std_logic; + signal aux3_sync : std_logic; + signal lo_ld_sync : std_logic; + signal source_ld_sync : std_logic; + signal nss_sync : std_logic; + + -- VCO table signals + signal vco_write_index : std_logic_vector(5 downto 0); + signal vco_read_index : std_logic_vector(5 downto 0); + signal vco_write : std_logic; + signal vco_write_data : std_logic_vector(15 downto 0); + signal vco_read_data : std_logic_vector(15 downto 0); + + -- modulation signals + signal mod_enable : std_logic; + signal mod_reset : std_logic; + signal mod_sample_word : std_logic_vector(15 downto 0); + signal mod_sample_data : std_logic_vector(7 downto 0); + signal mod_sample_latch : std_logic; + signal mod_threshold_level : std_logic_vector(10 downto 0); + signal mod_center : std_logic_vector(32 downto 0); + signal mod_deviation : std_logic_vector(25 downto 0); + signal mod_depth : std_logic_vector(6 downto 0); + signal mod_vco_min : std_logic_vector(31 downto 0); + signal mod_fifo_overflow : std_logic; + signal mod_fifo_underflow : std_logic; + signal mod_fifo_threshold_crossed : std_logic; + + signal mod_frequency : std_logic_vector(32 downto 0); + signal mod_attenuator : std_logic_vector(6 downto 0); + signal mod_new_output : std_logic; + + signal pll_calc_done : std_logic; + + signal intr : std_logic; +begin + + -- Reference CLK LED + LEDS(0) <= user_leds(2); + -- Lock status of PLLs + LEDS(1) <= clk_locked; + LEDS(2) <= SOURCE_LD; + LEDS(3) <= LO1_LD; + -- Sweep and active port + PORT_SELECT2 <= not port_select and not amp_shutdown; + PORT2_SELECT <= not port_select and not amp_shutdown; + PORT_SELECT1 <= port_select and not amp_shutdown; + PORT1_SELECT <= port_select and not amp_shutdown; + BAND_SELECT_HIGH <= not band_select; + BAND_SELECT_LOW <= band_select; + AMP_PWDN <= amp_shutdown; + + ATTENUATION <= attenuator when mod_reset = '1' else mod_attenuator; + + -- unused signals, ADCs not used + PORT1_MIX2_EN <= '0'; + PORT1_MIX1_EN <= '1'; + PORT2_MIX2_EN <= '0'; + PORT2_MIX1_EN <= '1'; + REF_MIX2_EN <= '0'; + REF_MIX1_EN <= '1'; + PORT1_CONVSTART <= '0'; + PORT1_SCLK <= '0'; + PORT2_CONVSTART <= '0'; + PORT2_SCLK <= '0'; + REF_CONVSTART <= '0'; + REF_SCLK <= '0'; + LO1_RF_EN <= '0'; + LO1_CE <= '0'; + + LEDS(4) <= not (not port_select and not amp_shutdown); + LEDS(5) <= not (port_select and not amp_shutdown); + -- Uncommitted LEDs + LEDS(7 downto 6) <= user_leds(1 downto 0); + MCU_INTR <= intr; + + MainCLK : PLL + port map( + -- Clock in ports + CLK_IN1 => CLK, + -- Clock out ports + CLK_OUT1 => clk_pll, + -- Status and control signals + RESET => RESET, + LOCKED => clk_locked + ); + + inv_clk_locked <= not clk_locked and not RESET; + + Inst_ResetDelay: ResetDelay + GENERIC MAP(CLK_DELAY => 100) + PORT MAP( + CLK => clk_pll, + IN_RESET => inv_clk_locked, + OUT_RESET => int_reset + ); + + Sync_AUX1 : Synchronizer + GENERIC MAP(stages => 2) + PORT MAP( + CLK => clk_pll, + SYNC_IN => MCU_AUX1, + SYNC_OUT => aux1_sync + ); + Sync_AUX2 : Synchronizer + GENERIC MAP(stages => 2) + PORT MAP( + CLK => clk_pll, + SYNC_IN => MCU_AUX2, + SYNC_OUT => aux2_sync + ); +-- Sync_AUX3 : Synchronizer +-- GENERIC MAP(stages => 2) +-- PORT MAP( +-- CLK => clk_pll, +-- SYNC_IN => MCU_AUX3, +-- SYNC_OUT => aux3_sync +-- ); +-- Sync_LO_LD : Synchronizer +-- GENERIC MAP(stages => 2) +-- PORT MAP( +-- CLK => clk_pll, +-- SYNC_IN => LO1_LD, +-- SYNC_OUT => lo_ld_sync +-- ); + Sync_SOURCE_LD : Synchronizer + GENERIC MAP(stages => 2) + PORT MAP( + CLK => clk_pll, + SYNC_IN => SOURCE_LD, + SYNC_OUT => source_ld_sync + ); + Sync_NSS : Synchronizer + GENERIC MAP(stages => 2) + PORT MAP( + CLK => clk_pll, + SYNC_IN => MCU_NSS, + SYNC_OUT => nss_sync + ); + + Source: MAX2871 + GENERIC MAP(CLK_DIV => 10) + PORT MAP( + CLK => clk_pll, + RESET => int_reset, + REG4 => source_reg_4, + REG3 => source_reg_3, + REG1 => source_reg_1, + REG0 => source_reg_0, + RELOAD => mod_new_output, + CLK_OUT => fpga_source_SCK, + MOSI => fpga_source_MOSI, + LE => fpga_source_LE, + DONE => source_reloaded + ); + + -- Source filter mapping + FILT_IN_C1 <= '0' when source_filter = "00" or source_filter = "10" else '1'; + FILT_IN_C2 <= '0' when source_filter = "11" or source_filter = "10" else '1'; + FILT_OUT_C1 <= '0' when source_filter = "00" or source_filter = "10" else '1'; + FILT_OUT_C2 <= '0' when source_filter = "00" or source_filter = "01" else '1'; + + -- PLL/SPI mux + -- only select FPGA SPI slave when both AUX1 and AUX2 are low + fpga_select <= nss_sync when aux1_sync = '0' and aux2_sync = '0' else '1'; + -- direct connection between MCU and SOURCE when AUX1 is high + SOURCE_CLK <= MCU_SCK when aux1_sync = '1' else fpga_source_SCK; + SOURCE_MOSI <= MCU_MOSI when aux1_sync = '1' else fpga_source_MOSI; + SOURCE_LE <= MCU_NSS when aux1_sync = '1' else fpga_source_LE; + -- direct connection between MCU and LO1 when AUX2 is high + LO1_CLK <= MCU_SCK when aux2_sync = '1' else '0'; + LO1_MOSI <= MCU_MOSI when aux2_sync = '1' else '0'; + LO1_LE <= MCU_NSS when aux2_sync = '1' else '0'; + -- select MISO source + MCU_MISO <= SOURCE_MUX when aux1_sync = '1' else + LO1_MUX when aux2_sync = '1' else + fpga_miso when MCU_NSS = '0' else + 'Z'; + + source_unlocked <= not source_ld_sync; + + VCOMap : VCO_Mem + PORT MAP ( + clka => clk_pll, + wea(0) => vco_write, + addra => vco_write_index, + dina => vco_write_data, + clkb => clk_pll, + addrb => vco_read_index, + doutb => vco_read_data + ); + + SPI: SPICommands PORT MAP( + CLK => clk_pll, + RESET => int_reset, + SCLK => MCU_SCK, + MOSI => MCU_MOSI, + MISO => fpga_miso, + NSS => fpga_select, + SOURCE_FILTER => source_filter, + SOURCE_POWER => source_power, + SOURCE_ATTENUATION => attenuator, + SOURCE_BANDSELECT => band_select, + SOURCE_PORTSELECT => port_select, + SOURCE_UNLOCKED => source_unlocked, + SOURCE_VCO_INDEX => vco_write_index, + SOURCE_VCO_MAXFREQ => vco_write_data, + SOURCE_VCO_WRITE => vco_write, + MOD_FIFO_DATA => mod_sample_data, + MOD_FIFO_WRITE => mod_sample_latch, + MOD_FIFO_UNDERFLOW => mod_fifo_underflow, + MOD_FIFO_OVERFLOW => mod_fifo_overflow, + MOD_FIFO_THRESHOLD_CROSSED => mod_fifo_threshold_crossed, + MOD_FIFO_THRESHOLD => mod_threshold_level, + MOD_ENABLE => mod_enable, + MOD_PHASE_INC => mod_sample_word, + MOD_CENTER_FREQ => mod_center, + MOD_DEVIATION_FREQ => mod_deviation, + MOD_AM_DEPTH => mod_depth, + MOD_VCO_MIN => mod_vco_min, + AMP_SHDN => amp_shutdown, + SOURCE_RF_EN => SOURCE_RF_EN, + SOURCE_CE_EN => SOURCE_CE, + PORTSWITCH_EN => portswitch_en, + LEDS => user_leds, + INTERRUPT_ASSERTED => intr + ); + + mod_reset <= not mod_enable; + + Modulation: Modulator PORT MAP( + CLK => clk_pll, + RESET => mod_reset, + SAMPLE_FREQ_WORD => mod_sample_word, + SAMPLE_DATA => mod_sample_data, + SAMPLE_LATCH => mod_sample_latch, + OVERFLOW => mod_fifo_overflow, + UNDERFLOW => mod_fifo_underflow, + THRESHOLD_LEVEL => mod_threshold_level, + THRESHOLD_CROSSED => mod_fifo_threshold_crossed, + FREQ_CENTER => mod_center, + FREQ_DEVIATION => mod_deviation, + MIN_ATTENUATION => attenuator, + AMPLITUDE_DEPTH => mod_depth, + FREQUENCY => mod_frequency, + ATTENUATOR => mod_attenuator, + NEW_OUTPUT => mod_new_output + ); + + PLL_Calc: MAX2871_Calc PORT MAP( + CLK => clk_pll, + RESET => int_reset, + CALC => mod_new_output, + FREQ => mod_frequency, + VCO_MIN => mod_vco_min, + DONE => pll_calc_done, + REG0 => source_reg_0, + REG1 => source_reg_1, + REG3 => source_reg_3, + REG4 => source_reg_4, + POWER => source_power, + VCO_SELECT => vco_read_index, + VCO_MAX_FREQ => vco_read_data + ); + +end Behavioral; +