jankae/LibreVNA
1
0
Fork 0
mirror of https://github.com/jankae/LibreVNA.git synced 2026-04-05 22:45:23 +00:00
Code Issues Projects Releases Packages Wiki Activity

Fix generator output spikes

Browse source 
- Add manual overwrite in FPGA for hardware that is usually handled by sweep control
- Use static hardware configuration for generator (no sweep active anymore)
This commit is contained in:
Jan Käberich 2022-06-23 17:51:15 +02:00
parent 36f826f7a6
commit 43b588c2f6
12 changed files with 169 additions and 72 deletions
Download patch file Download diff file Expand all files Collapse all files

28
Software/VNA_embedded/Application/Hardware.cpp
View file

@ -8,6 +8,7 @@
#include "Manual.hpp"
#include "delay.hpp"
#include "SpectrumAnalyzer.hpp"
#include "Communication.h"
#include <cstring>
#define LOG_LEVEL LOG_LEVEL_INFO
@ -139,6 +140,8 @@ bool HW::Init() {
return false;
}
FPGA::DisableHardwareOverwrite();
// Set default ADC samplerate
FPGA::WriteRegister(FPGA::Reg::ADCPrescaler, ADCprescaler);
// Set phase increment according to
@ -229,6 +232,7 @@ void HW::SetIdle() {
unlevel = false;
FPGA::AbortSweep();
FPGA::SetMode(FPGA::Mode::FPGA);
FPGA::DisableHardwareOverwrite();
FPGA::Enable(FPGA::Periphery::SourceChip, false);
FPGA::Enable(FPGA::Periphery::SourceRF, false);
FPGA::Enable(FPGA::Periphery::LO1Chip, false);
@ -289,7 +293,7 @@ HW::AmplitudeSettings HW::GetAmplitudeSettings(int16_t cdbm, uint64_t freq, bool
bool HW::TimedOut() {
constexpr uint64_t timeout = 1000000;
if(activeMode != Mode::Idle && Delay::get_us() - lastISR > timeout) {
if(activeMode != Mode::Idle && activeMode != Mode::Generator && Delay::get_us() - lastISR > timeout) {
return true;
} else {
return false;
@ -420,6 +424,28 @@ uint64_t HW::getLastISRTimestamp() {
return lastISR;
}
void HW::updateDeviceStatus() {
if(activeMode == Mode::Idle || activeMode == Mode::Generator) {
static uint32_t last_update = 0;
if(HAL_GetTick() - last_update >= 1000) {
last_update = HAL_GetTick();
HW::Ref::update();
Protocol::PacketInfo packet;
packet.type = Protocol::PacketType::DeviceStatusV1;
// Enable PLL chips for temperature reading
bool srcEn = FPGA::IsEnabled(FPGA::Periphery::SourceChip);
bool LOEn = FPGA::IsEnabled(FPGA::Periphery::LO1Chip);
FPGA::Enable(FPGA::Periphery::SourceChip);
FPGA::Enable(FPGA::Periphery::LO1Chip);
HW::getDeviceStatus(&packet.statusV1, true);
// restore PLL state
FPGA::Enable(FPGA::Periphery::SourceChip, srcEn);
FPGA::Enable(FPGA::Periphery::LO1Chip, LOEn);
Communication::Send(packet);
}
}
}
uint16_t HW::getDFTPhaseInc() {
return DFTphaseInc;
}