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Description of generator FPGA protocol
This commit is contained in:
Jan Käberich
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Documentation/DeveloperInfo/FPGA_protocol_Generator.pdf
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Documentation/DeveloperInfo/FPGA_protocol_Generator.pdf
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Documentation/DeveloperInfo/FPGA_protocol_Generator.tex
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Documentation/DeveloperInfo/FPGA_protocol_Generator.tex
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\documentclass{article}
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\usepackage
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[
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a4paper,% other options: a3paper, a5paper, etc
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left=2cm,
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right=2cm,
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top=2cm,
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bottom=2cm,
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% use vmargin=2cm to make vertical margins equal to 2cm.
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% us hmargin=3cm to make horizontal margins equal to 3cm.
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% use margin=3cm to make all margins equal to 3cm.
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]
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{geometry}
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\usepackage{tikz}
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\usepackage{siunitx}
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\DeclareSIUnit{\belmilliwatt}{Bm}
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\DeclareSIUnit{\dBm}{\deci\belmilliwatt}
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\pgfdeclarelayer{background}
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\pgfdeclarelayer{foreground}
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\pgfsetlayers{background,main,foreground}
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\newcommand{\bitrect}[2]{
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\begin{pgfonlayer}{foreground}
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\draw [thick] (0,0) rectangle (#1,1);
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\pgfmathsetmacro\result{#1-1}
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\foreach \x in {1,...,\result}
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\draw [thick] (\x,1) -- (\x, 0.8);
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\end{pgfonlayer}
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% \node [below left, align=right] at (0,0) {Type \\ Reset};
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\bitlabels{#1}{#2}
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}
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\newcommand{\rwbits}[3]{
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\draw [thick] (#1,0) rectangle ++(#2,1) node[pos=0.5]{#3};
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\pgfmathsetmacro\start{#1+0.5}
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\pgfmathsetmacro\finish{#1+#2-0.5}
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% \foreach \x in {\start,...,\finish}
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% \node [below, align=center] at (\x, 0) {R/W \\ 0};
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}
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\newcommand{\robits}[3]{
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\begin{pgfonlayer}{background}
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\draw [thick, fill=lightgray] (#1,0) rectangle ++(#2,1) node[pos=0.5]{#3};
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\end{pgfonlayer}
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\pgfmathsetmacro\start{#1+0.5}
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\pgfmathsetmacro\finish{#1+#2-0.5}
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% \foreach \x in {\start,...,\finish}
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% \node [below, align=center] at (\x, 0) {RO \\ 0};
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}
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\newcommand{\bitlabels}[2]{
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\foreach \bit in {1,...,#1}{
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\pgfmathsetmacro\result{#2}
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\node [above] at (\bit-0.5, 1) {\pgfmathprintnumber{\result}};
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}
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}
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\begin{document}
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\section{Digital Interface}
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\begin{center}
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\begin{tabular}{ c|c|c }
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Pin & Direction & Function\\
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\hline
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SCK & in & SCK for SPI communication/SCK for PLL communication\\
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MOSI & in & MOSI for SPI communication/MOSI for PLL communication\\
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MISO & out & MISO for SPI communication/MUX for PLL communication\\
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NSS & in & Chip Select for SPI communication/LE for PLL communication\\
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INTR & out & Active high interrupt indicator\\
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RESET & in & FPGA reset\\
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AUX1 & in & Selector for direct communication with Source PLL\\
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AUX2 & in & Selector for direct communication with LO PLL\\
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AUX3 & in & Active low modulation enable. Should be high when changing settings\\
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\end{tabular}
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\end{center}
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Depending on the voltage on AUX1/AUX2 the SPI port controls either the FPGA or one of the MAX2871 PLLs:
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\begin{center}
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\begin{tabular}{ c|c|c }
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AUX1 & AUX2 & Function\\
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\hline
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low & low & SPI communication with FPGA\\
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high & low & Direct feedthrough of SCK, MOSI, MISO and NSS to Source PLL\\
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low & high & Direct feedthrough of SCK, MOSI, MISO and NSS to LO PLL\\
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high & high & Invalid\\
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\end{tabular}
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\end{center}
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When communicating with a PLL, the MUX output of the MAX2871 is forwarded to MISO and the NSS signal is forwarded to the LE pin. As the LE pin should stay low until after a valid register has been shifted in (see MAX2871 datasheet), set NSS low before switching to PLL communication mode.
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\section{SPI Protocol}
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Each SPI transfer starts with pulling NSS low and ends with NSS returning to high level. SPI communication is done in words of 16\,bits. The first word after NSS is pulled low is the command word and determines the amount and meaning of the following words.
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The word received while transmitting the command word is the interrupt status register:
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\label{reg:status}
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\begin{center}
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\begin{tikzpicture}
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\bitrect{16}{16-\bit}
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\robits{0}{11}{reserved}
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\rwbits{11}{1}{THS}
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\rwbits{12}{1}{UDF}
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\rwbits{13}{1}{OVF}
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\rwbits{14}{1}{SU}
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\robits{15}{1}{res}
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\end{tikzpicture}
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\end{center}
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\begin{itemize}
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\item \textbf{THS:} Threshold of modulation FIFO reached. See also section~\ref{mod:fifo}. Reset on its own when the FIFO level drops again.
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\item \textbf{UDF:} Modulation FIFO underflow. Last sample will be used for modulation until new data arrives. Reset as a new sample is added to the FIFO.
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\item \textbf{OVF:} Modulation FIFO overflow. Oldest sample will be overwritten. Reset by disabling the modulation.
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\item \textbf{SU:} Source unlocked
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\end{itemize}
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\subsection{Writing a register}
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Writing a register requires the transfer of two words: First the control word selecting the destination address and a second word containing the new register value:
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\begin{center}
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\begin{tikzpicture}
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\bitrect{16}{16-\bit}
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\rwbits{0}{1}{1}
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\rwbits{1}{1}{0}
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\rwbits{2}{1}{0}
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\robits{3}{8}{reserved}
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\rwbits{11}{5}{Register Address}
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\end{tikzpicture}
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\begin{tikzpicture}
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\bitrect{16}{16-\bit}
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\rwbits{0}{16}{Register Value}
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\end{tikzpicture}
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\end{center}
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\subsection{Writing the VCO lookup table}
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The MAX2871 contains 64 individual VCOs. The correct VCO has to be selected for each frequency. During modulation, the FPGA performs the VCO selection and needs to know the frequency limits for each VCO. It contains a lookup table with a 16-bit entry for each VCO. This table has to be filled before enabling the modulation, as each MAX2871 sample has slightly different VCO limits (see MAX2871 datasheet for algorithm to determine the limits).
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Updating a table entry is done by sending two SPI words:
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\begin{center}
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\begin{tikzpicture}
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\bitrect{16}{16-\bit}
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\rwbits{0}{1}{0}
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\rwbits{1}{1}{0}
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\rwbits{2}{1}{0}
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\robits{3}{7}{reserved}
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\rwbits{10}{6}{VCO index}
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\end{tikzpicture}
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\begin{tikzpicture}
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\bitrect{16}{16-\bit}
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\rwbits{0}{16}{Maximum VCO frequency[15:0]}
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\end{tikzpicture}
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\end{center}
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The maximum VCO frequency is given in terms of the MAX2871 reference frequency. It is a Q10 fixed point integer.
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$$
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Maximum VCO frequency[15:0] = \frac{f_{max} * 1024}{f_{reference}}
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$$
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Example: With a reference frequency $f_{reference} = 104 MHz$ and a maximum usable frequency of the VCO of $f_{max} = 3718 MHz$, set the maximum VCO frequency value to 36608.
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\subsection{Modulation FIFO handling}
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\label{mod:fifo}
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The modulation module contains a data FIFO for the modulation data (samples). Each sample is an 8-bit word that determines the modulation state. The modulation moves on to the next sample at a rate determined by MOD\_PHASE\_INC. The FIFO has a size of 2048 samples. It can only be written to, reading back data from the FIFO is not possible.
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The FIFO also has three interrupts (see status register, section~ref{reg:status}):
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\begin{itemize}
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\item \textbf{Overflow:} Asserted when samples have been written to an already full FIFO. This bit does not clear even if the FIFO level drops afterwards. The modulation has to be disabled to reset this bit. Disabling the modulation also clears the FIFO.
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\item \textbf{Underflow:} Asserted when no more samples are available in the FIFO but the modulation module is scheduled to move to the next sample. The modulation will continue to use the last available sample until new data is written to the FIFO. This bit is cleared by writing new FIFO data.
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\item \textbf{Threshold crossed:} Asserted when the FIFO contains at least MOD\_FIFO\_THRESHOLD (see section~ref{reg:mod:fifo:thresh}) samples.
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\end{itemize}
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\subsubsection{Writing to the modulation FIFO}
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It is only possible to write to bytes at a time to the modulation FIFO. Initiate the write by sending the command word:
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\begin{center}
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\begin{tikzpicture}
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\bitrect{16}{16-\bit}
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\rwbits{0}{1}{0}
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\rwbits{1}{1}{0}
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\rwbits{2}{1}{1}
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\robits{3}{13}{reserved}
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\end{tikzpicture}
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\end{center}
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Follow up the same SPI transaction (NSS has to stay low) with as many words as desired, each word containing two FIFO samples:
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\begin{center}
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\begin{tikzpicture}
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\bitrect{16}{16-\bit}
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\rwbits{0}{8}{FIFO sample 1}
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\rwbits{8}{8}{FIFO sample 2}
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\end{tikzpicture}
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\end{center}
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FIFO sample 1 is added to the FIFO first, followed by FIFO sample 2.
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\section{Registers}
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\subsection{Interrupt Mask Register: 0x00}
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\begin{center}
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\begin{tikzpicture}
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\bitrect{16}{16-\bit}
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\robits{0}{11}{reserved}
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\rwbits{11}{1}{THSIE}
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\rwbits{12}{1}{UDFIE}
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\rwbits{13}{1}{OVFIE}
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\rwbits{14}{1}{SUIE}
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\robits{15}{1}{res}
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\end{tikzpicture}
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\end{center}
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\begin{itemize}
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\item \textbf{THSIE:} FIFO threshold crossed interrupt enable
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\item \textbf{UDFIE:} FIFO underflow interrupt enable
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\item \textbf{OVFIE:} FIFO overflow interrupt enable
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\item \textbf{SUIE:} Source unlocked interrupt enable
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\end{itemize}
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\subsection{Source Control Register: 0x01}
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\begin{center}
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\begin{tikzpicture}
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\bitrect{16}{16-\bit}
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\rwbits{0}{2}{SourceFilter}
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\rwbits{2}{2}{PWR}
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\rwbits{4}{7}{Attenuation}
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\rwbits{11}{1}{BS}
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\rwbits{12}{1}{PS}
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\rwbits{13}{1}{CE}
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\rwbits{14}{1}{RFEN}
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\rwbits{15}{1}{ASHD}
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\end{tikzpicture}
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\end{center}
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\begin{itemize}
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\item \textbf{SourceFilter:} Low pass filter selection for source signal
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\begin{center}
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\begin{tabular}{ c|c }
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Setting & Selected Band\\
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\hline
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00 & \SIrange{0}{900}{\mega\hertz}\\
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01 & \SIrange{900}{1800}{\mega\hertz}\\
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10 & \SIrange{1800}{3500}{\mega\hertz}\\
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11 & \SIrange{3500}{6000}{\mega\hertz}\\
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\end{tabular}
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\end{center}
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\item \textbf{PWR:} Power setting of source PLL. Will be written to register 4, bits [4:3] of the source PLL, controlling the output power of output A.
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\begin{center}
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\begin{tabular}{ c|c }
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Setting & Selected Power\\
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\hline
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00 & \SI{-4}{\dBm}\\
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01 & \SI{-1}{\dBm}\\
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10 & \SI{2}{\dBm}\\
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11 & \SI{5}{\dBm}\\
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\end{tabular}
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\end{center}
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\item \textbf{Attenuator:} Attenuation of source signal in \SI{0.25}{\decibel}.
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\item \textbf{BS: Band select.} Set to 0 for highband, set to 1 for lowband.
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\item \textbf{PS: Port select.} Set to 0 for Port 1, set to 1 for Port 2.
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\item \textbf{CE: Source chip enable.}
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\item \textbf{RFEN: Source RF enable.}
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\item \textbf{ASHD: Amplifier disable.}
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\end{itemize}
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\subsection{Modulation control register: 0x02}
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\begin{center}
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\begin{tikzpicture}
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\bitrect{16}{16-\bit}
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\rwbits{0}{3}{LEDS[2:0]}
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\robits{3}{5}{reserved}
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\rwbits{8}{7}{MOD\_AM\_DEPTH[6:0]}
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\rwbits{15}{1}{EN}
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\end{tikzpicture}
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\end{center}
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\begin{itemize}
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\item \textbf{LEDS:} User LED status:
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\begin{center}
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\begin{tabular}{ c|c }
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LED num & Function\\
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\hline
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0 & Debug\\
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1 & Ready\\
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2 & Ext. reference\\
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\end{tabular}
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\end{center}
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\item \textbf{MOD\_AM\_DEPTH:} Depth of amplitude modulation. Higher values of the modulation sample result in deeper modulation. This setting determines the maximum depth. 127 is equivalent to 100\% modulation.
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\item \textbf{EN: Enable modulation.} Set to 1 to enable the modulation. For the modulation to actually start, AUX3 also has to be pulled low. Set to 0 to disable the modulation (when changing settings or to clear the modulation FIFO).
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\end{itemize}
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\subsection{Modulation phase increment register: 0x03}
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\begin{center}
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\begin{tikzpicture}
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\bitrect{16}{16-\bit}
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\rwbits{0}{16}{MOD\_PHASE\_INC[15:0]}
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\end{tikzpicture}
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\end{center}
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Determines the rate at which the modulation module consumes samples:
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$$
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f_{sample} = \frac{104 MHz * MOD\_PHASE\_INC}{2^{27}}
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$$
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Example: set to 25811 for a sample rate of approximately 20 kHz.
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\subsection{Modulation center frequency LSB register: 0x04}
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\label{reg:mod:center:lsb}
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\begin{center}
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\begin{tikzpicture}
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\bitrect{16}{16-\bit}
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\rwbits{0}{16}{MOD\_CENTER\_FREQ[15:0]}
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\end{tikzpicture}
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\end{center}
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\begin{itemize}
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\item \textbf{MOD\_CENTER\_FREQ[32:0]:} See also other registers for remaining bits (sections~\ref{reg:mod:center:msb} and \ref{reg:mod:dev:msb}). Sets the center frequency of the frequency modulation. It is given in terms of the MAX2871 reference frequency. It is a Q27 fixed point integer.
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$$
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MOD\_CENTER\_FREQ[32:0] = \frac{f_{center} * 2^{27}}{f_{reference}}
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$$
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\end{itemize}
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\subsection{Modulation center frequency MSB register: 0x05}
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\label{reg:mod:center:msb}
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\begin{center}
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\begin{tikzpicture}
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\bitrect{16}{16-\bit}
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\rwbits{0}{16}{MOD\_CENTER\_FREQ[31:16]}
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\end{tikzpicture}
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\end{center}
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\subsection{Modulation deviation frequency LSB register: 0x06}
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\label{reg:mod:dev:lsb}
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\begin{center}
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\begin{tikzpicture}
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\bitrect{16}{16-\bit}
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\rwbits{0}{16}{MOD\_DEVIATION\_FREQ[15:0]}
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\end{tikzpicture}
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\end{center}
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\begin{itemize}
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\item \textbf{MOD\_DEVIATION\_FREQ[25:0]:} See also other register for remaining bits (section~\ref{reg:mod:dev:msb}). Sets the maximum deviation from the center frequency during frequency modulation. It is given in terms of the MAX2871 reference frequency. It is a Q27 fixed point integer. As it only has 26 bits, the maximum deviation is half the reference frequency.
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$$
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MOD\_DEVIATION\_FREQ[25:0] = \frac{f_{max_deviation} * 2^{27}}{f_{reference}}
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$$
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\end{itemize}
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\subsection{Modulation deviation frequency MSB register: 0x07}
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\label{reg:mod:dev:msb}
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\begin{center}
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\begin{tikzpicture}
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\bitrect{16}{16-\bit}
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\rwbits{0}{1}{CF32}
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\robits{1}{5}{reserved}
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\rwbits{6}{10}{MOD\_DEVIATION\_FREQ[25:16]}
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\end{tikzpicture}
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\end{center}
|
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\begin{itemize}
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\item \textbf{CF32:} Most significant bit of MOD\_CENTER\_FREQ.
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\end{itemize}
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\subsection{Minimum VCO frequency LSB register: 0x08}
|
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\label{reg:mod:minvco:lsb}
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\begin{center}
|
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\begin{tikzpicture}
|
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\bitrect{16}{16-\bit}
|
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\rwbits{0}{16}{MOD\_VCO\_MIN[15:0]}
|
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\end{tikzpicture}
|
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\end{center}
|
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\begin{itemize}
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\item \textbf{MOD\_VCO\_MIN[31:0]:} See also other register for remaining bits (section~\ref{reg:mod:minvco:msb}). Sets the minimal allowed undivided VCO frequency. Used to determine the VCO divider when changing frequencies. It is given in terms of the MAX2871 reference frequency. It is a Q27 fixed point integer. Always set this for a minimal undivided VCO frequency of 3 GHz.
|
||||
$$
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||||
MOD\_VCO\_MIN[31:0] = \frac{f_{min_vco} * 2^{27}}{f_{reference}}
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$$
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\end{itemize}
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For the default reference frequency of 104 MHz, set this value to 3871665231.
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\subsection{Minimum VCO frequency MSB register: 0x05}
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\label{reg:mod:minvco:msb}
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\begin{center}
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\begin{tikzpicture}
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\bitrect{16}{16-\bit}
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\rwbits{0}{16}{MOD\_VCO\_MIN[31:16]}
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\end{tikzpicture}
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\end{center}
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\subsection{Modulation FIFO threshold register: 0x0A}
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\label{reg:mod:fifo:thresh}
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\begin{center}
|
||||
\begin{tikzpicture}
|
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\bitrect{16}{16-\bit}
|
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\rwbits{0}{16}{MOD\_FIFO\_THRESHOLD[15:0]}
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\end{tikzpicture}
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||||
\end{center}
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\begin{itemize}
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\item \textbf{MOD\_FIFO\_THRESHOLD[15:0]:} Number of samples in the FIFO after which the FIFO threshold interrupt is asserted.
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\end{itemize}
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|
||||
\end{document}
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Binary file not shown.
|
|
@ -238,7 +238,7 @@
|
|||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1654646738" xil_pn:in_ck="-3416851794138383481" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="3256065936432453276" xil_pn:start_ts="1654646732">
|
||||
<transform xil_pn:end_ts="1654687639" xil_pn:in_ck="-3416851794138383481" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="3256065936432453276" xil_pn:start_ts="1654687633">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="WarningsGenerated"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
|
|
@ -260,7 +260,7 @@
|
|||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1654646741" xil_pn:in_ck="7073755081550385991" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="4604875190571501774" xil_pn:start_ts="1654646738">
|
||||
<transform xil_pn:end_ts="1654687642" xil_pn:in_ck="7073755081550385991" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="4604875190571501774" xil_pn:start_ts="1654687639">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<outfile xil_pn:name="_ngo"/>
|
||||
|
|
@ -269,7 +269,7 @@
|
|||
<outfile xil_pn:name="top.ngd"/>
|
||||
<outfile xil_pn:name="top_ngdbuild.xrpt"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1654646747" xil_pn:in_ck="8512332261572065657" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-4668962392366239264" xil_pn:start_ts="1654646741">
|
||||
<transform xil_pn:end_ts="1654687649" xil_pn:in_ck="8512332261572065657" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-4668962392366239264" xil_pn:start_ts="1654687642">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="WarningsGenerated"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
|
|
@ -283,7 +283,7 @@
|
|||
<outfile xil_pn:name="top_summary.xml"/>
|
||||
<outfile xil_pn:name="top_usage.xml"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1654646754" xil_pn:in_ck="1117507038335044978" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-1085068593928086116" xil_pn:start_ts="1654646747">
|
||||
<transform xil_pn:end_ts="1654687656" xil_pn:in_ck="1117507038335044978" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-1085068593928086116" xil_pn:start_ts="1654687649">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="WarningsGenerated"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
|
|
@ -298,7 +298,7 @@
|
|||
<outfile xil_pn:name="top_pad.txt"/>
|
||||
<outfile xil_pn:name="top_par.xrpt"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1654646759" xil_pn:in_ck="154288912438" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="3274353840855015246" xil_pn:start_ts="1654646754">
|
||||
<transform xil_pn:end_ts="1654687661" xil_pn:in_ck="154288912438" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="3274353840855015246" xil_pn:start_ts="1654687656">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="WarningsGenerated"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
|
|
@ -352,7 +352,7 @@
|
|||
<status xil_pn:value="InputChanged"/>
|
||||
<status xil_pn:value="InputRemoved"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1654646754" xil_pn:in_ck="8512326635937592693" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1654646751">
|
||||
<transform xil_pn:end_ts="1654687656" xil_pn:in_ck="8512326635937592693" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1654687654">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
|
||||
|
|
|
|||
|
|
@ -153,7 +153,7 @@ begin
|
|||
DONE <= '0';
|
||||
if unsigned(freq_buf) < unsigned(vco_min_buf) then
|
||||
vco_div <= vco_div + 1;
|
||||
freq_buf <= freq_buf(32 downto 1) & "0";
|
||||
freq_buf <= freq_buf(31 downto 0) & "0";
|
||||
else
|
||||
state <= VCO;
|
||||
end if;
|
||||
|
|
@ -161,7 +161,7 @@ begin
|
|||
when VCO =>
|
||||
approx_start <= '1';
|
||||
DONE <= '0';
|
||||
if unsigned(VCO_MAX_FREQ) < unsigned(freq_buf(15 downto 0)) then
|
||||
if unsigned(VCO_MAX_FREQ) < unsigned(freq_buf(32 downto 17)) then
|
||||
-- select next VCO
|
||||
vco_cnt <= vco_cnt + 1;
|
||||
else
|
||||
|
|
|
|||
|
|
@ -34,6 +34,7 @@ use IEEE.NUMERIC_STD.ALL;
|
|||
entity Modulator is
|
||||
Port ( CLK : in STD_LOGIC;
|
||||
RESET : in STD_LOGIC;
|
||||
ACTIVE : in STD_LOGIC;
|
||||
-- Determines sample rate
|
||||
SAMPLE_FREQ_WORD : in STD_LOGIC_VECTOR (15 downto 0);
|
||||
-- Input data, latched when SAMPLE_LATCH goes high
|
||||
|
|
@ -114,7 +115,7 @@ architecture Behavioral of Modulator is
|
|||
|
||||
signal sample : std_logic_vector(7 downto 0);
|
||||
|
||||
signal clk_sample_cnt : unsigned(27 downto 0);
|
||||
signal clk_sample_cnt : unsigned(26 downto 0);
|
||||
|
||||
type AMdepthTable is array(0 to 127) of std_logic_vector(6 downto 0);
|
||||
|
||||
|
|
@ -194,7 +195,9 @@ begin
|
|||
end if;
|
||||
write_pos <= write_pos + 1;
|
||||
end if;
|
||||
if ACTIVE = '1' then
|
||||
clk_sample_cnt <= clk_sample_cnt + unsigned(SAMPLE_FREQ_WORD);
|
||||
end if;
|
||||
if clk_sample_cnt(26) = '1' then
|
||||
-- take the next sample
|
||||
clk_sample_cnt(26) <= '0';
|
||||
|
|
|
|||
|
|
@ -173,6 +173,7 @@ begin
|
|||
spi_buf_in <= "1111000010100101";
|
||||
when "100" => state <= WriteRegister;
|
||||
selected_register <= to_integer(unsigned(spi_buf_out(4 downto 0)));
|
||||
when "001" => state <= WriteModulationData;
|
||||
when others => state <= FirstWord;
|
||||
end case;
|
||||
when WriteRegister =>
|
||||
|
|
|
|||
Binary file not shown.
|
|
@ -185,6 +185,7 @@ architecture Behavioral of top is
|
|||
PORT(
|
||||
CLK : IN std_logic;
|
||||
RESET : IN std_logic;
|
||||
ACTIVE : in STD_LOGIC;
|
||||
SAMPLE_FREQ_WORD : IN std_logic_vector(15 downto 0);
|
||||
SAMPLE_DATA : IN std_logic_vector(7 downto 0);
|
||||
SAMPLE_LATCH : IN std_logic;
|
||||
|
|
@ -273,6 +274,7 @@ architecture Behavioral of top is
|
|||
-- modulation signals
|
||||
signal mod_enable : std_logic;
|
||||
signal mod_reset : std_logic;
|
||||
signal mod_active : std_logic;
|
||||
signal mod_sample_word : std_logic_vector(15 downto 0);
|
||||
signal mod_sample_data : std_logic_vector(7 downto 0);
|
||||
signal mod_sample_latch : std_logic;
|
||||
|
|
@ -368,13 +370,13 @@ begin
|
|||
SYNC_IN => MCU_AUX2,
|
||||
SYNC_OUT => aux2_sync
|
||||
);
|
||||
-- Sync_AUX3 : Synchronizer
|
||||
-- GENERIC MAP(stages => 2)
|
||||
-- PORT MAP(
|
||||
-- CLK => clk_pll,
|
||||
-- SYNC_IN => MCU_AUX3,
|
||||
-- SYNC_OUT => aux3_sync
|
||||
-- );
|
||||
Sync_AUX3 : Synchronizer
|
||||
GENERIC MAP(stages => 2)
|
||||
PORT MAP(
|
||||
CLK => clk_pll,
|
||||
SYNC_IN => MCU_AUX3,
|
||||
SYNC_OUT => aux3_sync
|
||||
);
|
||||
-- Sync_LO_LD : Synchronizer
|
||||
-- GENERIC MAP(stages => 2)
|
||||
-- PORT MAP(
|
||||
|
|
@ -486,10 +488,12 @@ begin
|
|||
);
|
||||
|
||||
mod_reset <= not mod_enable;
|
||||
mod_active <= not aux3_sync;
|
||||
|
||||
Modulation: Modulator PORT MAP(
|
||||
CLK => clk_pll,
|
||||
RESET => mod_reset,
|
||||
ACTIVE => mod_active,
|
||||
SAMPLE_FREQ_WORD => mod_sample_word,
|
||||
SAMPLE_DATA => mod_sample_data,
|
||||
SAMPLE_LATCH => mod_sample_latch,
|
||||
|
|
|
|||
Loading…
Reference in a new issue