mirror of
https://github.com/jankae/LibreVNA.git
synced 2026-04-06 06:53:37 +00:00
embedded code copied from jankae/VNA and adjusted for STM32G4
This commit is contained in:
Jan Käberich
parent
7af204b349
commit
30d4ebe37b
215 changed files with 186208 additions and 0 deletions
408
Software/VNA_embedded/Application/Drivers/max2871.cpp
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408
Software/VNA_embedded/Application/Drivers/max2871.cpp
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#include "max2871.hpp"
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#include <string.h>
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#include <algorithm.hpp>
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#include "delay.hpp"
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#include <cmath>
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#define LOG_LEVEL LOG_LEVEL_WARN
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#define LOG_MODULE "MAX2871"
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#include "Log.h"
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bool MAX2871::Init() {
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return Init(10000000, true, 1, false);
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}
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bool MAX2871::Init(uint32_t f_ref, bool doubler, uint16_t r, bool div2) {
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for (uint8_t i = 0; i < 6; i++) {
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regs[i] = 0;
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}
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ChipEnable(false);
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RFEnable(false);
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SetReference(f_ref, doubler, r, div2);
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// non-inverting loop filter
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regs[2] |= (1UL << 6);
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// select digital lock detect
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regs[5] |= (0x1UL << 22);
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// fundamental VCO feedback
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regs[4] |= (1UL << 23);
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// reserved, set to 0x03
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regs[4] |= (0x3UL << 29);
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// enable double buffering for register 4
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regs[2] |= (1UL << 13);
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// automatically switch to integer mode if F = 0
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regs[5] |= (1UL << 24);
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SetMode(Mode::LowSpur2);
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// for all other CP modes the PLL reports unlock condition (output signal appears to be locked)
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SetCPMode(CPMode::CP20);
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SetCPCurrent(15);
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SetFrequency(1000000000);
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// initial register write according to datasheet timing
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ChipEnable(true);
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Write(5, regs[5]);
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Delay::ms(20);
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Write(4, regs[4]);
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Write(3, regs[3]);
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Write(2, regs[2]);
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Write(1, regs[1]);
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Write(0, regs[0]);
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Write(5, regs[5]);
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Delay::ms(20);
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Write(4, regs[4]);
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Write(3, regs[3]);
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Write(2, regs[2]);
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Write(1, regs[1]);
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Write(0, regs[0]);
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return true;
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}
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void MAX2871::ChipEnable(bool on) {
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if(!CE) {
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return;
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}
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if (on) {
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CE->BSRR = CEpin;
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} else {
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CE->BSRR = CEpin << 16;
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}
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}
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void MAX2871::RFEnable(bool on) {
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if(!RF_EN) {
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return;
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}
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if (on) {
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RF_EN->BSRR = RF_ENpin;
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Read();
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} else {
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RF_EN->BSRR = RF_ENpin << 16;
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}
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}
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bool MAX2871::Locked() {
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return LD->IDR & LDpin;
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}
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void MAX2871::SetPowerOutA(Power p, bool enabled) {
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// only set power of port A
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regs[4] &= ~0x38;
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regs[4] |= ((uint16_t) p << 3);
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if (enabled) {
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regs[4] |= 0x20;
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}
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}
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void MAX2871::SetPowerOutB(Power p, bool enabled) {
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// only set power of port B
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regs[4] &= ~0x1C0;
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regs[4] |= ((uint16_t) p << 6);
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if (enabled) {
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regs[4] |= 0x100;
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}
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}
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void MAX2871::SetMode(Mode m) {
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regs[2] &= ~0x60000000;
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regs[2] |= ((uint32_t) m << 29);
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}
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void MAX2871::SetCPMode(CPMode m) {
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regs[1] &= ~0x60000000;
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regs[1] |= ((uint32_t) m << 29);
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}
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void MAX2871::SetCPCurrent(uint8_t mA) {
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if(mA > 15) {
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LOG_WARN("Clipping charge pump current to 15mA");
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mA = 15;
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}
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regs[2] &= ~0x1E00;
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regs[2] |= ((uint16_t) mA << 9);
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}
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bool MAX2871::SetFrequency(uint64_t f) {
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if (f < 23500000 || f > MaxFreq) {
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LOG_ERR("Frequency must be between 23.5MHz and 6GHz");
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return false;
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}
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LOG_DEBUG("Setting frequency to %lu%06luHz...", (uint32_t ) (f / 1000000),
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(uint32_t ) (f % 1000000));
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// select divider
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uint64_t f_vco = f;
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uint8_t div = 0;
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if (f < 46875000) {
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div = 0x07;
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f_vco *= 128;
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} else if (f < 93750000) {
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div = 0x06;
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f_vco *= 64;
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} else if (f < 187500000) {
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div = 0x05;
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f_vco *= 32;
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} else if (f < 375000000) {
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div = 0x04;
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f_vco *= 16;
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} else if (f < 750000000) {
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div = 0x03;
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f_vco *= 8;
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} else if (f < 1500000000) {
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div = 0x02;
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f_vco *= 4;
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} else if (f < 3000000000) {
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div = 0x01;
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f_vco *= 2;
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}
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LOG_DEBUG("F_VCO: %lu%06luHz",
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(uint32_t ) (f_vco / 1000000), (uint32_t ) (f_vco % 1000000));
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if (gotVCOMap) {
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// manual VCO selection for lock time improvement
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uint16_t compare = f_vco / 100000;
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uint8_t vco = 0;
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for (; vco < 64; vco++) {
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if (VCOmax[vco] >= compare) {
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break;
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}
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} LOG_DEBUG("Manually selected VCO %d", vco);
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regs[3] &= ~0xFC000000;
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regs[3] |= (uint32_t) vco << 26;
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}
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uint16_t N = f_vco / f_PFD;
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if (N < 19 || N > 4091) {
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LOG_ERR("Invalid N value, should be between 19 and 4091, got %lu", N);
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return false;
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}
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uint32_t rem_f = f_vco - N * f_PFD;
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LOG_DEBUG("Remaining fractional frequency: %lu", rem_f);
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LOG_DEBUG("Looking for best fractional match");
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float fraction = (float) rem_f / f_PFD;
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auto approx = Algorithm::BestRationalApproximation(fraction, 4095);
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int32_t rem_approx = ((uint64_t) f_PFD * approx.num) / approx.denom;
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if(rem_approx != rem_f) {
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LOG_WARN("Best match is F=%u/M=%u, deviation of %luHz",
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approx.num, approx.denom, abs(rem_f - rem_approx));
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}
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uint64_t f_set = (uint64_t) N * f_PFD + (f_PFD * approx.num) / approx.denom;
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f_set /= (1UL << div);
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// write values to registers
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regs[4] &= ~0x00700000;
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regs[4] |= ((uint32_t) div << 20);
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regs[0] &= ~0x7FFFFFF8;
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regs[0] |= ((uint32_t) N << 15) | ((uint32_t) approx.num << 3);
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regs[1] &= ~0x00007FF8;
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regs[1] |= ((uint32_t) approx.denom << 3);
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LOG_DEBUG("Set frequency to %lu%06luHz...",
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(uint32_t ) (f_set / 1000000), (uint32_t ) (f_set % 1000000));
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outputFrequency = f_set;
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return true;
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}
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bool MAX2871::SetReference(uint32_t f_ref, bool doubler, uint16_t r,
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bool div2) {
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if (f_ref < 10000000) {
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LOG_ERR("Reference frequency must be >=10MHz, is %lu", f_ref);
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return false;
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} else if (f_ref > 105000000 && doubler) {
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LOG_ERR(
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"Reference frequency must be <=105MHz when used with doubler, is %lu",
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f_ref);
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return false;
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} else if (f_ref > 210000000) {
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LOG_ERR("Reference frequency must be <=210MHz, is %lu", f_ref);
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return false;
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}
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if (r < 1 || r > 1023) {
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LOG_ERR("Reference divider must be between 1 and 1023, is %d", r);
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return false;
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}
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// calculate PFD frequency
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uint32_t pfd = f_ref;
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if (doubler) {
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pfd *= 2;
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}
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pfd /= r;
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if (div2) {
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pfd /= 2;
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}
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if (pfd > 125000000) {
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LOG_ERR("PFD frequency must be <=125MHz, is %d",
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pfd);
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return false;
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}
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if(pfd > 32000000) {
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regs[2] |= (1UL << 31);
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} else {
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regs[2] &= ~(1UL << 31);
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}
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// input values are valid, adjust registers
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regs[2] &= ~0x03FFC000;
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if (doubler) {
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regs[2] |= (1UL << 25);
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}
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if (div2) {
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regs[2] |= (1UL << 24);
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}
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regs[2] |= (r << 14);
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f_PFD = pfd;
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LOG_INFO("Set PFD frequency to %lu", f_PFD);
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// updating VAS state machine clock
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uint16_t BS = f_PFD / 50000;
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if (BS > 1023) {
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BS = 1023;
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} else if (BS < 1) {
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BS = 1;
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}
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LOG_DEBUG("BS set to %lu", BS);
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regs[4] &= ~0x030FF000;
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regs[4] |= ((BS & 0xFF) << 12);
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regs[4] |= (((BS >> 8) & 0x03) << 24);
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// update ADC clock
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uint16_t cdiv = f_PFD/100000;
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LOG_DEBUG("CDIV set to %u", cdiv);
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regs[3] &= ~0x00007FF8;
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regs[3] |= (cdiv & 0xFFF) << 3;
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return true;
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}
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void MAX2871::Update() {
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Write(5, regs[5]);
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Write(4, regs[4]);
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Write(3, regs[3]);
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Write(2, regs[2]);
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Write(1, regs[1]);
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Write(0, regs[0]);
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}
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void MAX2871::UpdateFrequency() {
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Write(4, regs[4]);
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Write(3, regs[3]);
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Write(1, regs[1]);
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Write(0, regs[0]);
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}
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void MAX2871::Write(uint8_t reg, uint32_t val) {
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uint16_t data[2];
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// split value into two 16 bit words
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data[0] = val >> 16;
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data[1] = (val & 0xFFF8) | reg;
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Delay::us(1);
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HAL_SPI_Transmit(hspi, (uint8_t*) data, 2, 20);
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LE->BSRR = LEpin;
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Delay::us(1);
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LE->BSRR = LEpin << 16;
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}
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// Assumes that the MUX pin is already configured as "Read register 6" and connected to MISO
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uint32_t MAX2871::Read() {
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uint16_t transmit[2] = {0x0000, 0x0006};
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HAL_SPI_Transmit(hspi, (uint8_t*) transmit, 2, 20);
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LE->BSRR = LEpin;
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memset(transmit, 0, sizeof(transmit));
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uint16_t recv[2];
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HAL_SPI_TransmitReceive(hspi, (uint8_t*) transmit, (uint8_t*) recv, 2, 20);
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LE->BSRR = LEpin << 16;
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// assemble readback result
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uint32_t result = ((uint32_t) recv[0] << 16) | (recv[1] & 0xFFFF);
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result <<= 2;
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LOG_DEBUG("Readback: 0x%08x", result);
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return result;
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}
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bool MAX2871::BuildVCOMap() {
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memset(VCOmax, 0, sizeof(VCOmax));
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// save output frequency
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uint64_t oldFreq = outputFrequency;
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constexpr uint32_t step = 10000000;
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for (uint64_t freq = 3000000000; freq <= MaxFreq; freq += step) {
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SetFrequency(freq);
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UpdateFrequency();
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uint32_t start = HAL_GetTick();
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// set MUX to LD
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regs[2] &= ~(7UL << 26);
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regs[5] &= ~(1UL << 18);
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regs[2] |= (6UL << 26);
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Write(5, regs[5]);
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Write(2, regs[2]);
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while (!(MUX->IDR & MUXpin)) {
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if (HAL_GetTick() - start > 100) {
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LOG_ERR(
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"Failed to lock during VCO map build process, aborting (f=%lu%06luHz)",
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(uint32_t )(freq / 1000000),
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(uint32_t ) (freq % 1000000));
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gotVCOMap = false;
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// revert back to previous frequency
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SetFrequency(oldFreq);
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LE->BSRR = LEpin << 16;
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// Mux pin back to high impedance
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regs[2] &= ~(7UL << 26);
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regs[5] &= ~(1UL << 18);
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Update();
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return false;
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}
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}
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// set MUX to SPI read
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regs[2] &= ~(7UL << 26);
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regs[5] &= ~(1UL << 18);
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regs[2] |= (4UL << 26);
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regs[5] |= (1UL << 18);
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Write(5, regs[5]);
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Write(2, regs[2]);
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auto readback = Read();
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uint8_t vco = (readback & 0x01F8) >> 3;
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VCOmax[vco] = freq / 100000;
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LOG_INFO("VCO map: %lu%06luHz uses VCO %d",
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(uint32_t ) (freq / 1000000), (uint32_t ) (freq % 1000000), vco);
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}
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gotVCOMap = true;
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// revert back to previous frequency
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SetFrequency(oldFreq);
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// Mux pin back to high impedance
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regs[2] &= ~(7UL << 26);
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regs[5] &= ~(1UL << 18);
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// Turn off VAS, select VCO manually from now on
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regs[3] |= (1UL << 25);
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Update();
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return true;
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}
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uint8_t MAX2871::GetTemp() {
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// select temperature channel and start ADC
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regs[5] &= ~0x00000078;
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regs[5] |= 0x00000048;
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Write(5, regs[5]);
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Delay::us(100);
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// set MUX to SPI read
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regs[2] &= ~(7UL << 26);
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regs[5] &= ~(1UL << 18);
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regs[2] |= (4UL << 26);
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regs[5] |= (1UL << 18);
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Write(5, regs[5]);
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Write(2, regs[2]);
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uint8_t ADC_raw = (Read() >> 16) & 0x7F;
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LOG_DEBUG("Raw temp ADC: %d", ADC_raw);
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// Disable ADC
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regs[5] &= ~0x00000078;
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// Mux pin back to high impedance
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regs[2] &= ~(7UL << 26);
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regs[5] &= ~(1UL << 18);
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Write(5, regs[5]);
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Write(2, regs[2]);
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// convert to celsius and return
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return 95 - 1.14f * ADC_raw;
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}
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