mirror of
https://github.com/jankae/LibreVNA.git
synced 2026-04-05 22:45:23 +00:00
Refactoring, better code encapsulation for different operating modes
This commit is contained in:
Jan Käberich
parent
d9d00b8c71
commit
00244022c9
13 changed files with 701 additions and 519 deletions
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@ -1,3 +1,4 @@
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#include <HW_HAL.hpp>
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#include <VNA.hpp>
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#include "Si5351C.hpp"
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#include "max2871.hpp"
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@ -6,7 +7,8 @@
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#include "FPGA/FPGA.hpp"
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#include <complex>
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#include "Exti.hpp"
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#include "VNA_HAL.hpp"
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#include "Hardware.hpp"
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#include "Communication.h"
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#define LOG_LEVEL LOG_LEVEL_INFO
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#define LOG_MODULE "VNA"
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@ -17,12 +19,11 @@ static constexpr uint32_t IF1_alternate = 57000000;
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static constexpr uint32_t IF2 = 250000;
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static VNA::SweepCallback sweepCallback;
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static VNA::StatusCallback statusCallback;
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static Protocol::SweepSettings settings;
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static uint16_t pointCnt;
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static bool excitingPort1;
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static Protocol::Datapoint data;
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static bool manualMode = false;
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static bool active = false;
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using IFTableEntry = struct {
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uint16_t pointCnt;
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@ -36,208 +37,21 @@ static uint16_t IFTableIndexCnt = 0;
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static constexpr uint32_t BandSwitchFrequency = 25000000;
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static uint32_t extOutFreq = 0;
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static bool extRefInUse = false;
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using namespace HWHAL;
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using namespace VNAHAL;
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static void HaltedCallback() {
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LOG_DEBUG("Halted before point %d", pointCnt);
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// Check if IF table has entry at this point
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// if (IFTable[IFTableIndexCnt].pointCnt == pointCnt) {
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// LOG_DEBUG("Shifting IF to %lu at point %u",
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// IFTable[IFTableIndexCnt].IF1, pointCnt);
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// Si5351.WriteRawCLKConfig(1, IFTable[IFTableIndexCnt].clkconfig);
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// Si5351.WriteRawCLKConfig(4, IFTable[IFTableIndexCnt].clkconfig);
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// Si5351.WriteRawCLKConfig(5, IFTable[IFTableIndexCnt].clkconfig);
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// Si5351.ResetPLL(Si5351C::PLL::B);
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// IFTableIndexCnt++;
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// }
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uint64_t frequency = settings.f_start
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+ (settings.f_stop - settings.f_start) * pointCnt
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/ (settings.points - 1);
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if (frequency < BandSwitchFrequency) {
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// need the Si5351 as Source
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Si5351.SetCLK(SiChannel::LowbandSource, frequency, Si5351C::PLL::B,
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Si5351C::DriveStrength::mA2);
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if (pointCnt == 0) {
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// First point in sweep, enable CLK
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Si5351.Enable(SiChannel::LowbandSource);
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FPGA::Disable(FPGA::Periphery::SourceRF);
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}
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} else {
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// first sweep point in highband is also halted, disable lowband source
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Si5351.Disable(SiChannel::LowbandSource);
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FPGA::Enable(FPGA::Periphery::SourceRF);
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}
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FPGA::ResumeHaltedSweep();
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}
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static void ReadComplete(FPGA::SamplingResult result) {
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if(!manualMode) {
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// normal sweep mode
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auto port1_raw = std::complex<float>(result.P1I, result.P1Q);
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auto port2_raw = std::complex<float>(result.P2I, result.P2Q);
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auto ref = std::complex<float>(result.RefI, result.RefQ);
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auto port1 = port1_raw / ref;
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auto port2 = port2_raw / ref;
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data.pointNum = pointCnt;
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data.frequency = settings.f_start + (settings.f_stop - settings.f_start) * pointCnt / (settings.points - 1);
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if(excitingPort1) {
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data.real_S11 = port1.real();
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data.imag_S11 = port1.imag();
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data.real_S21 = port2.real();
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data.imag_S21 = port2.imag();
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} else {
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data.real_S12 = port1.real();
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data.imag_S12 = port1.imag();
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data.real_S22 = port2.real();
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data.imag_S22 = port2.imag();
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}
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// figure out whether this sweep point is complete and which port gets excited next
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bool pointComplete = false;
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if(settings.excitePort1 == 1 && settings.excitePort2 == 1) {
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// point is complete when port 2 was active
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pointComplete = !excitingPort1;
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// next measurement will be from other port
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excitingPort1 = !excitingPort1;
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} else {
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// only one port active, point is complete after every measurement
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pointComplete = true;
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}
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if(pointComplete) {
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if (sweepCallback) {
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sweepCallback(data);
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}
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pointCnt++;
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if (pointCnt >= settings.points) {
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// reached end of sweep, start again
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pointCnt = 0;
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IFTableIndexCnt = 0;
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}
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}
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} else {
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// Manual control mode, simply pass on raw result
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if(statusCallback) {
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statusCallback(result);
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}
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}
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}
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static void FPGA_Interrupt(void*) {
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FPGA::InitiateSampleRead(ReadComplete);
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}
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bool VNA::Init() {
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LOG_DEBUG("Initializing...");
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manualMode = false;
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Si5351.Init();
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// Use Si5351 to generate reference frequencies for other PLLs and ADC
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Si5351.SetPLL(Si5351C::PLL::A, 800000000, Si5351C::PLLSource::XTAL);
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while(!Si5351.Locked(Si5351C::PLL::A));
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Si5351.SetPLL(Si5351C::PLL::B, 800000000, Si5351C::PLLSource::XTAL);
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while(!Si5351.Locked(Si5351C::PLL::B));
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extRefInUse = 0;
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extOutFreq = 0;
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Si5351.Disable(SiChannel::ReferenceOut);
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// Both MAX2871 get a 100MHz reference
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Si5351.SetCLK(SiChannel::Source, 100000000, Si5351C::PLL::A, Si5351C::DriveStrength::mA2);
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Si5351.Enable(SiChannel::Source);
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Si5351.SetCLK(SiChannel::LO1, 100000000, Si5351C::PLL::A, Si5351C::DriveStrength::mA2);
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Si5351.Enable(SiChannel::LO1);
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// 16MHz FPGA clock
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Si5351.SetCLK(SiChannel::FPGA, 16000000, Si5351C::PLL::A, Si5351C::DriveStrength::mA2);
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Si5351.Enable(SiChannel::FPGA);
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// Generate second LO with Si5351
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Si5351.SetCLK(SiChannel::Port1LO2, IF1 - IF2, Si5351C::PLL::B, Si5351C::DriveStrength::mA2);
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Si5351.Enable(SiChannel::Port1LO2);
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Si5351.SetCLK(SiChannel::Port2LO2, IF1 - IF2, Si5351C::PLL::B, Si5351C::DriveStrength::mA2);
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Si5351.Enable(SiChannel::Port2LO2);
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Si5351.SetCLK(SiChannel::RefLO2, IF1 - IF2, Si5351C::PLL::B, Si5351C::DriveStrength::mA2);
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Si5351.Enable(SiChannel::RefLO2);
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// PLL reset appears to realign phases of clock signals
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Si5351.ResetPLL(Si5351C::PLL::B);
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LOG_DEBUG("Si5351 locked");
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// FPGA clock is now present, can initialize
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if (!FPGA::Init(HaltedCallback)) {
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LOG_ERR("Aborting due to uninitialized FPGA");
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return false;
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}
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// Enable new data and sweep halt interrupt
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FPGA::EnableInterrupt(FPGA::Interrupt::NewData);
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FPGA::EnableInterrupt(FPGA::Interrupt::SweepHalted);
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Exti::SetCallback(FPGA_INTR_GPIO_Port, FPGA_INTR_Pin, Exti::EdgeType::Rising, Exti::Pull::Down, FPGA_Interrupt);
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// Initialize PLLs and build VCO maps
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// enable source synthesizer
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FPGA::Enable(FPGA::Periphery::SourceChip);
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FPGA::SetMode(FPGA::Mode::SourcePLL);
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Source.Init(100000000, false, 1, false);
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Source.SetPowerOutA(MAX2871::Power::n4dbm);
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// output B is not used
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Source.SetPowerOutB(MAX2871::Power::n4dbm, false);
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if(!Source.BuildVCOMap()) {
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LOG_WARN("Source VCO map failed");
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} else {
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LOG_INFO("Source VCO map complete");
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}
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Source.SetFrequency(1000000000);
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Source.UpdateFrequency();
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LOG_DEBUG("Source temp: %u", Source.GetTemp());
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// disable source synthesizer/enable LO synthesizer
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FPGA::SetMode(FPGA::Mode::FPGA);
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FPGA::Disable(FPGA::Periphery::SourceChip);
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FPGA::Enable(FPGA::Periphery::LO1Chip);
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FPGA::SetMode(FPGA::Mode::LOPLL);
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LO1.Init(100000000, false, 1, false);
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LO1.SetPowerOutA(MAX2871::Power::n4dbm);
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LO1.SetPowerOutB(MAX2871::Power::n4dbm);
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if(!LO1.BuildVCOMap()) {
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LOG_WARN("LO1 VCO map failed");
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} else {
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LOG_INFO("LO1 VCO map complete");
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}
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LO1.SetFrequency(1000000000 + IF1);
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LO1.UpdateFrequency();
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LOG_DEBUG("LO temp: %u", LO1.GetTemp());
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FPGA::SetMode(FPGA::Mode::FPGA);
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// disable both synthesizers
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FPGA::Disable(FPGA::Periphery::LO1Chip);
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FPGA::WriteMAX2871Default(Source.GetRegisters());
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LOG_INFO("Initialized");
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FPGA::Enable(FPGA::Periphery::ReadyLED);
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return true;
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}
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bool VNA::ConfigureSweep(Protocol::SweepSettings s, SweepCallback cb) {
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if (manualMode) {
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// was used in manual mode last, do full initialization before starting sweep
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VNA::Init();
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}
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bool VNA::Setup(Protocol::SweepSettings s, SweepCallback cb) {
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HW::SetMode(HW::Mode::VNA);
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if(s.excitePort1 == 0 && s.excitePort2 == 0) {
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// both ports disabled, set to idle
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SetIdle();
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// both ports disabled, nothing to do
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HW::SetIdle();
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active = false;
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return false;
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}
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sweepCallback = cb;
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settings = s;
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// Abort possible active sweep first
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FPGA::AbortSweep();
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FPGA::SetMode(FPGA::Mode::FPGA);
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uint16_t points = settings.points <= FPGA::MaxPoints ? settings.points : FPGA::MaxPoints;
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// Configure sweep
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FPGA::SetNumberOfPoints(points);
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@ -264,7 +78,7 @@ bool VNA::ConfigureSweep(Protocol::SweepSettings s, SweepCallback cb) {
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// Transfer PLL configuration to FPGA
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for (uint16_t i = 0; i < points; i++) {
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uint64_t freq = s.f_start + (s.f_stop - s.f_start) * i / (s.points - 1);
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uint64_t freq = s.f_start + (s.f_stop - s.f_start) * i / (points - 1);
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// SetFrequency only manipulates the register content in RAM, no SPI communication is done.
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// No mode-switch of FPGA necessary here.
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@ -355,251 +169,116 @@ bool VNA::ConfigureSweep(Protocol::SweepSettings s, SweepCallback cb) {
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// starting port depends on whether port 1 is active in sweep
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excitingPort1 = s.excitePort1;
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IFTableIndexCnt = 0;
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active = true;
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// Start the sweep
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FPGA::StartSweep();
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return true;
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}
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bool VNA::ConfigureManual(Protocol::ManualControl m, StatusCallback cb) {
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manualMode = true;
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statusCallback = cb;
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FPGA::AbortSweep();
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// Configure lowband source
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if (m.SourceLowEN) {
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Si5351.SetCLK(SiChannel::LowbandSource, m.SourceLowFrequency, Si5351C::PLL::B,
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(Si5351C::DriveStrength) m.SourceLowPower);
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Si5351.Enable(SiChannel::LowbandSource);
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} else {
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Si5351.Disable(SiChannel::LowbandSource);
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bool VNA::MeasurementDone(FPGA::SamplingResult result) {
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if(!active) {
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return false;
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}
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// Configure highband source
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Source.SetFrequency(m.SourceHighFrequency);
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Source.SetPowerOutA((MAX2871::Power) m.SourceHighPower);
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// Configure LO1
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LO1.SetFrequency(m.LO1Frequency);
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// Configure LO2
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if(m.LO2EN) {
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// Generate second LO with Si5351
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Si5351.SetCLK(SiChannel::Port1LO2, m.LO2Frequency, Si5351C::PLL::B, Si5351C::DriveStrength::mA2);
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Si5351.Enable(SiChannel::Port1LO2);
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Si5351.SetCLK(SiChannel::Port2LO2, m.LO2Frequency, Si5351C::PLL::B, Si5351C::DriveStrength::mA2);
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Si5351.Enable(SiChannel::Port2LO2);
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Si5351.SetCLK(SiChannel::RefLO2, m.LO2Frequency, Si5351C::PLL::B, Si5351C::DriveStrength::mA2);
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Si5351.Enable(SiChannel::RefLO2);
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// PLL reset appears to realign phases of clock signals
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Si5351.ResetPLL(Si5351C::PLL::B);
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// normal sweep mode
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auto port1_raw = std::complex<float>(result.P1I, result.P1Q);
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auto port2_raw = std::complex<float>(result.P2I, result.P2Q);
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auto ref = std::complex<float>(result.RefI, result.RefQ);
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auto port1 = port1_raw / ref;
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auto port2 = port2_raw / ref;
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data.pointNum = pointCnt;
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data.frequency = settings.f_start + (settings.f_stop - settings.f_start) * pointCnt / (settings.points - 1);
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if(excitingPort1) {
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data.real_S11 = port1.real();
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data.imag_S11 = port1.imag();
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data.real_S21 = port2.real();
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data.imag_S21 = port2.imag();
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} else {
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Si5351.Disable(SiChannel::Port1LO2);
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Si5351.Disable(SiChannel::Port2LO2);
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Si5351.Disable(SiChannel::RefLO2);
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data.real_S12 = port1.real();
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data.imag_S12 = port1.imag();
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data.real_S22 = port2.real();
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data.imag_S22 = port2.imag();
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}
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FPGA::WriteMAX2871Default(Source.GetRegisters());
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FPGA::SetNumberOfPoints(1);
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FPGA::SetSamplesPerPoint(m.Samples);
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// Configure single sweep point
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FPGA::WriteSweepConfig(0, !m.SourceHighband, Source.GetRegisters(),
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LO1.GetRegisters(), m.attenuator, 0, FPGA::SettlingTime::us20,
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FPGA::Samples::SPPRegister, 0,
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(FPGA::LowpassFilter) m.SourceHighLowpass);
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FPGA::SetWindow((FPGA::Window) m.WindowType);
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// Enable/Disable periphery
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FPGA::Enable(FPGA::Periphery::SourceChip, m.SourceHighCE);
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FPGA::Enable(FPGA::Periphery::SourceRF, m.SourceHighRFEN);
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FPGA::Enable(FPGA::Periphery::LO1Chip, m.LO1CE);
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FPGA::Enable(FPGA::Periphery::LO1RF, m.LO1RFEN);
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FPGA::Enable(FPGA::Periphery::Amplifier, m.AmplifierEN);
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FPGA::Enable(FPGA::Periphery::Port1Mixer, m.Port1EN);
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FPGA::Enable(FPGA::Periphery::Port2Mixer, m.Port2EN);
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FPGA::Enable(FPGA::Periphery::RefMixer, m.RefEN);
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FPGA::Enable(FPGA::Periphery::ExcitePort1, m.PortSwitch == 0);
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FPGA::Enable(FPGA::Periphery::ExcitePort2, m.PortSwitch == 1);
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FPGA::StartSweep();
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return true;
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}
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bool VNA::GetTemps(uint8_t *source, uint8_t *lo) {
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FPGA::SetMode(FPGA::Mode::SourcePLL);
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*source = Source.GetTemp();
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FPGA::SetMode(FPGA::Mode::LOPLL);
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*lo = LO1.GetTemp();
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FPGA::SetMode(FPGA::Mode::FPGA);
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return true;
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}
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void VNA::fillDeviceInfo(Protocol::DeviceInfo *info) {
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// read PLL temperatures
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uint8_t tempSource, tempLO;
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VNA::GetTemps(&tempSource, &tempLO);
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LOG_INFO("PLL temperatures: %u/%u", tempSource, tempLO);
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// Read ADC min/max
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auto limits = FPGA::GetADCLimits();
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LOG_INFO("ADC limits: P1: %d/%d P2: %d/%d R: %d/%d",
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limits.P1min, limits.P1max, limits.P2min, limits.P2max,
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limits.Rmin, limits.Rmax);
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#define ADC_LIMIT 30000
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// Set VNA related member of info struct
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if(limits.P1min < -ADC_LIMIT || limits.P1max > ADC_LIMIT
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|| limits.P2min < -ADC_LIMIT || limits.P2max > ADC_LIMIT
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|| limits.Rmin < -ADC_LIMIT || limits.Rmax > ADC_LIMIT) {
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info->ADC_overload = true;
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// figure out whether this sweep point is complete and which port gets excited next
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bool pointComplete = false;
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if(settings.excitePort1 == 1 && settings.excitePort2 == 1) {
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// point is complete when port 2 was active
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pointComplete = !excitingPort1;
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// next measurement will be from other port
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excitingPort1 = !excitingPort1;
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} else {
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info->ADC_overload = false;
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// only one port active, point is complete after every measurement
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pointComplete = true;
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}
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auto status = FPGA::GetStatus();
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info->LO1_locked = (status & (int) FPGA::Interrupt::LO1Unlock) ? 0 : 1;
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info->source_locked = (status & (int) FPGA::Interrupt::SourceUnlock) ? 0 : 1;
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info->extRefAvailable = Ref::available();
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info->extRefInUse = extRefInUse;
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info->temperatures.LO1 = tempLO;
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info->temperatures.source = tempSource;
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info->temperatures.MCU = 0;
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FPGA::ResetADCLimits();
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}
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bool VNA::Ref::available() {
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return Si5351.ExtCLKAvailable();
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}
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bool VNA::Ref::applySettings(Protocol::ReferenceSettings s) {
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if(extOutFreq != s.ExtRefOuputFreq) {
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extOutFreq = s.ExtRefOuputFreq;
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if(extOutFreq == 0) {
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Si5351.Disable(SiChannel::ReferenceOut);
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LOG_INFO("External reference output disabled");
|
||||
} else {
|
||||
Si5351.SetCLK(SiChannel::ReferenceOut, extOutFreq, Si5351C::PLL::A);
|
||||
Si5351.Enable(SiChannel::ReferenceOut);
|
||||
LOG_INFO("External reference output set to %luHz", extOutFreq);
|
||||
if(pointComplete) {
|
||||
if (sweepCallback) {
|
||||
sweepCallback(data);
|
||||
}
|
||||
}
|
||||
bool useExternal = s.UseExternalRef;
|
||||
if (s.AutomaticSwitch) {
|
||||
useExternal = Ref::available();
|
||||
}
|
||||
if(useExternal != extRefInUse) {
|
||||
// switch between internal and external reference
|
||||
extRefInUse = useExternal;
|
||||
if(extRefInUse) {
|
||||
if(!Ref::available()) {
|
||||
LOG_WARN("Forced switch to external reference but no signal detected");
|
||||
}
|
||||
Si5351.ConfigureCLKIn(10000000);
|
||||
Si5351.SetPLL(Si5351C::PLL::A, 800000000, Si5351C::PLLSource::CLKIN);
|
||||
Si5351.SetPLL(Si5351C::PLL::B, 800000000, Si5351C::PLLSource::CLKIN);
|
||||
LOG_INFO("Switched to external reference");
|
||||
FPGA::Enable(FPGA::Periphery::ExtRefLED);
|
||||
} else {
|
||||
Si5351.SetPLL(Si5351C::PLL::A, 800000000, Si5351C::PLLSource::XTAL);
|
||||
Si5351.SetPLL(Si5351C::PLL::B, 800000000, Si5351C::PLLSource::XTAL);
|
||||
LOG_INFO("Switched to internal reference");
|
||||
FPGA::Disable(FPGA::Periphery::ExtRefLED);
|
||||
}
|
||||
}
|
||||
constexpr uint32_t lock_timeout = 10;
|
||||
uint32_t start = HAL_GetTick();
|
||||
while(!Si5351.Locked(Si5351C::PLL::A) || !Si5351.Locked(Si5351C::PLL::A)) {
|
||||
if(HAL_GetTick() - start > lock_timeout) {
|
||||
LOG_ERR("Clock distributor PLLs failed to lock");
|
||||
return false;
|
||||
pointCnt++;
|
||||
if (pointCnt >= settings.points) {
|
||||
// reached end of sweep, start again
|
||||
pointCnt = 0;
|
||||
IFTableIndexCnt = 0;
|
||||
// request to trigger work function
|
||||
return true;
|
||||
}
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
bool VNA::ConfigureGenerator(Protocol::GeneratorSettings g) {
|
||||
if(g.activePort == 0) {
|
||||
// both ports disabled, no need to configure PLLs
|
||||
SetIdle();
|
||||
return true;
|
||||
}
|
||||
Protocol::ManualControl m;
|
||||
// LOs not required
|
||||
m.LO1CE = 0;
|
||||
m.LO1Frequency = 1000000000;
|
||||
m.LO1RFEN = 0;
|
||||
m.LO1RFEN = 0;
|
||||
m.LO2EN = 0;
|
||||
m.LO2Frequency = 60000000;
|
||||
m.Port1EN = 0;
|
||||
m.Port2EN = 0;
|
||||
m.RefEN = 0;
|
||||
m.Samples = 131072;
|
||||
m.WindowType = (int) FPGA::Window::None;
|
||||
// Select correct source
|
||||
if(g.frequency < BandSwitchFrequency) {
|
||||
m.SourceLowEN = 1;
|
||||
m.SourceLowFrequency = g.frequency;
|
||||
m.SourceHighCE = 0;
|
||||
m.SourceHighRFEN = 0;
|
||||
m.SourceHighFrequency = BandSwitchFrequency;
|
||||
m.SourceHighLowpass = (int) FPGA::LowpassFilter::M947;
|
||||
m.SourceHighPower = (int) MAX2871::Power::n4dbm;
|
||||
m.SourceHighband = false;
|
||||
} else {
|
||||
m.SourceLowEN = 0;
|
||||
m.SourceLowFrequency = BandSwitchFrequency;
|
||||
m.SourceHighCE = 1;
|
||||
m.SourceHighRFEN = 1;
|
||||
m.SourceHighFrequency = g.frequency;
|
||||
if(g.frequency < 900000000UL) {
|
||||
m.SourceHighLowpass = (int) FPGA::LowpassFilter::M947;
|
||||
} else if(g.frequency < 1800000000UL) {
|
||||
m.SourceHighLowpass = (int) FPGA::LowpassFilter::M1880;
|
||||
} else if(g.frequency < 3500000000UL) {
|
||||
m.SourceHighLowpass = (int) FPGA::LowpassFilter::M3500;
|
||||
} else {
|
||||
m.SourceHighLowpass = (int) FPGA::LowpassFilter::None;
|
||||
}
|
||||
m.SourceHighband = true;
|
||||
}
|
||||
switch(g.activePort) {
|
||||
case 1:
|
||||
m.AmplifierEN = 1;
|
||||
m.PortSwitch = 0;
|
||||
break;
|
||||
case 2:
|
||||
m.AmplifierEN = 1;
|
||||
m.PortSwitch = 1;
|
||||
break;
|
||||
}
|
||||
// Set level (not very accurate)
|
||||
if(g.cdbm_level > -1000) {
|
||||
// use higher source power (approx 0dbm with no attenuation)
|
||||
m.SourceHighPower = (int) MAX2871::Power::p5dbm;
|
||||
m.SourceLowPower = (int) Si5351C::DriveStrength::mA8;
|
||||
} else {
|
||||
// use lower source power (approx -10dbm with no attenuation)
|
||||
m.SourceHighPower = (int) MAX2871::Power::n4dbm;
|
||||
m.SourceLowPower = (int) Si5351C::DriveStrength::mA2;
|
||||
g.cdbm_level += 1000;
|
||||
}
|
||||
// calculate required attenuation
|
||||
uint16_t attval = -g.cdbm_level / 25;
|
||||
if(attval > 127) {
|
||||
attval = 127;
|
||||
}
|
||||
m.attenuator = attval;
|
||||
return ConfigureManual(m, nullptr);
|
||||
void VNA::Work() {
|
||||
// end of sweep
|
||||
HW::Ref::update();
|
||||
// Compile info packet
|
||||
Protocol::PacketInfo packet;
|
||||
packet.type = Protocol::PacketType::DeviceInfo;
|
||||
packet.info.FPGA_configured = 1;
|
||||
packet.info.FW_major = FW_MAJOR;
|
||||
packet.info.FW_minor = FW_MINOR;
|
||||
packet.info.HW_Revision = HW_REVISION;
|
||||
HW::fillDeviceInfo(&packet.info);
|
||||
Communication::Send(packet);
|
||||
FPGA::ResetADCLimits();
|
||||
// Start next sweep
|
||||
FPGA::StartSweep();
|
||||
}
|
||||
|
||||
void VNA::SetIdle() {
|
||||
FPGA::AbortSweep();
|
||||
FPGA::SetMode(FPGA::Mode::FPGA);
|
||||
FPGA::Enable(FPGA::Periphery::SourceChip, false);
|
||||
FPGA::Enable(FPGA::Periphery::SourceRF, false);
|
||||
FPGA::Enable(FPGA::Periphery::LO1Chip, false);
|
||||
FPGA::Enable(FPGA::Periphery::LO1RF, false);
|
||||
FPGA::Enable(FPGA::Periphery::Amplifier, false);
|
||||
FPGA::Enable(FPGA::Periphery::Port1Mixer, false);
|
||||
FPGA::Enable(FPGA::Periphery::Port2Mixer, false);
|
||||
FPGA::Enable(FPGA::Periphery::RefMixer, false);
|
||||
void VNA::SweepHalted() {
|
||||
if(!active) {
|
||||
return;
|
||||
}
|
||||
LOG_DEBUG("Halted before point %d", pointCnt);
|
||||
// Check if IF table has entry at this point
|
||||
// if (IFTable[IFTableIndexCnt].pointCnt == pointCnt) {
|
||||
// LOG_DEBUG("Shifting IF to %lu at point %u",
|
||||
// IFTable[IFTableIndexCnt].IF1, pointCnt);
|
||||
// Si5351.WriteRawCLKConfig(1, IFTable[IFTableIndexCnt].clkconfig);
|
||||
// Si5351.WriteRawCLKConfig(4, IFTable[IFTableIndexCnt].clkconfig);
|
||||
// Si5351.WriteRawCLKConfig(5, IFTable[IFTableIndexCnt].clkconfig);
|
||||
// Si5351.ResetPLL(Si5351C::PLL::B);
|
||||
// IFTableIndexCnt++;
|
||||
// }
|
||||
uint64_t frequency = settings.f_start
|
||||
+ (settings.f_stop - settings.f_start) * pointCnt
|
||||
/ (settings.points - 1);
|
||||
if (frequency < BandSwitchFrequency) {
|
||||
// need the Si5351 as Source
|
||||
Si5351.SetCLK(SiChannel::LowbandSource, frequency, Si5351C::PLL::B,
|
||||
Si5351C::DriveStrength::mA2);
|
||||
if (pointCnt == 0) {
|
||||
// First point in sweep, enable CLK
|
||||
Si5351.Enable(SiChannel::LowbandSource);
|
||||
FPGA::Disable(FPGA::Periphery::SourceRF);
|
||||
}
|
||||
} else {
|
||||
// first sweep point in highband is also halted, disable lowband source
|
||||
Si5351.Disable(SiChannel::LowbandSource);
|
||||
FPGA::Enable(FPGA::Periphery::SourceRF);
|
||||
}
|
||||
|
||||
FPGA::ResumeHaltedSweep();
|
||||
}
|
||||
|
||||
void VNA::Stop() {
|
||||
active = false;
|
||||
FPGA::AbortSweep();
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue