g4klx/MMDVM_HS
1
0
Fork 0
mirror of https://github.com/g4klx/MMDVM_HS.git synced 2025-12-06 07:02:00 +01:00
Code Issues Actions Packages Projects Releases Wiki Activity

Adding 220 MHz and 900 MHz bands support

Browse source
This commit is contained in:
Andy CA6JAU 2017-02-10 17:58:51 -03:00
parent e04551979d
commit ee01691dc4
4 changed files with 63 additions and 25 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

52
ADF7021.cpp
View file

@ -134,13 +134,40 @@ void CIO::ifConf()
float divider; float divider;
uint8_t N_divider; uint8_t N_divider;
uint16_t F_divider; uint16_t F_divider;
uint32_t div2;
uint32_t ADF7021_REG1 = 0;
uint32_t ADF7021_REG2 = 0; uint32_t ADF7021_REG2 = 0;
uint32_t ADF7021_REG3 = 0; uint32_t ADF7021_REG3 = 0;
uint32_t ADF7021_REG4 = 0; uint32_t ADF7021_REG4 = 0;
uint32_t ADF7021_REG13 = 0; uint32_t ADF7021_REG13 = 0;
divider = (m_frequency_rx - 100000) / (ADF7021_PFD / 2.0); // Check frequency band
if( (m_frequency_tx >= VHF1_MIN) && (m_frequency_tx < VHF1_MAX) ) {
ADF7021_REG1 = ADF7021_REG1_VHF1; // VHF1, external VCO
div2 = 1U;
}
else if( (m_frequency_tx >= VHF2_MIN) && (m_frequency_tx < VHF2_MAX) ) {
ADF7021_REG1 = ADF7021_REG1_VHF2; // VHF1, external VCO
div2 = 1U;
}
else if( (m_frequency_tx >= UHF1_MIN)&&(m_frequency_tx < UHF1_MAX) ) {
ADF7021_REG1 = ADF7021_REG1_UHF1; // UHF1, internal VCO
div2 = 1U;
}
else if( (m_frequency_tx >= UHF2_MIN)&&(m_frequency_tx < UHF2_MAX) ) {
ADF7021_REG1 = ADF7021_REG1_UHF2; // UHF2, internal VCO
div2 = 2U;
}
else {
ADF7021_REG1 = ADF7021_REG1_UHF1; // UHF1, internal VCO
div2 = 1U;
}
if( div2 == 1U )
divider = (m_frequency_rx - 100000) / (ADF7021_PFD / 2U);
else
divider = (m_frequency_rx - 100000) / ADF7021_PFD;
N_divider = floor(divider); N_divider = floor(divider);
divider = (divider - N_divider) * 32768; divider = (divider - N_divider) * 32768;
@ -157,7 +184,10 @@ void CIO::ifConf()
ADF7021_RX_REG0 |= (uint32_t) N_divider << 19; // frequency; ADF7021_RX_REG0 |= (uint32_t) N_divider << 19; // frequency;
ADF7021_RX_REG0 |= (uint32_t) F_divider << 4; // frequency; ADF7021_RX_REG0 |= (uint32_t) F_divider << 4; // frequency;
divider = m_frequency_tx / (ADF7021_PFD / 2.0); if( div2 == 1U )
divider = m_frequency_tx / (ADF7021_PFD / 2U);
else
divider = m_frequency_tx / ADF7021_PFD;
N_divider = floor(divider); N_divider = floor(divider);
divider = (divider - N_divider) * 32768; divider = (divider - N_divider) * 32768;
@ -192,7 +222,7 @@ void CIO::ifConf()
ADF7021_REG13 |= (uint32_t) ADF7021_SLICER_TH_DSTAR << 4; // slicer threshold ADF7021_REG13 |= (uint32_t) ADF7021_SLICER_TH_DSTAR << 4; // slicer threshold
ADF7021_REG2 = (uint32_t) 0b00 << 28; // clock normal ADF7021_REG2 = (uint32_t) 0b00 << 28; // clock normal
ADF7021_REG2 |= (uint32_t) ADF7021_DEV_DSTAR << 19; // deviation ADF7021_REG2 |= (uint32_t) (ADF7021_DEV_DSTAR / div2)<< 19; // deviation
ADF7021_REG2 |= (uint32_t) 0b001 << 4; // modulation (GMSK) ADF7021_REG2 |= (uint32_t) 0b001 << 4; // modulation (GMSK)
} }
else if (m_dmrEnable) { else if (m_dmrEnable) {
@ -213,7 +243,7 @@ void CIO::ifConf()
ADF7021_REG13 |= (uint32_t) ADF7021_SLICER_TH_DMR << 4; // slicer threshold ADF7021_REG13 |= (uint32_t) ADF7021_SLICER_TH_DMR << 4; // slicer threshold
ADF7021_REG2 = (uint32_t) 0b10 << 28; // invert data ADF7021_REG2 = (uint32_t) 0b10 << 28; // invert data
ADF7021_REG2 |= (uint32_t) ADF7021_DEV_DMR << 19; // deviation ADF7021_REG2 |= (uint32_t) (ADF7021_DEV_DMR / div2) << 19; // deviation
ADF7021_REG2 |= (uint32_t) 0b111 << 4; // modulation (4FSK) ADF7021_REG2 |= (uint32_t) 0b111 << 4; // modulation (4FSK)
} }
else if (m_ysfEnable) { else if (m_ysfEnable) {
@ -234,7 +264,7 @@ void CIO::ifConf()
ADF7021_REG13 |= (uint32_t) ADF7021_SLICER_TH_YSF << 4; // slicer threshold ADF7021_REG13 |= (uint32_t) ADF7021_SLICER_TH_YSF << 4; // slicer threshold
ADF7021_REG2 = (uint32_t) 0b10 << 28; // invert data ADF7021_REG2 = (uint32_t) 0b10 << 28; // invert data
ADF7021_REG2 |= (uint32_t) ADF7021_DEV_YSF << 19; // deviation ADF7021_REG2 |= (uint32_t) (ADF7021_DEV_YSF / div2) << 19; // deviation
ADF7021_REG2 |= (uint32_t) 0b111 << 4; // modulation (4FSK) ADF7021_REG2 |= (uint32_t) 0b111 << 4; // modulation (4FSK)
} }
else if (m_p25Enable) { else if (m_p25Enable) {
@ -255,16 +285,12 @@ void CIO::ifConf()
ADF7021_REG13 |= (uint32_t) ADF7021_SLICER_TH_P25 << 4; // slicer threshold ADF7021_REG13 |= (uint32_t) ADF7021_SLICER_TH_P25 << 4; // slicer threshold
ADF7021_REG2 = (uint32_t) 0b10 << 28; // invert data ADF7021_REG2 = (uint32_t) 0b10 << 28; // invert data
ADF7021_REG2 |= (uint32_t) ADF7021_DEV_P25 << 19; // deviation ADF7021_REG2 |= (uint32_t) (ADF7021_DEV_P25 / div2) << 19; // deviation
ADF7021_REG2 |= (uint32_t) 0b111 << 4; // modulation (4FSK) ADF7021_REG2 |= (uint32_t) 0b111 << 4; // modulation (4FSK)
} }
// VCO/OSCILLATOR (REG1) // VCO/OSCILLATOR (REG1)
if( (m_frequency_tx >= VHF_MIN) && (m_frequency_tx < VHF_MAX) ) AD7021_control_word = ADF7021_REG1;
AD7021_control_word = ADF7021_REG1_VHF; // VHF, external VCO
else if( (m_frequency_tx >= UHF_MIN)&&(m_frequency_tx < UHF_MAX) )
AD7021_control_word = ADF7021_REG1_UHF; // UHF, internal VCO
Send_AD7021_control(); Send_AD7021_control();
// TX/RX CLOCK (3) // TX/RX CLOCK (3)

18
ADF7021.h
View file

@ -41,8 +41,10 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
#define ADF7021_PFD 3686400.0 #define ADF7021_PFD 3686400.0
// PLL (REG 01) // PLL (REG 01)
#define ADF7021_REG1_VHF 0x021F5041 #define ADF7021_REG1_VHF1 0x021F5041
#define ADF7021_REG1_UHF 0x00575041 #define ADF7021_REG1_VHF2 0x021F5041
#define ADF7021_REG1_UHF1 0x00575041
#define ADF7021_REG1_UHF2 0x00535041
// Deviation of modulator (REG 02) // Deviation of modulator (REG 02)
#define ADF7021_DEV_DSTAR 43U #define ADF7021_DEV_DSTAR 43U
@ -91,8 +93,10 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
#define ADF7021_PFD 4920000.0 #define ADF7021_PFD 4920000.0
// PLL (REG 01) // PLL (REG 01)
#define ADF7021_REG1_VHF 0x021F5041 #define ADF7021_REG1_VHF1 0x021F5041
#define ADF7021_REG1_UHF 0x00575041 #define ADF7021_REG1_VHF2 0x021F5041
#define ADF7021_REG1_UHF1 0x00575041
#define ADF7021_REG1_UHF2 0x00535041
// Deviation of modulator (REG 02) // Deviation of modulator (REG 02)
#define ADF7021_DEV_DSTAR 32U #define ADF7021_DEV_DSTAR 32U
@ -141,8 +145,10 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
#define ADF7021_PFD 6144000.0 #define ADF7021_PFD 6144000.0
// PLL (REG 01) // PLL (REG 01)
#define ADF7021_REG1_VHF 0x021F5021 #define ADF7021_REG1_VHF1 0x021F5021
#define ADF7021_REG1_UHF 0x00575021 #define ADF7021_REG1_VHF2 0x021F5021
#define ADF7021_REG1_UHF1 0x00575021
#define ADF7021_REG1_UHF2 0x00535021
// Deviation of modulator (REG 02) // Deviation of modulator (REG 02)
#define ADF7021_DEV_DSTAR 26U #define ADF7021_DEV_DSTAR 26U

6
IO.cpp
View file

@ -192,8 +192,10 @@ uint8_t CIO::setFreq(uint32_t frequency_rx, uint32_t frequency_tx)
// power level // power level
m_power = 0x20; m_power = 0x20;
if( !( ((frequency_rx >= VHF_MIN)&&(frequency_rx < VHF_MAX)) || ((frequency_tx >= VHF_MIN)&&(frequency_tx < VHF_MAX)) || \ if( !( ((frequency_rx >= VHF1_MIN)&&(frequency_rx < VHF1_MAX)) || ((frequency_tx >= VHF1_MIN)&&(frequency_tx < VHF1_MAX)) || \
((frequency_rx >= UHF_MIN)&&(frequency_rx < UHF_MAX)) || ((frequency_tx >= UHF_MIN)&&(frequency_tx < UHF_MAX)) ) ) ((frequency_rx >= UHF1_MIN)&&(frequency_rx < UHF1_MAX)) || ((frequency_tx >= UHF1_MIN)&&(frequency_tx < UHF1_MAX)) || \
((frequency_rx >= VHF2_MIN)&&(frequency_rx < VHF2_MAX)) || ((frequency_tx >= VHF2_MIN)&&(frequency_tx < VHF2_MAX)) || \
((frequency_rx >= UHF2_MIN)&&(frequency_rx < UHF2_MAX)) || ((frequency_tx >= UHF2_MIN)&&(frequency_tx < UHF2_MAX)) ) )
return 4U; return 4U;
m_frequency_rx = frequency_rx; m_frequency_rx = frequency_rx;

12
IO.h
View file

@ -26,10 +26,14 @@
#define LOW 0 #define LOW 0
#define HIGH 1 #define HIGH 1
#define VHF_MIN 144000000 #define VHF1_MIN 144000000
#define VHF_MAX 148000000 #define VHF1_MAX 148000000
#define UHF_MIN 430000000 #define VHF2_MIN 219000000
#define UHF_MAX 450000000 #define VHF2_MAX 225000000
#define UHF1_MIN 420000000
#define UHF1_MAX 450000000
#define UHF2_MIN 902000000
#define UHF2_MAX 928000000
extern uint32_t m_frequency_rx; extern uint32_t m_frequency_rx;
extern uint32_t m_frequency_tx; extern uint32_t m_frequency_tx;