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https://github.com/g4klx/MMDVM_HS.git
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Adding 220 MHz and 900 MHz bands support
This commit is contained in:
Andy CA6JAU
parent
e04551979d
commit
ee01691dc4
52
ADF7021.cpp
52
ADF7021.cpp
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@ -134,13 +134,40 @@ void CIO::ifConf()
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float divider;
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uint8_t N_divider;
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uint16_t F_divider;
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uint32_t div2;
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uint32_t ADF7021_REG1 = 0;
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uint32_t ADF7021_REG2 = 0;
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uint32_t ADF7021_REG3 = 0;
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uint32_t ADF7021_REG4 = 0;
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uint32_t ADF7021_REG13 = 0;
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divider = (m_frequency_rx - 100000) / (ADF7021_PFD / 2.0);
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// Check frequency band
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if( (m_frequency_tx >= VHF1_MIN) && (m_frequency_tx < VHF1_MAX) ) {
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ADF7021_REG1 = ADF7021_REG1_VHF1; // VHF1, external VCO
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div2 = 1U;
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}
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else if( (m_frequency_tx >= VHF2_MIN) && (m_frequency_tx < VHF2_MAX) ) {
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ADF7021_REG1 = ADF7021_REG1_VHF2; // VHF1, external VCO
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div2 = 1U;
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}
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else if( (m_frequency_tx >= UHF1_MIN)&&(m_frequency_tx < UHF1_MAX) ) {
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ADF7021_REG1 = ADF7021_REG1_UHF1; // UHF1, internal VCO
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div2 = 1U;
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}
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else if( (m_frequency_tx >= UHF2_MIN)&&(m_frequency_tx < UHF2_MAX) ) {
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ADF7021_REG1 = ADF7021_REG1_UHF2; // UHF2, internal VCO
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div2 = 2U;
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}
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else {
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ADF7021_REG1 = ADF7021_REG1_UHF1; // UHF1, internal VCO
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div2 = 1U;
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}
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if( div2 == 1U )
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divider = (m_frequency_rx - 100000) / (ADF7021_PFD / 2U);
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else
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divider = (m_frequency_rx - 100000) / ADF7021_PFD;
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N_divider = floor(divider);
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divider = (divider - N_divider) * 32768;
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@ -157,7 +184,10 @@ void CIO::ifConf()
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ADF7021_RX_REG0 |= (uint32_t) N_divider << 19; // frequency;
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ADF7021_RX_REG0 |= (uint32_t) F_divider << 4; // frequency;
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divider = m_frequency_tx / (ADF7021_PFD / 2.0);
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if( div2 == 1U )
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divider = m_frequency_tx / (ADF7021_PFD / 2U);
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else
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divider = m_frequency_tx / ADF7021_PFD;
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N_divider = floor(divider);
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divider = (divider - N_divider) * 32768;
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@ -192,7 +222,7 @@ void CIO::ifConf()
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ADF7021_REG13 |= (uint32_t) ADF7021_SLICER_TH_DSTAR << 4; // slicer threshold
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ADF7021_REG2 = (uint32_t) 0b00 << 28; // clock normal
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ADF7021_REG2 |= (uint32_t) ADF7021_DEV_DSTAR << 19; // deviation
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ADF7021_REG2 |= (uint32_t) (ADF7021_DEV_DSTAR / div2)<< 19; // deviation
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ADF7021_REG2 |= (uint32_t) 0b001 << 4; // modulation (GMSK)
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}
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else if (m_dmrEnable) {
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@ -213,7 +243,7 @@ void CIO::ifConf()
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ADF7021_REG13 |= (uint32_t) ADF7021_SLICER_TH_DMR << 4; // slicer threshold
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ADF7021_REG2 = (uint32_t) 0b10 << 28; // invert data
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ADF7021_REG2 |= (uint32_t) ADF7021_DEV_DMR << 19; // deviation
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ADF7021_REG2 |= (uint32_t) (ADF7021_DEV_DMR / div2) << 19; // deviation
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ADF7021_REG2 |= (uint32_t) 0b111 << 4; // modulation (4FSK)
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}
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else if (m_ysfEnable) {
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@ -234,7 +264,7 @@ void CIO::ifConf()
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ADF7021_REG13 |= (uint32_t) ADF7021_SLICER_TH_YSF << 4; // slicer threshold
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ADF7021_REG2 = (uint32_t) 0b10 << 28; // invert data
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ADF7021_REG2 |= (uint32_t) ADF7021_DEV_YSF << 19; // deviation
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ADF7021_REG2 |= (uint32_t) (ADF7021_DEV_YSF / div2) << 19; // deviation
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ADF7021_REG2 |= (uint32_t) 0b111 << 4; // modulation (4FSK)
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}
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else if (m_p25Enable) {
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@ -255,16 +285,12 @@ void CIO::ifConf()
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ADF7021_REG13 |= (uint32_t) ADF7021_SLICER_TH_P25 << 4; // slicer threshold
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ADF7021_REG2 = (uint32_t) 0b10 << 28; // invert data
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ADF7021_REG2 |= (uint32_t) ADF7021_DEV_P25 << 19; // deviation
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ADF7021_REG2 |= (uint32_t) (ADF7021_DEV_P25 / div2) << 19; // deviation
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ADF7021_REG2 |= (uint32_t) 0b111 << 4; // modulation (4FSK)
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}
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// VCO/OSCILLATOR (REG1)
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if( (m_frequency_tx >= VHF_MIN) && (m_frequency_tx < VHF_MAX) )
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AD7021_control_word = ADF7021_REG1_VHF; // VHF, external VCO
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else if( (m_frequency_tx >= UHF_MIN)&&(m_frequency_tx < UHF_MAX) )
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AD7021_control_word = ADF7021_REG1_UHF; // UHF, internal VCO
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AD7021_control_word = ADF7021_REG1;
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Send_AD7021_control();
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// TX/RX CLOCK (3)
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18
ADF7021.h
18
ADF7021.h
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@ -41,8 +41,10 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
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#define ADF7021_PFD 3686400.0
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// PLL (REG 01)
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#define ADF7021_REG1_VHF 0x021F5041
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#define ADF7021_REG1_UHF 0x00575041
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#define ADF7021_REG1_VHF1 0x021F5041
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#define ADF7021_REG1_VHF2 0x021F5041
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#define ADF7021_REG1_UHF1 0x00575041
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#define ADF7021_REG1_UHF2 0x00535041
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// Deviation of modulator (REG 02)
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#define ADF7021_DEV_DSTAR 43U
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@ -91,8 +93,10 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
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#define ADF7021_PFD 4920000.0
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// PLL (REG 01)
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#define ADF7021_REG1_VHF 0x021F5041
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#define ADF7021_REG1_UHF 0x00575041
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#define ADF7021_REG1_VHF1 0x021F5041
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#define ADF7021_REG1_VHF2 0x021F5041
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#define ADF7021_REG1_UHF1 0x00575041
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#define ADF7021_REG1_UHF2 0x00535041
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// Deviation of modulator (REG 02)
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#define ADF7021_DEV_DSTAR 32U
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@ -141,8 +145,10 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
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#define ADF7021_PFD 6144000.0
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// PLL (REG 01)
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#define ADF7021_REG1_VHF 0x021F5021
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#define ADF7021_REG1_UHF 0x00575021
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#define ADF7021_REG1_VHF1 0x021F5021
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#define ADF7021_REG1_VHF2 0x021F5021
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#define ADF7021_REG1_UHF1 0x00575021
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#define ADF7021_REG1_UHF2 0x00535021
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// Deviation of modulator (REG 02)
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#define ADF7021_DEV_DSTAR 26U
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6
IO.cpp
6
IO.cpp
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@ -192,8 +192,10 @@ uint8_t CIO::setFreq(uint32_t frequency_rx, uint32_t frequency_tx)
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// power level
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m_power = 0x20;
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if( !( ((frequency_rx >= VHF_MIN)&&(frequency_rx < VHF_MAX)) || ((frequency_tx >= VHF_MIN)&&(frequency_tx < VHF_MAX)) || \
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((frequency_rx >= UHF_MIN)&&(frequency_rx < UHF_MAX)) || ((frequency_tx >= UHF_MIN)&&(frequency_tx < UHF_MAX)) ) )
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if( !( ((frequency_rx >= VHF1_MIN)&&(frequency_rx < VHF1_MAX)) || ((frequency_tx >= VHF1_MIN)&&(frequency_tx < VHF1_MAX)) || \
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((frequency_rx >= UHF1_MIN)&&(frequency_rx < UHF1_MAX)) || ((frequency_tx >= UHF1_MIN)&&(frequency_tx < UHF1_MAX)) || \
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((frequency_rx >= VHF2_MIN)&&(frequency_rx < VHF2_MAX)) || ((frequency_tx >= VHF2_MIN)&&(frequency_tx < VHF2_MAX)) || \
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((frequency_rx >= UHF2_MIN)&&(frequency_rx < UHF2_MAX)) || ((frequency_tx >= UHF2_MIN)&&(frequency_tx < UHF2_MAX)) ) )
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return 4U;
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m_frequency_rx = frequency_rx;
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12
IO.h
12
IO.h
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@ -26,10 +26,14 @@
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#define LOW 0
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#define HIGH 1
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#define VHF_MIN 144000000
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#define VHF_MAX 148000000
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#define UHF_MIN 430000000
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#define UHF_MAX 450000000
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#define VHF1_MIN 144000000
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#define VHF1_MAX 148000000
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#define VHF2_MIN 219000000
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#define VHF2_MAX 225000000
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#define UHF1_MIN 420000000
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#define UHF1_MAX 450000000
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#define UHF2_MIN 902000000
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#define UHF2_MAX 928000000
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extern uint32_t m_frequency_rx;
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extern uint32_t m_frequency_tx;
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