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Adding support for P25 wide modulation
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@ -345,7 +345,11 @@ void CIO::ifConf(MMDVM_STATE modemState, bool reset)
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ADF7021_REG2 = (uint32_t) 0b10 << 28; // invert data (and RC alpha = 0.5)
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ADF7021_REG2 |= (uint32_t) (ADF7021_DEV_P25 / div2) << 19; // deviation
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#if defined(ENABLE_P25_WIDE)
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ADF7021_REG2 |= (uint32_t) 0b011 << 4; // modulation (4FSK)
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#else
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ADF7021_REG2 |= (uint32_t) 0b111 << 4; // modulation (RC 4FSK)
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#endif
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break;
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default:
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10
ADF7021.h
10
ADF7021.h
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@ -62,7 +62,11 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
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#define ADF7021_DEV_DMR 23U
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#define ADF7021_DEV_YSF_L 18U
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#define ADF7021_DEV_YSF_H 36U
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#if defined(ENABLE_P25_WIDE)
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#define ADF7021_DEV_P25 32U
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#else
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#define ADF7021_DEV_P25 22U
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#endif
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// TX/RX CLOCK register (REG 03)
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#define ADF7021_REG3_DSTAR 0x2A4C4193
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@ -142,7 +146,11 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
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#define ADF7021_DEV_DMR 14U
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#define ADF7021_DEV_YSF_L 11U
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#define ADF7021_DEV_YSF_H 21U
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#if defined(ENABLE_P25_WIDE)
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#define ADF7021_DEV_P25 21U
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#else
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#define ADF7021_DEV_P25 14U
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#endif
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// TX/RX CLOCK register (REG 03)
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#define ADF7021_REG3_DSTAR 0x29EC4153
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@ -220,7 +228,7 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
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#define ADF7021_SLICER_TH_DMR 57U
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#define ADF7021_SLICER_TH_YSF_L 38U
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#define ADF7021_SLICER_TH_YSF_H 75U
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#define ADF7021_SLICER_TH_P25 52U
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#define ADF7021_SLICER_TH_P25 47U
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#endif
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