mirror of
https://github.com/g4klx/MMDVM_HS.git
synced 2026-04-05 14:35:14 +00:00
Adding 19.68 MHz TCXO support
This commit is contained in:
Andy CA6JAU
parent
7d6d179846
commit
d71b7aa053
4 changed files with 186 additions and 67 deletions
135
ADF7021.cpp
135
ADF7021.cpp
|
|
@ -22,7 +22,7 @@
|
|||
|
||||
#include "Config.h"
|
||||
|
||||
#if defined(ADF7021)
|
||||
#if defined(ENABLE_ADF7021)
|
||||
|
||||
#include "Globals.h"
|
||||
#include "IO.h"
|
||||
|
|
@ -67,8 +67,8 @@ void Send_REG0_RX()
|
|||
|
||||
ADF7021_RX_REG0 = (uint32_t)0b0000;
|
||||
ADF7021_RX_REG0 |= (uint32_t)0b01011 << 27; // mux regulator/uart enabled/receive
|
||||
ADF7021_RX_REG0 |= (uint32_t)N_divider << 19; //frequency;
|
||||
ADF7021_RX_REG0 |= (uint32_t)F_divider << 4; //frequency;
|
||||
ADF7021_RX_REG0 |= (uint32_t)N_divider << 19; // frequency;
|
||||
ADF7021_RX_REG0 |= (uint32_t)F_divider << 4; // frequency;
|
||||
|
||||
AD7021_control_byte = ADF7021_RX_REG0;
|
||||
Send_AD7021_control();
|
||||
|
|
@ -87,10 +87,10 @@ void Send_REG0_TX()
|
|||
divider = (divider - N_divider) * 32768;
|
||||
F_divider = floor(divider + 0.5);
|
||||
|
||||
ADF7021_TX_REG0 = (uint32_t)0b0000; // register 0
|
||||
ADF7021_TX_REG0 |= (uint32_t)0b01010 << 27; // mux regulator/uart enabled/transmit
|
||||
ADF7021_TX_REG0 |= (uint32_t)N_divider << 19; //frequency;
|
||||
ADF7021_TX_REG0 |= (uint32_t)F_divider << 4; //frequency;
|
||||
ADF7021_TX_REG0 = (uint32_t) 0b0000; // register 0
|
||||
ADF7021_TX_REG0 |= (uint32_t) 0b01010 << 27; // mux regulator/uart enabled/transmit
|
||||
ADF7021_TX_REG0 |= (uint32_t) N_divider << 19; // frequency;
|
||||
ADF7021_TX_REG0 |= (uint32_t) F_divider << 4; // frequency;
|
||||
|
||||
AD7021_control_byte = ADF7021_TX_REG0;
|
||||
Send_AD7021_control();
|
||||
|
|
@ -98,88 +98,101 @@ void Send_REG0_TX()
|
|||
|
||||
void CIO::ifConf()
|
||||
{
|
||||
uint32_t ADF7021_REG2 = 0;
|
||||
uint32_t ADF7021_REG3 = 0;
|
||||
uint32_t ADF7021_REG4 = 0;
|
||||
uint32_t ADF7021_REG2 = 0;
|
||||
uint32_t ADF7021_REG3 = 0;
|
||||
uint32_t ADF7021_REG4 = 0;
|
||||
uint32_t ADF7021_REG13 = 0;
|
||||
|
||||
if (m_dstarEnable) {
|
||||
// Dev: 1200 Hz, symb rate = 4800
|
||||
|
||||
ADF7021_REG3 = 0x2A4C4193;
|
||||
ADF7021_REG4 = 0x00A82A94;
|
||||
ADF7021_REG13 = 0x0000000D;
|
||||
ADF7021_REG3 = ADF7021_REG3_DSTAR;
|
||||
|
||||
// K=32
|
||||
ADF7021_REG4 = (uint32_t) 0b0100 << 0; // register 4
|
||||
ADF7021_REG4 |= (uint32_t) 0b001 << 4; // mode, GMSK
|
||||
ADF7021_REG4 |= (uint32_t) 0b1 << 7;
|
||||
ADF7021_REG4 |= (uint32_t) 0b10 << 8;
|
||||
ADF7021_REG4 |= (uint32_t) ADF7021_DISC_BW_DSTAR << 10; // Disc BW
|
||||
ADF7021_REG4 |= (uint32_t) ADF7021_POST_BW_DSTAR << 20; // Post dem BW
|
||||
ADF7021_REG4 |= (uint32_t) 0b00 << 30; // IF filter
|
||||
|
||||
ADF7021_REG2 = (uint32_t)0b00 << 28; // clock normal
|
||||
ADF7021_REG2 |= (uint32_t)0b000101010 << 19; // deviation
|
||||
ADF7021_REG2 |= (uint32_t)0b001 << 4; // modulation (GMSK)
|
||||
ADF7021_REG13 = (uint32_t) 0b1101 << 0; // register 13
|
||||
ADF7021_REG13 |= (uint32_t) ADF7021_SLICER_TH_DSTAR << 4; // slicer threshold
|
||||
|
||||
ADF7021_REG2 = (uint32_t) 0b00 << 28; // clock normal
|
||||
ADF7021_REG2 |= (uint32_t) ADF7021_DEV_DSTAR << 19; // deviation
|
||||
ADF7021_REG2 |= (uint32_t) 0b001 << 4; // modulation (GMSK)
|
||||
}
|
||||
else if (m_dmrEnable) {
|
||||
// Dev: +1 symb 648 Hz, symb rate = 4800
|
||||
|
||||
ADF7021_REG3 = 0x2A4C80D3;
|
||||
ADF7021_REG3 = ADF7021_REG3_DMR;
|
||||
|
||||
// K=32
|
||||
ADF7021_REG4 = (uint32_t)0b0100 << 0; // register 4
|
||||
ADF7021_REG4 |= (uint32_t)0b011 << 4; // mode, 4FSK
|
||||
ADF7021_REG4 |= (uint32_t)0b0 << 7;
|
||||
ADF7021_REG4 |= (uint32_t)0b11 << 8;
|
||||
ADF7021_REG4 |= (uint32_t)393U << 10; // Disc BW
|
||||
ADF7021_REG4 |= (uint32_t)65U << 20; // Post dem BW
|
||||
ADF7021_REG4 |= (uint32_t)0b10 << 30; // IF filter
|
||||
ADF7021_REG4 = (uint32_t) 0b0100 << 0; // register 4
|
||||
ADF7021_REG4 |= (uint32_t) 0b011 << 4; // mode, 4FSK
|
||||
ADF7021_REG4 |= (uint32_t) 0b0 << 7;
|
||||
ADF7021_REG4 |= (uint32_t) 0b11 << 8;
|
||||
ADF7021_REG4 |= (uint32_t) ADF7021_DISC_BW_DMR << 10; // Disc BW
|
||||
ADF7021_REG4 |= (uint32_t) ADF7021_POST_BW_DMR << 20; // Post dem BW
|
||||
ADF7021_REG4 |= (uint32_t) 0b10 << 30; // IF filter
|
||||
|
||||
ADF7021_REG13 = 0x0000033D;
|
||||
ADF7021_REG13 = (uint32_t) 0b1101 << 0; // register 13
|
||||
ADF7021_REG13 |= (uint32_t) ADF7021_SLICER_TH_DMR << 4; // slicer threshold
|
||||
|
||||
ADF7021_REG2 = (uint32_t)0b10 << 28; // invert data
|
||||
ADF7021_REG2 |= (uint32_t)24U << 19; // deviation
|
||||
ADF7021_REG2 |= (uint32_t)0b111 << 4; // modulation (4FSK)
|
||||
ADF7021_REG2 = (uint32_t) 0b10 << 28; // invert data
|
||||
ADF7021_REG2 |= (uint32_t) ADF7021_DEV_DMR << 19; // deviation
|
||||
ADF7021_REG2 |= (uint32_t) 0b111 << 4; // modulation (4FSK)
|
||||
}
|
||||
else if (m_ysfEnable) {
|
||||
// Dev: +1 symb 900 Hz, symb rate = 4800
|
||||
|
||||
ADF7021_REG3 = 0x2A4C80D3;
|
||||
ADF7021_REG3 = ADF7021_REG3_YSF;
|
||||
|
||||
// K=28
|
||||
ADF7021_REG4 = (uint32_t)0b0100 << 0; // register 4
|
||||
ADF7021_REG4 |= (uint32_t)0b011 << 4; // mode, 4FSK
|
||||
ADF7021_REG4 |= (uint32_t)0b0 << 7;
|
||||
ADF7021_REG4 |= (uint32_t)0b11 << 8;
|
||||
ADF7021_REG4 |= (uint32_t)344U << 10; // Disc BW
|
||||
ADF7021_REG4 |= (uint32_t)65U << 20; // Post dem BW
|
||||
ADF7021_REG4 |= (uint32_t)0b10 << 30; // IF filter
|
||||
ADF7021_REG4 = (uint32_t) 0b0100 << 0; // register 4
|
||||
ADF7021_REG4 |= (uint32_t) 0b011 << 4; // mode, 4FSK
|
||||
ADF7021_REG4 |= (uint32_t) 0b0 << 7;
|
||||
ADF7021_REG4 |= (uint32_t) 0b11 << 8;
|
||||
ADF7021_REG4 |= (uint32_t) ADF7021_DISC_BW_YSF << 10; // Disc BW
|
||||
ADF7021_REG4 |= (uint32_t) ADF7021_POST_BW_YSF << 20; // Post dem BW
|
||||
ADF7021_REG4 |= (uint32_t) 0b10 << 30; // IF filter
|
||||
|
||||
ADF7021_REG13 = 0x000003BD;
|
||||
ADF7021_REG13 = (uint32_t) 0b1101 << 0; // register 13
|
||||
ADF7021_REG13 |= (uint32_t) ADF7021_SLICER_TH_YSF << 4; // slicer threshold
|
||||
|
||||
ADF7021_REG2 = (uint32_t)0b10 << 28; // invert data
|
||||
ADF7021_REG2 |= (uint32_t)32U << 19; // deviation
|
||||
ADF7021_REG2 |= (uint32_t)0b111 << 4; // modulation (4FSK)
|
||||
ADF7021_REG2 = (uint32_t) 0b10 << 28; // invert data
|
||||
ADF7021_REG2 |= (uint32_t) ADF7021_DEV_YSF << 19; // deviation
|
||||
ADF7021_REG2 |= (uint32_t) 0b111 << 4; // modulation (4FSK)
|
||||
}
|
||||
else if (m_p25Enable) {
|
||||
// Dev: +1 symb 600 Hz, symb rate = 4800
|
||||
|
||||
ADF7021_REG3 = 0x2A4C80D3;
|
||||
ADF7021_REG3 = ADF7021_REG3_P25;
|
||||
|
||||
// K=32
|
||||
ADF7021_REG4 = (uint32_t)0b0100 << 0; // register 4
|
||||
ADF7021_REG4 |= (uint32_t)0b011 << 4; // mode, 4FSK
|
||||
ADF7021_REG4 |= (uint32_t)0b0 << 7;
|
||||
ADF7021_REG4 |= (uint32_t)0b11 << 8;
|
||||
ADF7021_REG4 |= (uint32_t)393U << 10; // Disc BW
|
||||
ADF7021_REG4 |= (uint32_t)65U << 20; // Post dem BW
|
||||
ADF7021_REG4 |= (uint32_t)0b10 << 30; // IF filter
|
||||
ADF7021_REG4 = (uint32_t) 0b0100 << 0; // register 4
|
||||
ADF7021_REG4 |= (uint32_t) 0b011 << 4; // mode, 4FSK
|
||||
ADF7021_REG4 |= (uint32_t) 0b0 << 7;
|
||||
ADF7021_REG4 |= (uint32_t) 0b11 << 8;
|
||||
ADF7021_REG4 |= (uint32_t) ADF7021_DISC_BW_P25 << 10; // Disc BW
|
||||
ADF7021_REG4 |= (uint32_t) ADF7021_POST_BW_P25 << 20; // Post dem BW
|
||||
ADF7021_REG4 |= (uint32_t) 0b10 << 30; // IF filter
|
||||
|
||||
ADF7021_REG13 = 0x000002DD;
|
||||
ADF7021_REG13 = (uint32_t) 0b1101 << 0; // register 13
|
||||
ADF7021_REG13 |= (uint32_t) ADF7021_SLICER_TH_P25 << 4; // slicer threshold
|
||||
|
||||
ADF7021_REG2 = (uint32_t)0b10 << 28; // invert data
|
||||
ADF7021_REG2 |= (uint32_t)22U << 19; // deviation
|
||||
ADF7021_REG2 |= (uint32_t)0b111 << 4; // modulation (4FSK)
|
||||
ADF7021_REG2 = (uint32_t) 0b10 << 28; // invert data
|
||||
ADF7021_REG2 |= (uint32_t) ADF7021_DEV_P25 << 19; // deviation
|
||||
ADF7021_REG2 |= (uint32_t) 0b111 << 4; // modulation (4FSK)
|
||||
}
|
||||
|
||||
// VCO/OSCILLATOR (REG1)
|
||||
if( (m_frequency_tx >= VHF_MIN) && (m_frequency_tx < VHF_MAX) )
|
||||
AD7021_control_byte = 0x021F5041; // VHF, external VCO
|
||||
AD7021_control_byte = ADF7021_REG1_VHF; // VHF, external VCO
|
||||
else if( (m_frequency_tx >= UHF_MIN)&&(m_frequency_tx < UHF_MAX) )
|
||||
AD7021_control_byte = 0x00575041; // UHF, internal VCO
|
||||
AD7021_control_byte = ADF7021_REG1_UHF; // UHF, internal VCO
|
||||
|
||||
Send_AD7021_control();
|
||||
|
||||
|
|
@ -192,13 +205,13 @@ void CIO::ifConf()
|
|||
Send_AD7021_control();
|
||||
|
||||
// IF FILTER (5)
|
||||
AD7021_control_byte = 0x000024F5;
|
||||
AD7021_control_byte = ADF7021_REG5;
|
||||
Send_AD7021_control();
|
||||
|
||||
// MODULATION (2)
|
||||
ADF7021_REG2 |= (uint32_t)0b0010; // register 2
|
||||
ADF7021_REG2 |= (uint32_t)m_power << 13; // power level
|
||||
ADF7021_REG2 |= (uint32_t)0b110001 << 7; // PA
|
||||
ADF7021_REG2 |= (uint32_t) 0b0010; // register 2
|
||||
ADF7021_REG2 |= (uint32_t) m_power << 13; // power level
|
||||
ADF7021_REG2 |= (uint32_t) 0b110001 << 7; // PA
|
||||
AD7021_control_byte = ADF7021_REG2;
|
||||
Send_AD7021_control();
|
||||
|
||||
|
|
@ -207,15 +220,15 @@ void CIO::ifConf()
|
|||
Send_AD7021_control();
|
||||
|
||||
// IF FINE CAL (fine cal, defaults) (6)
|
||||
AD7021_control_byte = 0x05080B16;
|
||||
AD7021_control_byte = ADF7021_REG6;
|
||||
Send_AD7021_control();
|
||||
|
||||
// AGC (auto, defaults) (9)
|
||||
AD7021_control_byte = 0x000231E9; // auto
|
||||
AD7021_control_byte = 0x000231E9;
|
||||
Send_AD7021_control();
|
||||
|
||||
// AFC (off, defaults) (10)
|
||||
AD7021_control_byte = 0x3296472A; // off
|
||||
AD7021_control_byte = ADF7021_REG10;
|
||||
Send_AD7021_control();
|
||||
|
||||
// SYNC WORD DET (11)
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue