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Adding 19.68 MHz TCXO support

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This commit is contained in:
Andy CA6JAU 2017-02-05 18:48:55 -03:00
parent 7d6d179846
commit d71b7aa053
4 changed files with 186 additions and 67 deletions
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135
ADF7021.cpp
View file

@ -22,7 +22,7 @@
#include "Config.h"
#if defined(ADF7021)
#if defined(ENABLE_ADF7021)
#include "Globals.h"
#include "IO.h"
@ -67,8 +67,8 @@ void Send_REG0_RX()
ADF7021_RX_REG0 = (uint32_t)0b0000;
ADF7021_RX_REG0 |= (uint32_t)0b01011 << 27; // mux regulator/uart enabled/receive
ADF7021_RX_REG0 |= (uint32_t)N_divider << 19; //frequency;
ADF7021_RX_REG0 |= (uint32_t)F_divider << 4; //frequency;
ADF7021_RX_REG0 |= (uint32_t)N_divider << 19; // frequency;
ADF7021_RX_REG0 |= (uint32_t)F_divider << 4; // frequency;
AD7021_control_byte = ADF7021_RX_REG0;
Send_AD7021_control();
@ -87,10 +87,10 @@ void Send_REG0_TX()
divider = (divider - N_divider) * 32768;
F_divider = floor(divider + 0.5);
ADF7021_TX_REG0 = (uint32_t)0b0000; // register 0
ADF7021_TX_REG0 |= (uint32_t)0b01010 << 27; // mux regulator/uart enabled/transmit
ADF7021_TX_REG0 |= (uint32_t)N_divider << 19; //frequency;
ADF7021_TX_REG0 |= (uint32_t)F_divider << 4; //frequency;
ADF7021_TX_REG0 = (uint32_t) 0b0000; // register 0
ADF7021_TX_REG0 |= (uint32_t) 0b01010 << 27; // mux regulator/uart enabled/transmit
ADF7021_TX_REG0 |= (uint32_t) N_divider << 19; // frequency;
ADF7021_TX_REG0 |= (uint32_t) F_divider << 4; // frequency;
AD7021_control_byte = ADF7021_TX_REG0;
Send_AD7021_control();
@ -98,88 +98,101 @@ void Send_REG0_TX()
void CIO::ifConf()
{
uint32_t ADF7021_REG2 = 0;
uint32_t ADF7021_REG3 = 0;
uint32_t ADF7021_REG4 = 0;
uint32_t ADF7021_REG2 = 0;
uint32_t ADF7021_REG3 = 0;
uint32_t ADF7021_REG4 = 0;
uint32_t ADF7021_REG13 = 0;
if (m_dstarEnable) {
// Dev: 1200 Hz, symb rate = 4800
ADF7021_REG3 = 0x2A4C4193;
ADF7021_REG4 = 0x00A82A94;
ADF7021_REG13 = 0x0000000D;
ADF7021_REG3 = ADF7021_REG3_DSTAR;
// K=32
ADF7021_REG4 = (uint32_t) 0b0100 << 0; // register 4
ADF7021_REG4 |= (uint32_t) 0b001 << 4; // mode, GMSK
ADF7021_REG4 |= (uint32_t) 0b1 << 7;
ADF7021_REG4 |= (uint32_t) 0b10 << 8;
ADF7021_REG4 |= (uint32_t) ADF7021_DISC_BW_DSTAR << 10; // Disc BW
ADF7021_REG4 |= (uint32_t) ADF7021_POST_BW_DSTAR << 20; // Post dem BW
ADF7021_REG4 |= (uint32_t) 0b00 << 30; // IF filter
ADF7021_REG2 = (uint32_t)0b00 << 28; // clock normal
ADF7021_REG2 |= (uint32_t)0b000101010 << 19; // deviation
ADF7021_REG2 |= (uint32_t)0b001 << 4; // modulation (GMSK)
ADF7021_REG13 = (uint32_t) 0b1101 << 0; // register 13
ADF7021_REG13 |= (uint32_t) ADF7021_SLICER_TH_DSTAR << 4; // slicer threshold
ADF7021_REG2 = (uint32_t) 0b00 << 28; // clock normal
ADF7021_REG2 |= (uint32_t) ADF7021_DEV_DSTAR << 19; // deviation
ADF7021_REG2 |= (uint32_t) 0b001 << 4; // modulation (GMSK)
}
else if (m_dmrEnable) {
// Dev: +1 symb 648 Hz, symb rate = 4800
ADF7021_REG3 = 0x2A4C80D3;
ADF7021_REG3 = ADF7021_REG3_DMR;
// K=32
ADF7021_REG4 = (uint32_t)0b0100 << 0; // register 4
ADF7021_REG4 |= (uint32_t)0b011 << 4; // mode, 4FSK
ADF7021_REG4 |= (uint32_t)0b0 << 7;
ADF7021_REG4 |= (uint32_t)0b11 << 8;
ADF7021_REG4 |= (uint32_t)393U << 10; // Disc BW
ADF7021_REG4 |= (uint32_t)65U << 20; // Post dem BW
ADF7021_REG4 |= (uint32_t)0b10 << 30; // IF filter
ADF7021_REG4 = (uint32_t) 0b0100 << 0; // register 4
ADF7021_REG4 |= (uint32_t) 0b011 << 4; // mode, 4FSK
ADF7021_REG4 |= (uint32_t) 0b0 << 7;
ADF7021_REG4 |= (uint32_t) 0b11 << 8;
ADF7021_REG4 |= (uint32_t) ADF7021_DISC_BW_DMR << 10; // Disc BW
ADF7021_REG4 |= (uint32_t) ADF7021_POST_BW_DMR << 20; // Post dem BW
ADF7021_REG4 |= (uint32_t) 0b10 << 30; // IF filter
ADF7021_REG13 = 0x0000033D;
ADF7021_REG13 = (uint32_t) 0b1101 << 0; // register 13
ADF7021_REG13 |= (uint32_t) ADF7021_SLICER_TH_DMR << 4; // slicer threshold
ADF7021_REG2 = (uint32_t)0b10 << 28; // invert data
ADF7021_REG2 |= (uint32_t)24U << 19; // deviation
ADF7021_REG2 |= (uint32_t)0b111 << 4; // modulation (4FSK)
ADF7021_REG2 = (uint32_t) 0b10 << 28; // invert data
ADF7021_REG2 |= (uint32_t) ADF7021_DEV_DMR << 19; // deviation
ADF7021_REG2 |= (uint32_t) 0b111 << 4; // modulation (4FSK)
}
else if (m_ysfEnable) {
// Dev: +1 symb 900 Hz, symb rate = 4800
ADF7021_REG3 = 0x2A4C80D3;
ADF7021_REG3 = ADF7021_REG3_YSF;
// K=28
ADF7021_REG4 = (uint32_t)0b0100 << 0; // register 4
ADF7021_REG4 |= (uint32_t)0b011 << 4; // mode, 4FSK
ADF7021_REG4 |= (uint32_t)0b0 << 7;
ADF7021_REG4 |= (uint32_t)0b11 << 8;
ADF7021_REG4 |= (uint32_t)344U << 10; // Disc BW
ADF7021_REG4 |= (uint32_t)65U << 20; // Post dem BW
ADF7021_REG4 |= (uint32_t)0b10 << 30; // IF filter
ADF7021_REG4 = (uint32_t) 0b0100 << 0; // register 4
ADF7021_REG4 |= (uint32_t) 0b011 << 4; // mode, 4FSK
ADF7021_REG4 |= (uint32_t) 0b0 << 7;
ADF7021_REG4 |= (uint32_t) 0b11 << 8;
ADF7021_REG4 |= (uint32_t) ADF7021_DISC_BW_YSF << 10; // Disc BW
ADF7021_REG4 |= (uint32_t) ADF7021_POST_BW_YSF << 20; // Post dem BW
ADF7021_REG4 |= (uint32_t) 0b10 << 30; // IF filter
ADF7021_REG13 = 0x000003BD;
ADF7021_REG13 = (uint32_t) 0b1101 << 0; // register 13
ADF7021_REG13 |= (uint32_t) ADF7021_SLICER_TH_YSF << 4; // slicer threshold
ADF7021_REG2 = (uint32_t)0b10 << 28; // invert data
ADF7021_REG2 |= (uint32_t)32U << 19; // deviation
ADF7021_REG2 |= (uint32_t)0b111 << 4; // modulation (4FSK)
ADF7021_REG2 = (uint32_t) 0b10 << 28; // invert data
ADF7021_REG2 |= (uint32_t) ADF7021_DEV_YSF << 19; // deviation
ADF7021_REG2 |= (uint32_t) 0b111 << 4; // modulation (4FSK)
}
else if (m_p25Enable) {
// Dev: +1 symb 600 Hz, symb rate = 4800
ADF7021_REG3 = 0x2A4C80D3;
ADF7021_REG3 = ADF7021_REG3_P25;
// K=32
ADF7021_REG4 = (uint32_t)0b0100 << 0; // register 4
ADF7021_REG4 |= (uint32_t)0b011 << 4; // mode, 4FSK
ADF7021_REG4 |= (uint32_t)0b0 << 7;
ADF7021_REG4 |= (uint32_t)0b11 << 8;
ADF7021_REG4 |= (uint32_t)393U << 10; // Disc BW
ADF7021_REG4 |= (uint32_t)65U << 20; // Post dem BW
ADF7021_REG4 |= (uint32_t)0b10 << 30; // IF filter
ADF7021_REG4 = (uint32_t) 0b0100 << 0; // register 4
ADF7021_REG4 |= (uint32_t) 0b011 << 4; // mode, 4FSK
ADF7021_REG4 |= (uint32_t) 0b0 << 7;
ADF7021_REG4 |= (uint32_t) 0b11 << 8;
ADF7021_REG4 |= (uint32_t) ADF7021_DISC_BW_P25 << 10; // Disc BW
ADF7021_REG4 |= (uint32_t) ADF7021_POST_BW_P25 << 20; // Post dem BW
ADF7021_REG4 |= (uint32_t) 0b10 << 30; // IF filter
ADF7021_REG13 = 0x000002DD;
ADF7021_REG13 = (uint32_t) 0b1101 << 0; // register 13
ADF7021_REG13 |= (uint32_t) ADF7021_SLICER_TH_P25 << 4; // slicer threshold
ADF7021_REG2 = (uint32_t)0b10 << 28; // invert data
ADF7021_REG2 |= (uint32_t)22U << 19; // deviation
ADF7021_REG2 |= (uint32_t)0b111 << 4; // modulation (4FSK)
ADF7021_REG2 = (uint32_t) 0b10 << 28; // invert data
ADF7021_REG2 |= (uint32_t) ADF7021_DEV_P25 << 19; // deviation
ADF7021_REG2 |= (uint32_t) 0b111 << 4; // modulation (4FSK)
}
// VCO/OSCILLATOR (REG1)
if( (m_frequency_tx >= VHF_MIN) && (m_frequency_tx < VHF_MAX) )
AD7021_control_byte = 0x021F5041; // VHF, external VCO
AD7021_control_byte = ADF7021_REG1_VHF; // VHF, external VCO
else if( (m_frequency_tx >= UHF_MIN)&&(m_frequency_tx < UHF_MAX) )
AD7021_control_byte = 0x00575041; // UHF, internal VCO
AD7021_control_byte = ADF7021_REG1_UHF; // UHF, internal VCO
Send_AD7021_control();
@ -192,13 +205,13 @@ void CIO::ifConf()
Send_AD7021_control();
// IF FILTER (5)
AD7021_control_byte = 0x000024F5;
AD7021_control_byte = ADF7021_REG5;
Send_AD7021_control();
// MODULATION (2)
ADF7021_REG2 |= (uint32_t)0b0010; // register 2
ADF7021_REG2 |= (uint32_t)m_power << 13; // power level
ADF7021_REG2 |= (uint32_t)0b110001 << 7; // PA
ADF7021_REG2 |= (uint32_t) 0b0010; // register 2
ADF7021_REG2 |= (uint32_t) m_power << 13; // power level
ADF7021_REG2 |= (uint32_t) 0b110001 << 7; // PA
AD7021_control_byte = ADF7021_REG2;
Send_AD7021_control();
@ -207,15 +220,15 @@ void CIO::ifConf()
Send_AD7021_control();
// IF FINE CAL (fine cal, defaults) (6)
AD7021_control_byte = 0x05080B16;
AD7021_control_byte = ADF7021_REG6;
Send_AD7021_control();
// AGC (auto, defaults) (9)
AD7021_control_byte = 0x000231E9; // auto
AD7021_control_byte = 0x000231E9;
Send_AD7021_control();
// AFC (off, defaults) (10)
AD7021_control_byte = 0x3296472A; // off
AD7021_control_byte = ADF7021_REG10;
Send_AD7021_control();
// SYNC WORD DET (11)

106
ADF7021.h
View file

@ -25,9 +25,111 @@
#include "Config.h"
#if defined(ADF7021)
#if defined(ENABLE_ADF7021)
#define ADF7021_PFD 3686400.0
/*
- Most of the registers values are obteined from ADI eval software:
http://www.analog.com/en/products/rf-microwave/integrated-transceivers-transmitters-receivers/low-power-rf-transceivers/adf7021.html
- or ADF7021 datasheet formulas:
www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
*/
#define ADF7021_REG1_VHF 0x021F5041
#define ADF7021_REG1_UHF 0x00575041
/****** Support for 14.7456 MHz TCXO (modified RF7021SE boards) ******/
#if defined(ADF7021_14_7456)
// R = 4
#define ADF7021_PFD 3686400.0
// Deviation of modulator (REG 02)
#define ADF7021_DEV_DSTAR 42U
#define ADF7021_DEV_DMR 24U
#define ADF7021_DEV_YSF 32U
#define ADF7021_DEV_P25 22U
// TX/RX CLOCK register (REG 03)
#define ADF7021_REG3_DSTAR 0x2A4C4193
#define ADF7021_REG3_DMR 0x2A4C80D3
#define ADF7021_REG3_YSF 0x2A4C80D3
#define ADF7021_REG3_P25 0x2A4C80D3
// Discriminator bandwith, demodulator (REG 04)
// Bug in ADI evaluation software, use datasheet formula (4FSK)
#define ADF7021_DISC_BW_DSTAR 522U // K=85
#define ADF7021_DISC_BW_DMR 393U // K=32
#define ADF7021_DISC_BW_YSF 344U // K=28
#define ADF7021_DISC_BW_P25 393U // K=32
// Post demodulator bandwith (REG 04)
#define ADF7021_POST_BW_DSTAR 10U
#define ADF7021_POST_BW_DMR 65U
#define ADF7021_POST_BW_YSF 65U
#define ADF7021_POST_BW_P25 65U
// IF filter (REG 05)
#define ADF7021_REG5 0x000024F5
// IF CAL (fine cal, defaults) (REG 06)
#define ADF7021_REG6 0x05080B16
// AFC (off, defaults) (REG 10)
#define ADF7021_REG10 0x3296472A
// Slicer threshold for 4FSK demodulator (REG 13)
#define ADF7021_SLICER_TH_DSTAR 00U
#define ADF7021_SLICER_TH_DMR 51U
#define ADF7021_SLICER_TH_YSF 59U
#define ADF7021_SLICER_TH_P25 45U
/****** Support for 19.6800 MHz TCXO (original RF7021SE boards) ******/
#elif defined(ADF7021_19_6800)
// R = 4
#define ADF7021_PFD 4920000.0
// Deviation of modulator (REG 02)
#define ADF7021_DEV_DSTAR 32U
#define ADF7021_DEV_DMR 17U
#define ADF7021_DEV_YSF 24U
#define ADF7021_DEV_P25 16U
// TX/RX CLOCK register (REG 03)
#define ADF7021_REG3_DSTAR 0x2B1449E3
#define ADF7021_REG3_DMR 0x2B148123
#define ADF7021_REG3_YSF 0x2B148123
#define ADF7021_REG3_P25 0x2B148123
// Discriminator bandwith, demodulator (REG 04)
// Bug in ADI evaluation software, use datasheet formula (4FSK)
#define ADF7021_DISC_BW_DSTAR 583U // K=83
#define ADF7021_DISC_BW_DMR 397U // K=32
#define ADF7021_DISC_BW_YSF 347U // K=28
#define ADF7021_DISC_BW_P25 397U // K=32
// Post demodulator bandwith (REG 04)
#define ADF7021_POST_BW_DSTAR 09U
#define ADF7021_POST_BW_DMR 65U
#define ADF7021_POST_BW_YSF 65U
#define ADF7021_POST_BW_P25 65U
// IF filter (REG 05)
#define ADF7021_REG5 0x00003155
// IF CAL (coarse cal, defaults) (REG 06)
#define ADF7021_REG6 0x050972C6
// AFC (off, defaults) (REG 10)
#define ADF7021_REG10 0x3296354A
// Slicer threshold for 4FSK demodulator (REG 13)
#define ADF7021_SLICER_TH_DSTAR 00U
#define ADF7021_SLICER_TH_DMR 51U
#define ADF7021_SLICER_TH_YSF 59U
#define ADF7021_SLICER_TH_P25 45U
#endif
#define bitRead(value, bit) (((value) >> (bit)) & 0x01)

8
Config.h
View file

@ -20,13 +20,17 @@
#define CONFIG_H
// Enable ADF7021 support:
#define ADF7021
#define ENABLE_ADF7021
// TCXO of the ADF7021:
#define ADF7021_14_7456
// #define ADF7021_19_6800
// Host communication selection:
//#define STM32_USART1_HOST
#define STM32_USB_HOST
// Enable Nextion LCD serial port repeater:
#define SERIAL_REPEATER
//#define SERIAL_REPEATER
#endif

4
IO.cpp
View file

@ -103,11 +103,11 @@ void CIO::interrupt()
void CIO::start()
{
ifConf();
if (m_started)
return;
ifConf();
delay_rx();
setRX();