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Adding AFC support for all modes and improving register values
This commit is contained in:
Andy CA6JAU
parent
055d83fc7e
commit
c1ec2f6fca
11
ADF7021.cpp
11
ADF7021.cpp
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@ -140,6 +140,7 @@ void CIO::ifConf()
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uint32_t ADF7021_REG2 = 0;
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uint32_t ADF7021_REG3 = 0;
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uint32_t ADF7021_REG4 = 0;
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uint32_t ADF7021_REG10 = 0;
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uint32_t ADF7021_REG13 = 0;
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// Toggle CE pin for ADF7021 reset
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@ -214,6 +215,7 @@ void CIO::ifConf()
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// Dev: 1200 Hz, symb rate = 4800
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ADF7021_REG3 = ADF7021_REG3_DSTAR;
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ADF7021_REG10 = ADF7021_REG10_DSTAR;
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// K=32
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ADF7021_REG4 = (uint32_t) 0b0100 << 0; // register 4
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@ -235,6 +237,7 @@ void CIO::ifConf()
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// Dev: +1 symb 648 Hz, symb rate = 4800
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ADF7021_REG3 = ADF7021_REG3_DMR;
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ADF7021_REG10 = ADF7021_REG10_DMR;
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// K=32
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ADF7021_REG4 = (uint32_t) 0b0100 << 0; // register 4
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@ -256,6 +259,7 @@ void CIO::ifConf()
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// Dev: +1 symb 900 Hz, symb rate = 4800
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ADF7021_REG3 = ADF7021_REG3_YSF;
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ADF7021_REG10 = ADF7021_REG10_YSF;
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// K=28
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ADF7021_REG4 = (uint32_t) 0b0100 << 0; // register 4
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@ -277,6 +281,7 @@ void CIO::ifConf()
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// Dev: +1 symb 600 Hz, symb rate = 4800
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ADF7021_REG3 = ADF7021_REG3_P25;
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ADF7021_REG10 = ADF7021_REG10_P25;
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// K=32
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ADF7021_REG4 = (uint32_t) 0b0100 << 0; // register 4
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@ -311,6 +316,10 @@ void CIO::ifConf()
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AD7021_control_word = ADF7021_REG5;
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Send_AD7021_control();
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// Delay for coarse IF filter calibration
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delay_rx();
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delay_rx();
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// Frequency RX (0)
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setRX();
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@ -333,7 +342,7 @@ void CIO::ifConf()
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AD7021_control_word = 0x000231E9;
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Send_AD7021_control();
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// AFC (off, defaults) (10)
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// AFC (10)
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AD7021_control_word = ADF7021_REG10;
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Send_AD7021_control();
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71
ADF7021.h
71
ADF7021.h
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@ -61,30 +61,33 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
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// Discriminator bandwith, demodulator (REG 04)
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// Bug in ADI evaluation software, use datasheet formula (4FSK)
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#define ADF7021_DISC_BW_DSTAR 522U // K=85
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#define ADF7021_DISC_BW_DMR 393U // K=32
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#define ADF7021_DISC_BW_YSF 344U // K=28
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#define ADF7021_DISC_BW_P25 394U // K=32
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#define ADF7021_DISC_BW_DMR 392U // K=32
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#define ADF7021_DISC_BW_YSF 343U // K=28
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#define ADF7021_DISC_BW_P25 393U // K=32
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// Post demodulator bandwith (REG 04)
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#define ADF7021_POST_BW_DSTAR 10U
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#define ADF7021_POST_BW_DMR 65U
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#define ADF7021_POST_BW_YSF 15U
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#define ADF7021_POST_BW_YSF 20U
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#define ADF7021_POST_BW_P25 6U
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// IF filter (REG 05)
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#define ADF7021_REG5 0x000024F5
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// IF CAL (fine cal, defaults) (REG 06)
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#define ADF7021_REG6 0x05080B16
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#define ADF7021_REG6 0x05070E16
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// AFC (off, defaults) (REG 10)
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#define ADF7021_REG10 0x3296472A
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// AFC (on) (REG 10)
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#define ADF7021_REG10_DSTAR 0x0C96473A
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#define ADF7021_REG10_DMR 0x019E473A
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#define ADF7021_REG10_YSF 0x029E473A
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#define ADF7021_REG10_P25 0x029E473A
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// Slicer threshold for 4FSK demodulator (REG 13)
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#define ADF7021_SLICER_TH_DSTAR 0U
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#define ADF7021_SLICER_TH_DMR 51U
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#define ADF7021_SLICER_TH_YSF 75U
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#define ADF7021_SLICER_TH_P25 52U
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#define ADF7021_SLICER_TH_DMR 53U
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#define ADF7021_SLICER_TH_YSF 68U
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#define ADF7021_SLICER_TH_P25 46U
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/****** Support for 19.6800 MHz TCXO (original RF7021SE boards) ******/
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#elif defined(ADF7021_19_6800)
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@ -113,14 +116,14 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
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// Discriminator bandwith, demodulator (REG 04)
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// Bug in ADI evaluation software, use datasheet formula (4FSK)
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#define ADF7021_DISC_BW_DSTAR 597U // K=85
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#define ADF7021_DISC_BW_DMR 393U // K=32
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#define ADF7021_DISC_BW_YSF 344U // K=28
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#define ADF7021_DISC_BW_P25 394U // K=32
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#define ADF7021_DISC_BW_DMR 392U // K=32
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#define ADF7021_DISC_BW_YSF 343U // K=28
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#define ADF7021_DISC_BW_P25 393U // K=32
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// Post demodulator bandwith (REG 04)
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#define ADF7021_POST_BW_DSTAR 20U
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#define ADF7021_POST_BW_DSTAR 10U
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#define ADF7021_POST_BW_DMR 65U
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#define ADF7021_POST_BW_YSF 15U
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#define ADF7021_POST_BW_YSF 20U
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#define ADF7021_POST_BW_P25 6U
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// IF filter (REG 05)
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@ -129,14 +132,17 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
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// IF CAL (coarse cal, defaults) (REG 06)
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#define ADF7021_REG6 0x050972C6
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// AFC (off, defaults) (REG 10)
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#define ADF7021_REG10 0x3296354A
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// AFC (on) (REG 10)
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#define ADF7021_REG10_DSTAR 0x0C96355A
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#define ADF7021_REG10_DMR 0x019E355A
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#define ADF7021_REG10_YSF 0x029E355A
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#define ADF7021_REG10_P25 0x029E355A
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// Slicer threshold for 4FSK demodulator (REG 13)
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#define ADF7021_SLICER_TH_DSTAR 0U
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#define ADF7021_SLICER_TH_DMR 51U
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#define ADF7021_SLICER_TH_YSF 75U
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#define ADF7021_SLICER_TH_P25 52U
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#define ADF7021_SLICER_TH_DMR 53U
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#define ADF7021_SLICER_TH_YSF 68U
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#define ADF7021_SLICER_TH_P25 46U
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/****** Support for 12.2880 MHz TCXO ******/
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#elif defined(ADF7021_12_2880)
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@ -165,15 +171,15 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
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// Discriminator bandwith, demodulator (REG 04)
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// Bug in ADI evaluation software, use datasheet formula (4FSK)
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#define ADF7021_DISC_BW_DSTAR 522U // K=85
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#define ADF7021_DISC_BW_DMR 491U // K=32
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#define ADF7021_DISC_BW_YSF 430U // K=28
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#define ADF7021_DISC_BW_P25 493U // K=32
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#define ADF7021_DISC_BW_DMR 490U // K=32
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#define ADF7021_DISC_BW_YSF 429U // K=28
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#define ADF7021_DISC_BW_P25 491U // K=32
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// Post demodulator bandwith (REG 04)
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#define ADF7021_POST_BW_DSTAR 20U
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#define ADF7021_POST_BW_DSTAR 10U
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#define ADF7021_POST_BW_DMR 65U
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#define ADF7021_POST_BW_YSF 15U
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#define ADF7021_POST_BW_P25 7U
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#define ADF7021_POST_BW_YSF 20U
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#define ADF7021_POST_BW_P25 6U
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// IF filter (REG 05)
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#define ADF7021_REG5 0x00001ED5
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@ -181,14 +187,17 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
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// IF CAL (fine cal, defaults) (REG 06)
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#define ADF7021_REG6 0x0505EBB6
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// AFC (off, defaults) (REG 10)
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#define ADF7021_REG10 0x3296556A
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// AFC (on, defaults) (REG 10)
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#define ADF7021_REG10_DSTAR 0x0C96557A
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#define ADF7021_REG10_DMR 0x019E557A
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#define ADF7021_REG10_YSF 0x029E557A
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#define ADF7021_REG10_P25 0x029E557A
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// Slicer threshold for 4FSK demodulator (REG 13)
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#define ADF7021_SLICER_TH_DSTAR 0U
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#define ADF7021_SLICER_TH_DMR 51U
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#define ADF7021_SLICER_TH_YSF 75U
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#define ADF7021_SLICER_TH_P25 52U
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#define ADF7021_SLICER_TH_DMR 53U
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#define ADF7021_SLICER_TH_YSF 68U
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#define ADF7021_SLICER_TH_P25 46U
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#endif
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