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New registers values for DMR and YSF (14.7456 MHz)

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This commit is contained in:
Andy CA6JAU 2017-04-28 23:20:13 -03:00
parent e1c5e0b13a
commit bd759e04fb
2 changed files with 16 additions and 14 deletions
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2
ADF7021.cpp
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@ -305,7 +305,7 @@ void CIO::ifConf(MMDVM_STATE modemState, bool reset)
case STATE_YSF:
// Dev: +1 symb 900 Hz, symb rate = 4800
ADF7021_REG3 = ADF7021_REG3_YSF;
ADF7021_REG3 = (m_LoDevYSF ? ADF7021_REG3_YSF_L : ADF7021_REG3_YSF_H);
ADF7021_REG10 = ADF7021_REG10_YSF;
// K=28

28
ADF7021.h
View file

@ -47,8 +47,8 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
// R = 4
// DEMOD_CLK = 2.4576 MHz (DSTAR)
// DEMOD_CLK = 4.9152 MHz (DMR, P25)
// DEMOD_CLK = 7.3728 MHz (YSF)
// DEMOD_CLK = 4.9152 MHz (DMR, YSF_L, P25)
// DEMOD_CLK = 7.3728 MHz (YSF_H)
#define ADF7021_PFD 3686400.0
// PLL (REG 01)
@ -68,12 +68,13 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
#define ADF7021_REG3_DSTAR 0x2A4C4193
#if defined(TEST_DAC)
#define ADF7021_REG3_DMR 0x2A4C04D3
#define ADF7021_REG3_YSF 0x2A4C04D3
#define ADF7021_REG3_YSF_L 0x2A4C04D3
#define ADF7021_REG3_YSF_H 0x2A4C0493
#define ADF7021_REG3_P25 0x2A4C04D3
#else
#define ADF7021_REG3_DMR 0x2A4C80D3
//#define ADF7021_REG3_YSF 0x2A4C80D3
#define ADF7021_REG3_YSF 0x2A4CC093
#define ADF7021_REG3_YSF_L 0x2A4C80D3
#define ADF7021_REG3_YSF_H 0x2A4CC093
#define ADF7021_REG3_P25 0x2A4C80D3
#endif
@ -81,15 +82,14 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
// Bug in ADI evaluation software, use datasheet formula (4FSK)
#define ADF7021_DISC_BW_DSTAR 522U // K=85
#define ADF7021_DISC_BW_DMR 393U // K=32
#define ADF7021_DISC_BW_YSF_L 394U // K=32
//#define ADF7021_DISC_BW_YSF_H 344U // K=28
#define ADF7021_DISC_BW_YSF_L 393U // K=32
#define ADF7021_DISC_BW_YSF_H 516U // K=28
#define ADF7021_DISC_BW_P25 394U // K=32
// Post demodulator bandwith (REG 04)
#define ADF7021_POST_BW_DSTAR 10U
#define ADF7021_POST_BW_DMR 150U
#define ADF7021_POST_BW_YSF 15U
#define ADF7021_POST_BW_YSF 20U
#define ADF7021_POST_BW_P25 6U
// IF filter (REG 05)
@ -128,8 +128,8 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
// R = 2
// DEMOD_CLK = 2.4576 MHz (DSTAR)
// DEMOD_CLK = 4.0960 MHz (DMR, P25)
// DEMOD_CLK = 6.1440 MHz (YSF)
// DEMOD_CLK = 4.0960 MHz (DMR, YSF_L, P25)
// DEMOD_CLK = 6.1440 MHz (YSF_H)
#define ADF7021_PFD 6144000.0
// PLL (REG 01)
@ -149,11 +149,13 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
#define ADF7021_REG3_DSTAR 0x29EC4153
#if defined(TEST_DAC)
#define ADF7021_REG3_DMR 0x29EC0493
#define ADF7021_REG3_YSF 0x29EC0493
#define ADF7021_REG3_YSF_L 0x29EC0493
#define ADF7021_REG3_YSF_H 0x29EC0493
#define ADF7021_REG3_P25 0x29EC0493
#else
#define ADF7021_REG3_DMR 0x29ECA093
#define ADF7021_REG3_YSF 0x29ECA093
#define ADF7021_REG3_YSF_L 0x29ECA093
#define ADF7021_REG3_YSF_H 0x29ECA093
#define ADF7021_REG3_P25 0x29ECA093
#endif
@ -167,7 +169,7 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
// Post demodulator bandwith (REG 04)
#define ADF7021_POST_BW_DSTAR 10U
#define ADF7021_POST_BW_DMR 100U
#define ADF7021_POST_BW_DMR 150U
#define ADF7021_POST_BW_YSF 20U
#define ADF7021_POST_BW_P25 6U