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Moving specific ADF7021 code to ADF7021.cpp
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parent
99eb2fa11a
commit
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5 changed files with 141 additions and 151 deletions
132
ADF7021.cpp
132
ADF7021.cpp
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@ -29,6 +29,11 @@
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#include "ADF7021.h"
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#include <math.h>
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volatile bool totx_request = false;
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volatile bool torx_request = false;
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volatile bool even = true;
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static uint32_t last_clk = 2;
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volatile uint32_t AD7021_control_word;
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uint32_t ADF7021_RX_REG0;
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@ -162,9 +167,9 @@ void CIO::ifConf(MMDVM_STATE modemState, bool reset)
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// Toggle CE pin for ADF7021 reset
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if(reset) {
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CE_pin(LOW);
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delay_rx();
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delay_reset();
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CE_pin(HIGH);
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delay_rx();
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delay_reset();
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}
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// Check frequency band
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@ -360,9 +365,7 @@ void CIO::ifConf(MMDVM_STATE modemState, bool reset)
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Send_AD7021_control();
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// Delay for coarse IF filter calibration
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delay_rx();
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delay_rx();
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delay_rx();
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delay_ifcal_coarse();
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// Frequency RX (0)
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setRX();
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@ -400,6 +403,117 @@ void CIO::ifConf(MMDVM_STATE modemState, bool reset)
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}
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void CIO::interrupt()
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{
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uint8_t bit = 0;
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if (!m_started)
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return;
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uint8_t clk = CLK_pin();
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// this is to prevent activation by spurious interrupts
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// which seem to happen if you send out an control word
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// needs investigation
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// this workaround will fail if only rising or falling edge
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// is used to trigger the interrupt !!!!
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// TODO: figure out why sending the control word seems to issue interrupts
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// possibly this is a design problem of the RF7021 board or too long wires
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// on the breadboard build
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// but normally this will not hurt too much
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if (clk == last_clk) {
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return;
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} else {
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last_clk = clk;
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}
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// we set the TX bit at TXD low, sampling of ADF7021 happens at rising clock
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if (m_tx && clk == 0) {
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m_txBuffer.get(bit);
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even = !even;
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// use this for tracking issues
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// P25_pin(even);
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#if defined(BIDIR_DATA_PIN)
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if(bit)
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RXD_pin_write(HIGH);
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else
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RXD_pin_write(LOW);
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#else
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if(bit)
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TXD_pin(HIGH);
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else
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TXD_pin(LOW);
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#endif
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// wait a brief period before raising SLE
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if (totx_request == true) {
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asm volatile("nop \n\t"
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"nop \n\t"
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"nop \n\t"
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);
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// SLE Pulse, should be moved out of here into class method
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// according to datasheet in 4FSK we have to deliver this before 1/4 tbit == 26uS
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SLE_pin(HIGH);
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asm volatile("nop \n\t"
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"nop \n\t"
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"nop \n\t"
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);
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SLE_pin(LOW);
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SDATA_pin(LOW);
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// now do housekeeping
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totx_request = false;
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// first tranmittted bit is always the odd bit
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even = false;
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}
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}
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// we sample the RX bit at rising TXD clock edge, so TXD must be 1 and we are not in tx mode
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if (!m_tx && clk == 1) {
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if(RXD_pin())
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bit = 1;
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else
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bit = 0;
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m_rxBuffer.put(bit);
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}
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if (torx_request == true && even == false && m_tx && clk == 0) {
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// that is absolutely crucial in 4FSK, see datasheet:
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// enable sle after 1/4 tBit == 26uS when sending MSB (even == false) and clock is low
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delay_us(26);
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// SLE Pulse, should be moved out of here into class method
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SLE_pin(HIGH);
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asm volatile("nop \n\t"
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"nop \n\t"
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"nop \n\t"
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);
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SLE_pin(LOW);
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SDATA_pin(LOW);
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// now do housekeeping
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m_tx = false;
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torx_request = false;
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//last tranmittted bit is always the even bit
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// since the current bit is a transitional "don't care" bit, never transmitted
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even = true;
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}
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m_watchdog++;
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m_modeTimerCnt++;
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if(m_scanPauseCnt >= SCAN_PAUSE)
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m_scanPauseCnt = 0;
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if(m_scanPauseCnt != 0)
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m_scanPauseCnt++;
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}
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//======================================================================================================================
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void CIO::setTX()
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{
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@ -416,6 +530,8 @@ void CIO::setTX()
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Data_dir_out(true); // Data pin output mode
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#endif
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totx_request = true;
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while(CLK_pin());
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}
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//======================================================================================================================
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@ -432,7 +548,11 @@ void CIO::setRX(bool doSle)
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#if defined(BIDIR_DATA_PIN)
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Data_dir_out(false); // Data pin input mode
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#endif
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if(!doSle) {
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torx_request = true;
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while(torx_request) { asm volatile ("nop"); }
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}
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}
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void CIO::setLoDevYSF(bool on)
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