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Fix YSF +1 sym deviation to 900 Hz (according to standard), and fix deviation values for 12.288 MHz TCXO

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This commit is contained in:
Andy CA6JAU 2017-08-20 20:49:56 -03:00
parent 92d9844f64
commit 6df168a17d
1 changed files with 6 additions and 6 deletions
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12
ADF7021.h
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@ -77,8 +77,8 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
// Deviation of modulator (REG 02)
#define ADF7021_DEV_DSTAR 43U
#define ADF7021_DEV_DMR 23U
#define ADF7021_DEV_YSF_L 18U
#define ADF7021_DEV_YSF_H 36U
#define ADF7021_DEV_YSF_L 16U
#define ADF7021_DEV_YSF_H 32U
#if defined(ENABLE_P25_WIDE)
#define ADF7021_DEV_P25 32U
#else
@ -161,12 +161,12 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
// Deviation of modulator (REG 02)
#define ADF7021_DEV_DSTAR 26U
#define ADF7021_DEV_DMR 14U
#define ADF7021_DEV_YSF_L 11U
#define ADF7021_DEV_YSF_H 21U
#define ADF7021_DEV_YSF_L 10U
#define ADF7021_DEV_YSF_H 19U
#if defined(ENABLE_P25_WIDE)
#define ADF7021_DEV_P25 21U
#define ADF7021_DEV_P25 19U
#else
#define ADF7021_DEV_P25 14U
#define ADF7021_DEV_P25 13U
#endif
// TX/RX CLOCK register (REG 03)