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https://github.com/g4klx/MMDVM_HS.git
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Adding Jonathan support for low deviation in YSF
This commit is contained in:
Andy CA6JAU
parent
2f442f7ddf
commit
4f293ee84f
11
ADF7021.cpp
11
ADF7021.cpp
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@ -276,15 +276,15 @@ void CIO::ifConf()
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ADF7021_REG4 |= (uint32_t) 0b011 << 4; // mode, 4FSK
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ADF7021_REG4 |= (uint32_t) 0b0 << 7;
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ADF7021_REG4 |= (uint32_t) 0b11 << 8;
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ADF7021_REG4 |= (uint32_t) ADF7021_DISC_BW_YSF << 10; // Disc BW
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ADF7021_REG4 |= (uint32_t) (m_LoDevYSF ? ADF7021_DISC_BW_YSF_L : ADF7021_DISC_BW_YSF_H) << 10; // Disc BW
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ADF7021_REG4 |= (uint32_t) ADF7021_POST_BW_YSF << 20; // Post dem BW
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ADF7021_REG4 |= (uint32_t) 0b10 << 30; // IF filter
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ADF7021_REG13 = (uint32_t) 0b1101 << 0; // register 13
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ADF7021_REG13 |= (uint32_t) ADF7021_SLICER_TH_YSF << 4; // slicer threshold
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ADF7021_REG13 |= (uint32_t) (m_LoDevYSF ? ADF7021_SLICER_TH_YSF_L : ADF7021_SLICER_TH_YSF_H) << 4; // slicer threshold
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ADF7021_REG2 = (uint32_t) 0b10 << 28; // invert data
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ADF7021_REG2 |= (uint32_t) (ADF7021_DEV_YSF / div2) << 19; // deviation
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ADF7021_REG2 |= (uint32_t) ((m_LoDevYSF ? ADF7021_DEV_YSF_L : ADF7021_DEV_YSF_H) / div2) << 19; // deviation
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ADF7021_REG2 |= (uint32_t) 0b111 << 4; // modulation (4FSK)
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}
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else if (m_p25Enable) {
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@ -398,4 +398,9 @@ void CIO::setRX()
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PTT_pin(LOW);
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}
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void CIO::setLoDevYSF(bool on)
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{
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m_LoDevYSF = on;
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}
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#endif
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57
ADF7021.h
57
ADF7021.h
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@ -49,11 +49,8 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
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// Deviation of modulator (REG 02)
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#define ADF7021_DEV_DSTAR 43U
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#define ADF7021_DEV_DMR 23U
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#if defined(ADF7021_YSF_HALF_DEV)
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#define ADF7021_DEV_YSF 16U
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#else
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#define ADF7021_DEV_YSF 32U
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#endif
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#define ADF7021_DEV_YSF_L 16U
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#define ADF7021_DEV_YSF_H 32U
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#define ADF7021_DEV_P25 22U
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// TX/RX CLOCK register (REG 03)
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@ -66,11 +63,8 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
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// Bug in ADI evaluation software, use datasheet formula (4FSK)
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#define ADF7021_DISC_BW_DSTAR 522U // K=85
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#define ADF7021_DISC_BW_DMR 393U // K=32
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#if defined(ADF7021_YSF_HALF_DEV)
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#define ADF7021_DISC_BW_YSF 394U // K=32
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#else
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#define ADF7021_DISC_BW_YSF 344U // K=28
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#endif
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#define ADF7021_DISC_BW_YSF_L 394U // K=32
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#define ADF7021_DISC_BW_YSF_H 344U // K=28
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#define ADF7021_DISC_BW_P25 394U // K=32
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// Post demodulator bandwith (REG 04)
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@ -125,11 +119,8 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
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// Deviation of modulator (REG 02)
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#define ADF7021_DEV_DSTAR 32U
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#define ADF7021_DEV_DMR 17U
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#if defined(ADF7021_YSF_HALF_DEV)
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#define ADF7021_DEV_YSF 12U
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#else
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#define ADF7021_DEV_YSF 24U
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#endif
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#define ADF7021_DEV_YSF_L 12U
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#define ADF7021_DEV_YSF_H 24U
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#define ADF7021_DEV_P25 16U
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// TX/RX CLOCK register (REG 03)
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@ -142,11 +133,8 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
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// Bug in ADI evaluation software, use datasheet formula (4FSK)
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#define ADF7021_DISC_BW_DSTAR 597U // K=85
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#define ADF7021_DISC_BW_DMR 393U // K=32
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#if defined(ADF7021_YSF_HALF_DEV)
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#define ADF7021_DISC_BW_YSF 394U // K=32
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#else
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#define ADF7021_DISC_BW_YSF 344U // K=28
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#endif
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#define ADF7021_DISC_BW_YSF_L 394U // K=32
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#define ADF7021_DISC_BW_YSF_H 344U // K=28
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#define ADF7021_DISC_BW_P25 394U // K=32
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// Post demodulator bandwith (REG 04)
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@ -201,11 +189,8 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
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// Deviation of modulator (REG 02)
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#define ADF7021_DEV_DSTAR 26U
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#define ADF7021_DEV_DMR 14U
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#if defined(ADF7021_YSF_HALF_DEV)
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#define ADF7021_DEV_YSF 10U
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#else
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#define ADF7021_DEV_YSF 19U
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#endif
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#define ADF7021_DEV_YSF_L 10U
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#define ADF7021_DEV_YSF_H 19U
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#define ADF7021_DEV_P25 14U
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// TX/RX CLOCK register (REG 03)
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@ -218,11 +203,8 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
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// Bug in ADI evaluation software, use datasheet formula (4FSK)
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#define ADF7021_DISC_BW_DSTAR 522U // K=85
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#define ADF7021_DISC_BW_DMR 491U // K=32
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#if defined(ADF7021_YSF_HALF_DEV)
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#define ADF7021_DISC_BW_YSF 493U // K=32
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#else
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#define ADF7021_DISC_BW_YSF 430U // K=28
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#endif
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#define ADF7021_DISC_BW_YSF_L 493U // K=32
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#define ADF7021_DISC_BW_YSF_H 430U // K=28
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#define ADF7021_DISC_BW_P25 493U // K=32
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// Post demodulator bandwith (REG 04)
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@ -269,23 +251,18 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
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#define ADF7021_SLICER_TH_DSTAR 0U
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#define ADF7021_SLICER_TH_DMR 48U
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#if defined(ADF7021_YSF_HALF_DEV)
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#define ADF7021_SLICER_TH_YSF 32U
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#else
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#define ADF7021_SLICER_TH_YSF 63U
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#endif
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#define ADF7021_SLICER_TH_YSF_L 32U
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#define ADF7021_SLICER_TH_YSF_H 63U
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#define ADF7021_SLICER_TH_P25 43U
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#else
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#define ADF7021_SLICER_TH_DSTAR 0U
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#define ADF7021_SLICER_TH_DMR 54U
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#if defined(ADF7021_YSF_HALF_DEV)
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#define ADF7021_SLICER_TH_YSF 38U
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#else
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#define ADF7021_SLICER_TH_YSF 75U
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#endif
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#define ADF7021_SLICER_TH_YSF_L 38U
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#define ADF7021_SLICER_TH_YSF_H 75U
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#define ADF7021_SLICER_TH_P25 52U
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#endif
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#define bitRead(value, bit) (((value) >> (bit)) & 0x01)
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3
Config.h
3
Config.h
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@ -55,9 +55,6 @@
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// #define STM32_USART1_HOST
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#define STM32_USB_HOST
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// Enable Half Deviation mode in YSF (experimental)
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// #define ADF7021_YSF_HALF_DEV
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// Send RSSI value:
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// #define SEND_RSSI_DATA
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@ -57,6 +57,8 @@ extern bool m_dmrEnable;
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extern bool m_ysfEnable;
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extern bool m_p25Enable;
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extern bool m_duplex;
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extern bool m_tx;
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extern bool m_dcd;
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3
IO.cpp
3
IO.cpp
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@ -35,7 +35,8 @@ m_rxBuffer(RX_RINGBUFFER_SIZE),
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m_txBuffer(TX_RINGBUFFER_SIZE),
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m_ledCount(0U),
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m_ledValue(true),
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m_watchdog(0U)
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m_watchdog(0U),
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m_LoDevYSF(false)
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{
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Init();
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2
IO.h
2
IO.h
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@ -82,6 +82,7 @@ public:
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uint8_t setFreq(uint32_t frequency_rx, uint32_t frequency_tx);
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void setMode(void);
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void setDecode(bool dcd);
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void setLoDevYSF(bool ysfLoDev);
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// RF interface API
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void setTX(void);
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@ -102,6 +103,7 @@ private:
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bool m_started;
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CBitRB m_rxBuffer;
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CBitRB m_txBuffer;
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bool m_LoDevYSF;
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uint32_t m_ledCount;
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bool m_ledValue;
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@ -33,6 +33,8 @@ bool m_dmrEnable = true;
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bool m_ysfEnable = true;
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bool m_p25Enable = true;
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bool m_duplex = false;
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bool m_tx = false;
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bool m_dcd = false;
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@ -29,6 +29,8 @@ bool m_dmrEnable = true;
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bool m_ysfEnable = true;
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bool m_p25Enable = true;
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bool m_duplex = false;
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bool m_tx = false;
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bool m_dcd = false;
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@ -191,6 +191,9 @@ uint8_t CSerialPort::setConfig(const uint8_t* data, uint8_t length)
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{
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if (length < 13U)
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return 4U;
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bool ysfLoDev = (data[0U] & 0x08U) == 0x08U;
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bool simplex = (data[0U] & 0x80U) == 0x80U;
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bool dstarEnable = (data[1U] & 0x01U) == 0x01U;
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bool dmrEnable = (data[1U] & 0x02U) == 0x02U;
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@ -224,6 +227,8 @@ uint8_t CSerialPort::setConfig(const uint8_t* data, uint8_t length)
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m_dmrEnable = dmrEnable;
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m_ysfEnable = ysfEnable;
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m_p25Enable = p25Enable;
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m_duplex = !simplex;
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dstarTX.setTXDelay(txDelay);
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ysfTX.setTXDelay(txDelay);
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@ -232,6 +237,7 @@ uint8_t CSerialPort::setConfig(const uint8_t* data, uint8_t length)
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dmrDMORX.setColorCode(colorCode);
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io.setLoDevYSF(ysfLoDev);
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io.start();
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return 0U;
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