mirror of
https://github.com/g4klx/MMDVM_HS.git
synced 2026-04-05 14:35:14 +00:00
Support for interrupt counter test mode
This commit is contained in:
Andy CA6JAU
parent
c45a7cf38f
commit
1aab7ec355
13 changed files with 93 additions and 59 deletions
55
ADF7021.cpp
55
ADF7021.cpp
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@ -20,7 +20,7 @@
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include "Config.h"
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#if defined(ENABLE_ADF7021)
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@ -283,7 +283,7 @@ void CIO::ifConf(MMDVM_STATE modemState, bool reset)
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m_RX_F_divider = floor(divider + 0.5);
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ADF7021_RX_REG0 = (uint32_t) 0b0000;
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#if defined(BIDIR_DATA_PIN)
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ADF7021_RX_REG0 |= (uint32_t) 0b01001 << 27; // mux regulator/receive
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#else
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@ -292,7 +292,7 @@ void CIO::ifConf(MMDVM_STATE modemState, bool reset)
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ADF7021_RX_REG0 |= (uint32_t) m_RX_N_divider << 19; // frequency;
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ADF7021_RX_REG0 |= (uint32_t) m_RX_F_divider << 4; // frequency;
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if( div2 == 1U )
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divider = m_frequency_tx / (ADF7021_PFD / 2U);
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else
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@ -369,7 +369,7 @@ void CIO::ifConf(MMDVM_STATE modemState, bool reset)
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ADF7021_REG3 = ADF7021_REG3_DSTAR;
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ADF7021_REG10 = ADF7021_REG10_DSTAR;
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// K=32
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ADF7021_REG4 = (uint32_t) 0b0100 << 0; // register 4
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ADF7021_REG4 |= (uint32_t) 0b001 << 4; // mode, GMSK
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@ -386,10 +386,10 @@ void CIO::ifConf(MMDVM_STATE modemState, bool reset)
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ADF7021_REG2 |= (uint32_t) (m_dstarDev / div2) << 19; // deviation
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ADF7021_REG2 |= (uint32_t) 0b001 << 4; // modulation (GMSK)
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break;
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case STATE_DMR:
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// Dev: +1 symb 648 Hz, symb rate = 4800
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ADF7021_REG3 = ADF7021_REG3_DMR;
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ADF7021_REG10 = ADF7021_REG10_DMR;
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@ -413,7 +413,7 @@ void CIO::ifConf(MMDVM_STATE modemState, bool reset)
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ADF7021_REG2 |= (uint32_t) 0b111 << 4; // modulation (RC 4FSK)
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#endif
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break;
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case STATE_YSF:
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// Dev: +1 symb 900 Hz, symb rate = 4800
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@ -440,7 +440,7 @@ void CIO::ifConf(MMDVM_STATE modemState, bool reset)
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ADF7021_REG2 |= (uint32_t) 0b111 << 4; // modulation (RC 4FSK)
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#endif
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break;
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case STATE_P25:
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// Dev: +1 symb 600 Hz, symb rate = 4800
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@ -467,7 +467,7 @@ void CIO::ifConf(MMDVM_STATE modemState, bool reset)
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ADF7021_REG2 |= (uint32_t) 0b111 << 4; // modulation (RC 4FSK)
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#endif
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break;
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case STATE_NXDN:
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// Dev: +1 symb 350 Hz, symb rate = 2400
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@ -494,7 +494,7 @@ void CIO::ifConf(MMDVM_STATE modemState, bool reset)
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ADF7021_REG2 |= (uint32_t) 0b111 << 4; // modulation (RC 4FSK)
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#endif
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break;
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default:
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break;
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}
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@ -531,7 +531,7 @@ void CIO::ifConf(MMDVM_STATE modemState, bool reset)
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ADF7021_REG2 |= (uint32_t) 0b110001 << 7; // PA
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AD7021_control_word = ADF7021_REG2;
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Send_AD7021_control();
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// TEST DAC (14)
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#if defined(TEST_DAC)
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AD7021_control_word = 0x0000001E;
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@ -567,7 +567,7 @@ void CIO::ifConf(MMDVM_STATE modemState, bool reset)
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// 3FSK/4FSK DEMOD (13)
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AD7021_control_word = ADF7021_REG13;
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Send_AD7021_control();
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#if defined(TEST_TX)
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PTT_pin(HIGH);
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AD7021_control_word = ADF7021_TX_REG0;
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@ -607,7 +607,7 @@ void CIO::ifConf2(MMDVM_STATE modemState)
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ADF7021_REG3 = ADF7021_REG3_DSTAR;
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ADF7021_REG10 = ADF7021_REG10_DSTAR;
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// K=32
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ADF7021_REG4 = (uint32_t) 0b0100 << 0; // register 4
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ADF7021_REG4 |= (uint32_t) 0b001 << 4; // mode, GMSK
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@ -624,10 +624,10 @@ void CIO::ifConf2(MMDVM_STATE modemState)
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ADF7021_REG2 |= (uint32_t) (m_dstarDev / div2)<< 19; // deviation
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ADF7021_REG2 |= (uint32_t) 0b001 << 4; // modulation (GMSK)
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break;
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case STATE_DMR:
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// Dev: +1 symb 648 Hz, symb rate = 4800
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ADF7021_REG3 = ADF7021_REG3_DMR;
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ADF7021_REG10 = ADF7021_REG10_DMR;
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@ -647,7 +647,7 @@ void CIO::ifConf2(MMDVM_STATE modemState)
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ADF7021_REG2 |= (uint32_t) (m_dmrDev / div2) << 19; // deviation
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ADF7021_REG2 |= (uint32_t) 0b111 << 4; // modulation (RC 4FSK)
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break;
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case STATE_YSF:
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// Dev: +1 symb 900 Hz, symb rate = 4800
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@ -670,7 +670,7 @@ void CIO::ifConf2(MMDVM_STATE modemState)
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ADF7021_REG2 |= (uint32_t) (m_ysfDev / div2) << 19; // deviation
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ADF7021_REG2 |= (uint32_t) 0b111 << 4; // modulation (RC 4FSK)
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break;
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case STATE_P25:
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// Dev: +1 symb 600 Hz, symb rate = 4800
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@ -740,7 +740,7 @@ void CIO::ifConf2(MMDVM_STATE modemState)
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// IF coarse cal (5)
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AD7021_control_word = ADF7021_REG5;
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Send_AD7021_control2();
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// Delay for coarse IF filter calibration
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delay_IFcal();
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@ -754,7 +754,7 @@ void CIO::ifConf2(MMDVM_STATE modemState)
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ADF7021_REG2 |= (uint32_t) 0b110001 << 7; // PA
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AD7021_control_word = ADF7021_REG2;
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Send_AD7021_control2();
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// TEST DAC (14)
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AD7021_control_word = 0x0000000E;
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Send_AD7021_control2();
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@ -778,7 +778,7 @@ void CIO::ifConf2(MMDVM_STATE modemState)
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// 3FSK/4FSK DEMOD (13)
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AD7021_control_word = ADF7021_REG13;
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Send_AD7021_control2();
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// TEST MODE (disabled) (15)
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AD7021_control_word = 0x000E000F;
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Send_AD7021_control2();
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@ -788,7 +788,7 @@ void CIO::ifConf2(MMDVM_STATE modemState)
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void CIO::interrupt()
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{
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uint8_t bit = 0U;
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if (!m_started)
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return;
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@ -850,7 +850,7 @@ void CIO::interrupt()
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even = ADF7021_EVEN_BIT;
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}
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}
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// we sample the RX bit at rising TXD clock edge, so TXD must be 1 and we are not in tx mode
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if (!m_tx && clk == 1U && !m_duplex) {
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if(RXD_pin())
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@ -860,7 +860,7 @@ void CIO::interrupt()
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m_rxBuffer.put(bit, m_control);
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}
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if (torx_request == true && even == ADF7021_EVEN_BIT && m_tx && clk == 0U) {
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// that is absolutely crucial in 4FSK, see datasheet:
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// enable sle after 1/4 tBit == 26uS when sending MSB (even == false) and clock is low
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@ -881,14 +881,15 @@ void CIO::interrupt()
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// last tranmittted bit is always the even bit
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// since the current bit is a transitional "don't care" bit, never transmitted
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even = !ADF7021_EVEN_BIT;
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}
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}
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m_watchdog++;
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m_modeTimerCnt++;
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m_int1counter++;
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if(m_scanPauseCnt >= SCAN_PAUSE)
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m_scanPauseCnt = 0U;
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if(m_scanPauseCnt != 0U)
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m_scanPauseCnt++;
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}
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@ -897,7 +898,7 @@ void CIO::interrupt()
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void CIO::interrupt2()
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{
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uint8_t bit = 0U;
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if(m_duplex) {
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if(RXD2_pin())
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bit = 1U;
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@ -906,6 +907,8 @@ void CIO::interrupt2()
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m_rxBuffer.put(bit, m_control);
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}
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m_int2counter++;
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}
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#endif
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