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https://github.com/g4klx/MMDVM_HS.git
synced 2026-04-05 14:35:14 +00:00
Adding second ADF7021 support and fixing some mistakes
This commit is contained in:
Andy CA6JAU
parent
e86e1bfdd2
commit
0c22c47d5c
13 changed files with 379 additions and 28 deletions
217
ADF7021.cpp
217
ADF7021.cpp
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@ -38,6 +38,9 @@ volatile uint32_t AD7021_control_word;
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uint32_t ADF7021_RX_REG0;
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uint32_t ADF7021_TX_REG0;
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uint32_t ADF7021_REG1;
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uint32_t div2;
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uint8_t m_control;
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static void Send_AD7021_control_shift()
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{
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@ -74,6 +77,24 @@ void Send_AD7021_control(bool doSle)
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}
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}
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#if defined(DUPLEX)
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static void Send_AD7021_control_sle2Pulse()
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{
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io.SLE2_pin(HIGH);
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io.dlybit();
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io.SLE2_pin(LOW);
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}
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void Send_AD7021_control2(bool doSle)
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{
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Send_AD7021_control_shift();
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if (doSle) {
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Send_AD7021_control_sle2Pulse();
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}
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}
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#endif
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#if defined(SEND_RSSI_DATA)
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uint16_t CIO::readRSSI()
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{
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@ -152,9 +173,7 @@ void CIO::ifConf(MMDVM_STATE modemState, bool reset)
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float divider;
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uint8_t N_divider;
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uint16_t F_divider;
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uint32_t div2;
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uint32_t ADF7021_REG1 = 0;
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uint32_t ADF7021_REG2 = 0;
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uint32_t ADF7021_REG3 = 0;
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uint32_t ADF7021_REG4 = 0;
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@ -420,12 +439,182 @@ void CIO::ifConf(MMDVM_STATE modemState, bool reset)
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AD7021_control_word = 0x000E000F;
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#endif
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Send_AD7021_control();
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#if defined(DUPLEX)
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if(m_duplex)
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ifConf2(modemState);
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#endif
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}
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#if defined(DUPLEX)
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void CIO::ifConf2(MMDVM_STATE modemState)
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{
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uint32_t ADF7021_REG2 = 0;
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uint32_t ADF7021_REG3 = 0;
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uint32_t ADF7021_REG4 = 0;
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uint32_t ADF7021_REG10 = 0;
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uint32_t ADF7021_REG13 = 0;
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switch (modemState) {
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case STATE_DSTAR:
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// Dev: 1200 Hz, symb rate = 4800
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ADF7021_REG3 = ADF7021_REG3_DSTAR;
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ADF7021_REG10 = ADF7021_REG10_DSTAR;
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// K=32
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ADF7021_REG4 = (uint32_t) 0b0100 << 0; // register 4
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ADF7021_REG4 |= (uint32_t) 0b001 << 4; // mode, GMSK
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ADF7021_REG4 |= (uint32_t) 0b1 << 7;
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ADF7021_REG4 |= (uint32_t) 0b10 << 8;
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ADF7021_REG4 |= (uint32_t) ADF7021_DISC_BW_DSTAR << 10; // Disc BW
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ADF7021_REG4 |= (uint32_t) ADF7021_POST_BW_DSTAR << 20; // Post dem BW
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ADF7021_REG4 |= (uint32_t) 0b10 << 30; // IF filter
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ADF7021_REG13 = (uint32_t) 0b1101 << 0; // register 13
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ADF7021_REG13 |= (uint32_t) ADF7021_SLICER_TH_DSTAR << 4; // slicer threshold
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ADF7021_REG2 = (uint32_t) 0b00 << 28; // clock normal
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ADF7021_REG2 |= (uint32_t) (ADF7021_DEV_DSTAR / div2)<< 19; // deviation
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ADF7021_REG2 |= (uint32_t) 0b001 << 4; // modulation (GMSK)
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break;
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case STATE_DMR:
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// Dev: +1 symb 648 Hz, symb rate = 4800
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ADF7021_REG3 = ADF7021_REG3_DMR;
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ADF7021_REG10 = ADF7021_REG10_DMR;
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// K=32
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ADF7021_REG4 = (uint32_t) 0b0100 << 0; // register 4
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ADF7021_REG4 |= (uint32_t) 0b011 << 4; // mode, 4FSK
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ADF7021_REG4 |= (uint32_t) 0b0 << 7;
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ADF7021_REG4 |= (uint32_t) 0b11 << 8;
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ADF7021_REG4 |= (uint32_t) ADF7021_DISC_BW_DMR << 10; // Disc BW
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ADF7021_REG4 |= (uint32_t) ADF7021_POST_BW_DMR << 20; // Post dem BW
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ADF7021_REG4 |= (uint32_t) 0b10 << 30; // IF filter
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ADF7021_REG13 = (uint32_t) 0b1101 << 0; // register 13
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ADF7021_REG13 |= (uint32_t) ADF7021_SLICER_TH_DMR << 4; // slicer threshold
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ADF7021_REG2 = (uint32_t) 0b10 << 28; // invert data (and RC alpha = 0.5)
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ADF7021_REG2 |= (uint32_t) (ADF7021_DEV_DMR / div2) << 19; // deviation
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ADF7021_REG2 |= (uint32_t) 0b111 << 4; // modulation (RC 4FSK)
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break;
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case STATE_YSF:
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// Dev: +1 symb 900 Hz, symb rate = 4800
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ADF7021_REG3 = (m_LoDevYSF ? ADF7021_REG3_YSF_L : ADF7021_REG3_YSF_H);
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ADF7021_REG10 = ADF7021_REG10_YSF;
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// K=28
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ADF7021_REG4 = (uint32_t) 0b0100 << 0; // register 4
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ADF7021_REG4 |= (uint32_t) 0b011 << 4; // mode, 4FSK
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ADF7021_REG4 |= (uint32_t) 0b0 << 7;
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ADF7021_REG4 |= (uint32_t) 0b11 << 8;
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ADF7021_REG4 |= (uint32_t) (m_LoDevYSF ? ADF7021_DISC_BW_YSF_L : ADF7021_DISC_BW_YSF_H) << 10; // Disc BW
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ADF7021_REG4 |= (uint32_t) ADF7021_POST_BW_YSF << 20; // Post dem BW
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ADF7021_REG4 |= (uint32_t) 0b10 << 30; // IF filter
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ADF7021_REG13 = (uint32_t) 0b1101 << 0; // register 13
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ADF7021_REG13 |= (uint32_t) (m_LoDevYSF ? ADF7021_SLICER_TH_YSF_L : ADF7021_SLICER_TH_YSF_H) << 4; // slicer threshold
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ADF7021_REG2 = (uint32_t) 0b10 << 28; // invert data (and RC alpha = 0.5)
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ADF7021_REG2 |= (uint32_t) ((m_LoDevYSF ? ADF7021_DEV_YSF_L : ADF7021_DEV_YSF_H) / div2) << 19; // deviation
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ADF7021_REG2 |= (uint32_t) 0b111 << 4; // modulation (RC 4FSK)
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break;
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case STATE_P25:
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// Dev: +1 symb 600 Hz, symb rate = 4800
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ADF7021_REG3 = ADF7021_REG3_P25;
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ADF7021_REG10 = ADF7021_REG10_P25;
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// K=32
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ADF7021_REG4 = (uint32_t) 0b0100 << 0; // register 4
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ADF7021_REG4 |= (uint32_t) 0b011 << 4; // mode, 4FSK
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ADF7021_REG4 |= (uint32_t) 0b0 << 7;
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ADF7021_REG4 |= (uint32_t) 0b11 << 8;
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ADF7021_REG4 |= (uint32_t) ADF7021_DISC_BW_P25 << 10; // Disc BW
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ADF7021_REG4 |= (uint32_t) ADF7021_POST_BW_P25 << 20; // Post dem BW
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ADF7021_REG4 |= (uint32_t) 0b10 << 30; // IF filter
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ADF7021_REG13 = (uint32_t) 0b1101 << 0; // register 13
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ADF7021_REG13 |= (uint32_t) ADF7021_SLICER_TH_P25 << 4; // slicer threshold
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ADF7021_REG2 = (uint32_t) 0b10 << 28; // invert data (and RC alpha = 0.5)
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ADF7021_REG2 |= (uint32_t) (ADF7021_DEV_P25 / div2) << 19; // deviation
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ADF7021_REG2 |= (uint32_t) 0b111 << 4; // modulation (RC 4FSK)
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break;
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default:
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break;
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}
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// VCO/OSCILLATOR (1)
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AD7021_control_word = ADF7021_REG1;
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Send_AD7021_control2();
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// TX/RX CLOCK (3)
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AD7021_control_word = ADF7021_REG3;
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Send_AD7021_control2();
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// DEMOD (4)
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AD7021_control_word = ADF7021_REG4;
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Send_AD7021_control2();
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// IF FILTER (5)
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AD7021_control_word = ADF7021_REG5;
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Send_AD7021_control2();
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// Delay for coarse IF filter calibration
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delay_ifcal_coarse();
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// Frequency RX (0) and set to RX only
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AD7021_control_word = ADF7021_RX_REG0;
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Send_AD7021_control2();
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// MODULATION (2)
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ADF7021_REG2 |= (uint32_t) 0b0010; // register 2
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ADF7021_REG2 |= (uint32_t) m_power << 13; // power level
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ADF7021_REG2 |= (uint32_t) 0b110001 << 7; // PA
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AD7021_control_word = ADF7021_REG2;
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Send_AD7021_control2();
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// TEST DAC (14)
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AD7021_control_word = 0x0000000E;
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Send_AD7021_control2();
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// AGC (auto, defaults) (9)
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AD7021_control_word = 0x000231E9;
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Send_AD7021_control2();
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// AFC (10)
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AD7021_control_word = ADF7021_REG10;
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Send_AD7021_control2();
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// SYNC WORD DET (11)
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AD7021_control_word = 0x0000003B;
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Send_AD7021_control2();
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// SWD/THRESHOLD (12)
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AD7021_control_word = 0x0000010C;
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Send_AD7021_control2();
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// 3FSK/4FSK DEMOD (13)
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AD7021_control_word = ADF7021_REG13;
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Send_AD7021_control2();
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// TEST MODE (disabled) (15)
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AD7021_control_word = 0x000E000F;
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Send_AD7021_control2();
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}
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#endif
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void CIO::interrupt()
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{
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uint8_t bit = 0;
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uint8_t control = MARK_NONE;
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if (!m_started)
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return;
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@ -450,7 +639,7 @@ void CIO::interrupt()
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// we set the TX bit at TXD low, sampling of ADF7021 happens at rising clock
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if (m_tx && clk == 0) {
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m_txBuffer.get(bit, control);
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m_txBuffer.get(bit, m_control);
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even = !even;
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// use this for tracking issues
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@ -493,13 +682,13 @@ void CIO::interrupt()
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}
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// we sample the RX bit at rising TXD clock edge, so TXD must be 1 and we are not in tx mode
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if (!m_tx && clk == 1) {
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if (!m_tx && clk == 1 && !m_duplex) {
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if(RXD_pin())
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bit = 1;
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else
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bit = 0;
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m_rxBuffer.put(bit, control);
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m_rxBuffer.put(bit, m_control);
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}
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if (torx_request == true && even == false && m_tx && clk == 0) {
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@ -534,6 +723,22 @@ void CIO::interrupt()
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m_scanPauseCnt++;
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}
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#if defined(DUPLEX)
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void CIO::interrupt2()
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{
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uint8_t bit = 0;
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if(m_duplex) {
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if(RXD2_pin())
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bit = 1;
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else
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bit = 0;
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m_rxBuffer.put(bit, m_control);
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}
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}
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#endif
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//======================================================================================================================
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void CIO::setTX()
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{
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