2017-04-29 16:58:41 +02:00
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/*
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* Copyright (C) 2009-2017 by Jonathan Naylor G4KLX
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2018-01-21 15:56:15 +01:00
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* Copyright (C) 2017,2018 by Andy Uribe CA6JAU
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2017-04-29 16:58:41 +02:00
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include "Config.h"
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2017-04-30 04:05:03 +02:00
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#if defined(DUPLEX)
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2017-04-29 16:58:41 +02:00
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#include "Globals.h"
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#include "DMRSlotRX.h"
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#include "DMRSlotType.h"
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#include "Utils.h"
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2017-05-21 18:40:20 +02:00
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const uint8_t MAX_SYNC_BYTES_ERRS = 3U;
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2017-04-29 16:58:41 +02:00
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const uint8_t MAX_SYNC_LOST_FRAMES = 13U;
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const uint16_t NOENDPTR = 9999U;
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const uint8_t CONTROL_NONE = 0x00U;
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const uint8_t CONTROL_VOICE = 0x20U;
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const uint8_t CONTROL_DATA = 0x40U;
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2018-07-16 02:51:42 +02:00
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const uint8_t BIT_MASK_TABLE[] = {0x80U, 0x40U, 0x20U, 0x10U, 0x08U, 0x04U, 0x02U, 0x01U};
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#define WRITE_BIT1(p,i,b) p[(i)>>3] = (b) ? (p[(i)>>3] | BIT_MASK_TABLE[(i)&7]) : (p[(i)>>3] & ~BIT_MASK_TABLE[(i)&7])
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#define READ_BIT1(p,i) ((p[(i)>>3] & BIT_MASK_TABLE[(i)&7]) >> (7 - ((i)&7)))
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2017-05-07 01:19:08 +02:00
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CDMRSlotRX::CDMRSlotRX() :
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m_slot(false),
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2017-04-30 04:05:03 +02:00
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m_patternBuffer(0x00U),
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2017-04-29 16:58:41 +02:00
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m_buffer(),
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m_dataPtr(0U),
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2018-01-21 04:57:53 +01:00
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m_syncPtr1(0U),
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m_startPtr1(0U),
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m_endPtr1(NOENDPTR),
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m_control1(CONTROL_NONE),
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m_syncCount1(0U),
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m_state1(DMRRXS_NONE),
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m_n1(0U),
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m_type1(0U),
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m_syncPtr2(0U),
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m_startPtr2(0U),
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m_endPtr2(NOENDPTR),
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m_control2(CONTROL_NONE),
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m_syncCount2(0U),
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m_state2(DMRRXS_NONE),
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m_n2(0U),
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m_type2(0U),
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2017-04-29 16:58:41 +02:00
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m_delayPtr(0U),
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m_colorCode(0U),
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2018-01-21 04:57:53 +01:00
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m_delay(0U)
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2017-04-29 16:58:41 +02:00
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{
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}
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2017-05-07 01:19:08 +02:00
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void CDMRSlotRX::start(bool slot)
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2017-04-29 16:58:41 +02:00
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{
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2017-05-07 01:19:08 +02:00
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m_slot = slot;
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2017-04-29 16:58:41 +02:00
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m_delayPtr = 0U;
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}
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void CDMRSlotRX::reset()
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{
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m_dataPtr = 0U;
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m_delayPtr = 0U;
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2017-05-07 01:19:08 +02:00
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m_patternBuffer = 0U;
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2018-01-21 04:57:53 +01:00
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m_syncPtr1 = 0U;
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m_control1 = CONTROL_NONE;
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m_syncCount1 = 0U;
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m_state1 = DMRRXS_NONE;
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m_startPtr1 = 0U;
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m_endPtr1 = NOENDPTR;
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m_type1 = 0U;
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m_n1 = 0U;
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m_syncPtr2 = 0U;
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m_control2 = CONTROL_NONE;
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m_syncCount2 = 0U;
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m_state2 = DMRRXS_NONE;
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m_startPtr2 = 0U;
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m_endPtr2 = NOENDPTR;
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m_type2 = 0U;
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m_n2 = 0U;
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2017-04-29 16:58:41 +02:00
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}
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2017-04-30 04:05:03 +02:00
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bool CDMRSlotRX::databit(bool bit)
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2017-04-29 16:58:41 +02:00
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{
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2018-01-21 04:57:53 +01:00
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uint16_t min;
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uint16_t max;
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2017-04-29 16:58:41 +02:00
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m_delayPtr++;
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if (m_delayPtr < m_delay)
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2018-01-21 04:57:53 +01:00
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return (m_state1 != DMRRXS_NONE) || (m_state2 != DMRRXS_NONE);
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2017-04-29 16:58:41 +02:00
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2018-07-16 02:51:42 +02:00
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WRITE_BIT1(m_buffer, m_dataPtr, bit);
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2017-04-30 04:05:03 +02:00
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m_patternBuffer <<= 1;
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if (bit)
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m_patternBuffer |= 0x01U;
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2017-05-01 06:02:47 +02:00
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2018-01-21 04:57:53 +01:00
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if (m_state1 == DMRRXS_NONE || m_state2 == DMRRXS_NONE) {
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2017-05-07 01:19:08 +02:00
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correlateSync();
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2017-04-29 16:58:41 +02:00
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} else {
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2018-01-21 04:57:53 +01:00
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if(m_slot) {
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min = m_syncPtr2 + DMR_BUFFER_LENGTH_BITS - 2;
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max = m_syncPtr2 + 2;
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} else {
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min = m_syncPtr1 + DMR_BUFFER_LENGTH_BITS - 2;
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max = m_syncPtr1 + 2;
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}
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2017-05-07 01:19:08 +02:00
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if (min >= DMR_BUFFER_LENGTH_BITS)
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min -= DMR_BUFFER_LENGTH_BITS;
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if (max >= DMR_BUFFER_LENGTH_BITS)
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max -= DMR_BUFFER_LENGTH_BITS;
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if (min < max) {
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if (m_dataPtr >= min && m_dataPtr <= max)
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correlateSync();
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} else {
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if (m_dataPtr >= min || m_dataPtr <= max)
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correlateSync();
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}
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2017-04-29 16:58:41 +02:00
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}
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2018-01-21 04:57:53 +01:00
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if(m_slot)
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procSlot2();
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else
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procSlot1();
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m_dataPtr++;
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2017-04-29 16:58:41 +02:00
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2018-01-21 04:57:53 +01:00
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if (m_dataPtr >= DMR_BUFFER_LENGTH_BITS)
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m_dataPtr = 0U;
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2017-04-29 16:58:41 +02:00
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2018-01-21 04:57:53 +01:00
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return (m_state1 != DMRRXS_NONE) || (m_state2 != DMRRXS_NONE);;
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}
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void CDMRSlotRX::procSlot1()
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{
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if (m_dataPtr == m_endPtr1) {
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frame1[0U] = m_control1;
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bitsToBytes(m_startPtr1, DMR_FRAME_LENGTH_BYTES, frame1 + 1U);
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if (m_control1 == CONTROL_DATA) {
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2017-04-29 16:58:41 +02:00
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// Data sync
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uint8_t colorCode;
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uint8_t dataType;
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CDMRSlotType slotType;
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2018-01-21 04:57:53 +01:00
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slotType.decode(frame1 + 1U, colorCode, dataType);
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2017-04-29 16:58:41 +02:00
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if (colorCode == m_colorCode) {
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2018-01-21 04:57:53 +01:00
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m_syncCount1 = 0U;
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m_n1 = 0U;
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2017-04-29 16:58:41 +02:00
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2018-01-21 04:57:53 +01:00
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frame1[0U] |= dataType;
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2017-04-29 16:58:41 +02:00
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switch (dataType) {
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case DT_DATA_HEADER:
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2018-01-21 04:57:53 +01:00
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DEBUG2("DMRSlot1RX: data header found pos", m_syncPtr1);
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writeRSSIData1();
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m_state1 = DMRRXS_DATA;
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m_type1 = 0x00U;
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2017-04-29 16:58:41 +02:00
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break;
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case DT_RATE_12_DATA:
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case DT_RATE_34_DATA:
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case DT_RATE_1_DATA:
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2018-01-21 04:57:53 +01:00
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if (m_state1 == DMRRXS_DATA) {
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DEBUG2("DMRSlot1RX: data payload found pos", m_syncPtr1);
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writeRSSIData1();
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m_type1 = dataType;
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2017-04-29 16:58:41 +02:00
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}
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break;
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case DT_VOICE_LC_HEADER:
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2018-01-21 04:57:53 +01:00
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DEBUG2("DMRSlot1RX: voice header found pos", m_syncPtr1);
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writeRSSIData1();
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m_state1 = DMRRXS_VOICE;
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2017-04-29 16:58:41 +02:00
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break;
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case DT_VOICE_PI_HEADER:
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2018-01-21 04:57:53 +01:00
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if (m_state1 == DMRRXS_VOICE) {
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DEBUG2("DMRSlot1RX: voice pi header found pos", m_syncPtr1);
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writeRSSIData1();
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2017-04-29 16:58:41 +02:00
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}
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2018-01-21 04:57:53 +01:00
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m_state1 = DMRRXS_VOICE;
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2017-04-29 16:58:41 +02:00
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break;
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case DT_TERMINATOR_WITH_LC:
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2018-01-21 04:57:53 +01:00
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if (m_state1 == DMRRXS_VOICE) {
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DEBUG2("DMRSlot1RX: voice terminator found pos", m_syncPtr1);
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writeRSSIData1();
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m_state1 = DMRRXS_NONE;
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m_endPtr1 = NOENDPTR;
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2017-04-29 16:58:41 +02:00
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}
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break;
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default: // DT_CSBK
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2018-01-21 04:57:53 +01:00
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DEBUG2("DMRSlot1RX: csbk found pos", m_syncPtr1);
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writeRSSIData1();
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m_state1 = DMRRXS_NONE;
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m_endPtr1 = NOENDPTR;
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2017-04-29 16:58:41 +02:00
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break;
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}
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}
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2018-01-21 04:57:53 +01:00
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} else if (m_control1 == CONTROL_VOICE) {
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2017-04-29 16:58:41 +02:00
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// Voice sync
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2018-01-21 04:57:53 +01:00
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DEBUG2("DMRSlot1RX: voice sync found pos", m_syncPtr1);
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writeRSSIData1();
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m_state1 = DMRRXS_VOICE;
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m_syncCount1 = 0U;
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m_n1 = 0U;
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2017-04-29 16:58:41 +02:00
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} else {
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2018-01-21 04:57:53 +01:00
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if (m_state1 != DMRRXS_NONE) {
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m_syncCount1++;
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if (m_syncCount1 >= MAX_SYNC_LOST_FRAMES) {
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serial.writeDMRLost(0U);
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m_state1 = DMRRXS_NONE;
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m_endPtr1 = NOENDPTR;
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2017-04-29 16:58:41 +02:00
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}
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}
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2018-01-21 04:57:53 +01:00
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if (m_state1 == DMRRXS_VOICE) {
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if (m_n1 >= 5U) {
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frame1[0U] = CONTROL_VOICE;
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m_n1 = 0U;
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2017-04-29 16:58:41 +02:00
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} else {
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2018-01-21 04:57:53 +01:00
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frame1[0U] = ++m_n1;
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2017-04-29 16:58:41 +02:00
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}
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2018-01-21 04:57:53 +01:00
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serial.writeDMRData(0U, frame1, DMR_FRAME_LENGTH_BYTES + 1U);
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} else if (m_state1 == DMRRXS_DATA) {
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if (m_type1 != 0x00U) {
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frame1[0U] = CONTROL_DATA | m_type1;
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writeRSSIData1();
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2017-04-29 16:58:41 +02:00
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}
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}
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}
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2017-05-07 01:19:08 +02:00
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// End of this slot, reset some items for the next slot.
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2018-01-21 04:57:53 +01:00
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m_control1 = CONTROL_NONE;
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2017-04-29 16:58:41 +02:00
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}
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2018-01-21 04:57:53 +01:00
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}
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2017-04-29 16:58:41 +02:00
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2018-01-21 04:57:53 +01:00
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void CDMRSlotRX::procSlot2()
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{
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if (m_dataPtr == m_endPtr2) {
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frame2[0U] = m_control2;
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2017-04-29 16:58:41 +02:00
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2018-01-21 04:57:53 +01:00
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bitsToBytes(m_startPtr2, DMR_FRAME_LENGTH_BYTES, frame2 + 1U);
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if (m_control2 == CONTROL_DATA) {
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// Data sync
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uint8_t colorCode;
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uint8_t dataType;
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CDMRSlotType slotType;
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slotType.decode(frame2 + 1U, colorCode, dataType);
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if (colorCode == m_colorCode) {
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m_syncCount2 = 0U;
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m_n2 = 0U;
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frame2[0U] |= dataType;
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switch (dataType) {
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case DT_DATA_HEADER:
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DEBUG2("DMRSlot2RX: data header found pos", m_syncPtr2);
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writeRSSIData2();
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|
|
|
m_state2 = DMRRXS_DATA;
|
|
|
|
|
m_type2 = 0x00U;
|
|
|
|
|
break;
|
|
|
|
|
case DT_RATE_12_DATA:
|
|
|
|
|
case DT_RATE_34_DATA:
|
|
|
|
|
case DT_RATE_1_DATA:
|
|
|
|
|
if (m_state2 == DMRRXS_DATA) {
|
|
|
|
|
DEBUG2("DMRSlot2RX: data payload found pos", m_syncPtr2);
|
|
|
|
|
writeRSSIData2();
|
|
|
|
|
m_type2 = dataType;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case DT_VOICE_LC_HEADER:
|
|
|
|
|
DEBUG2("DMRSlot2RX: voice header found pos", m_syncPtr2);
|
|
|
|
|
writeRSSIData2();
|
|
|
|
|
m_state2 = DMRRXS_VOICE;
|
|
|
|
|
break;
|
|
|
|
|
case DT_VOICE_PI_HEADER:
|
|
|
|
|
if (m_state2 == DMRRXS_VOICE) {
|
|
|
|
|
DEBUG2("DMRSlot2RX: voice pi header found pos", m_syncPtr2);
|
|
|
|
|
writeRSSIData2();
|
|
|
|
|
}
|
|
|
|
|
m_state2 = DMRRXS_VOICE;
|
|
|
|
|
break;
|
|
|
|
|
case DT_TERMINATOR_WITH_LC:
|
|
|
|
|
if (m_state2 == DMRRXS_VOICE) {
|
|
|
|
|
DEBUG2("DMRSlot2RX: voice terminator found pos", m_syncPtr2);
|
|
|
|
|
writeRSSIData2();
|
|
|
|
|
m_state2 = DMRRXS_NONE;
|
|
|
|
|
m_endPtr2 = NOENDPTR;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
default: // DT_CSBK
|
|
|
|
|
DEBUG2("DMRSlot2RX: csbk found pos", m_syncPtr2);
|
|
|
|
|
writeRSSIData2();
|
|
|
|
|
m_state2 = DMRRXS_NONE;
|
|
|
|
|
m_endPtr2 = NOENDPTR;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
} else if (m_control2 == CONTROL_VOICE) {
|
|
|
|
|
// Voice sync
|
|
|
|
|
DEBUG2("DMRSlot2RX: voice sync found pos", m_syncPtr2);
|
|
|
|
|
writeRSSIData2();
|
|
|
|
|
m_state2 = DMRRXS_VOICE;
|
|
|
|
|
m_syncCount2 = 0U;
|
|
|
|
|
m_n2 = 0U;
|
|
|
|
|
} else {
|
|
|
|
|
if (m_state2 != DMRRXS_NONE) {
|
|
|
|
|
m_syncCount2++;
|
|
|
|
|
if (m_syncCount2 >= MAX_SYNC_LOST_FRAMES) {
|
|
|
|
|
serial.writeDMRLost(1U);
|
|
|
|
|
m_state2 = DMRRXS_NONE;
|
|
|
|
|
m_endPtr2 = NOENDPTR;
|
|
|
|
|
}
|
|
|
|
|
}
|
2017-05-07 01:19:08 +02:00
|
|
|
|
2018-01-21 04:57:53 +01:00
|
|
|
if (m_state2 == DMRRXS_VOICE) {
|
|
|
|
|
if (m_n2 >= 5U) {
|
|
|
|
|
frame2[0U] = CONTROL_VOICE;
|
|
|
|
|
m_n2 = 0U;
|
|
|
|
|
} else {
|
|
|
|
|
frame2[0U] = ++m_n2;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
serial.writeDMRData(1U, frame2, DMR_FRAME_LENGTH_BYTES + 1U);
|
|
|
|
|
} else if (m_state2 == DMRRXS_DATA) {
|
|
|
|
|
if (m_type2 != 0x00U) {
|
|
|
|
|
frame2[0U] = CONTROL_DATA | m_type2;
|
|
|
|
|
writeRSSIData2();
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// End of this slot, reset some items for the next slot.
|
|
|
|
|
m_control2 = CONTROL_NONE;
|
|
|
|
|
}
|
2017-04-29 16:58:41 +02:00
|
|
|
}
|
|
|
|
|
|
2017-05-07 01:19:08 +02:00
|
|
|
void CDMRSlotRX::correlateSync()
|
2018-01-21 04:57:53 +01:00
|
|
|
{
|
|
|
|
|
uint16_t syncPtr;
|
|
|
|
|
uint16_t startPtr;
|
|
|
|
|
uint16_t endPtr;
|
|
|
|
|
uint8_t control;
|
|
|
|
|
|
2017-04-30 04:05:03 +02:00
|
|
|
if (countBits64((m_patternBuffer & DMR_SYNC_BITS_MASK) ^ DMR_MS_DATA_SYNC_BITS) <= MAX_SYNC_BYTES_ERRS) {
|
|
|
|
|
|
2018-01-21 04:57:53 +01:00
|
|
|
control = CONTROL_DATA;
|
|
|
|
|
syncPtr = m_dataPtr;
|
2017-05-07 01:19:08 +02:00
|
|
|
|
2018-01-21 04:57:53 +01:00
|
|
|
startPtr = m_dataPtr + DMR_BUFFER_LENGTH_BITS - DMR_SLOT_TYPE_LENGTH_BITS / 2U - DMR_INFO_LENGTH_BITS / 2U - DMR_SYNC_LENGTH_BITS + 1;
|
|
|
|
|
if (startPtr >= DMR_BUFFER_LENGTH_BITS)
|
|
|
|
|
startPtr -= DMR_BUFFER_LENGTH_BITS;
|
2017-05-07 01:19:08 +02:00
|
|
|
|
2018-01-21 04:57:53 +01:00
|
|
|
endPtr = m_dataPtr + DMR_SLOT_TYPE_LENGTH_BITS / 2U + DMR_INFO_LENGTH_BITS / 2U;
|
|
|
|
|
if (endPtr >= DMR_BUFFER_LENGTH_BITS)
|
|
|
|
|
endPtr -= DMR_BUFFER_LENGTH_BITS;
|
|
|
|
|
|
|
|
|
|
if(m_slot) {
|
|
|
|
|
m_syncPtr2 = syncPtr;
|
|
|
|
|
m_startPtr2 = startPtr;
|
|
|
|
|
m_endPtr2 = endPtr;
|
|
|
|
|
m_control2 = control;
|
|
|
|
|
} else {
|
|
|
|
|
m_syncPtr1 = syncPtr;
|
|
|
|
|
m_startPtr1 = startPtr;
|
|
|
|
|
m_endPtr1 = endPtr;
|
|
|
|
|
m_control1 = control;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
//DEBUG5("SYNC corr MS Data found slot/pos/start/end:", m_slot ? 2U : 1U, m_dataPtr, startPtr, endPtr);
|
2017-04-30 04:05:03 +02:00
|
|
|
|
|
|
|
|
} else if (countBits64((m_patternBuffer & DMR_SYNC_BITS_MASK) ^ DMR_MS_VOICE_SYNC_BITS) <= MAX_SYNC_BYTES_ERRS) {
|
2017-04-29 16:58:41 +02:00
|
|
|
|
2018-01-21 04:57:53 +01:00
|
|
|
control = CONTROL_VOICE;
|
|
|
|
|
syncPtr = m_dataPtr;
|
|
|
|
|
|
|
|
|
|
startPtr = m_dataPtr + DMR_BUFFER_LENGTH_BITS - DMR_SLOT_TYPE_LENGTH_BITS / 2U - DMR_INFO_LENGTH_BITS / 2U - DMR_SYNC_LENGTH_BITS + 1;
|
|
|
|
|
if (startPtr >= DMR_BUFFER_LENGTH_BITS)
|
|
|
|
|
startPtr -= DMR_BUFFER_LENGTH_BITS;
|
2017-05-07 01:19:08 +02:00
|
|
|
|
2018-01-21 04:57:53 +01:00
|
|
|
endPtr = m_dataPtr + DMR_SLOT_TYPE_LENGTH_BITS / 2U + DMR_INFO_LENGTH_BITS / 2U;
|
|
|
|
|
if (endPtr >= DMR_BUFFER_LENGTH_BITS)
|
|
|
|
|
endPtr -= DMR_BUFFER_LENGTH_BITS;
|
|
|
|
|
|
|
|
|
|
if(m_slot) {
|
|
|
|
|
m_syncPtr2 = syncPtr;
|
|
|
|
|
m_startPtr2 = startPtr;
|
|
|
|
|
m_endPtr2 = endPtr;
|
|
|
|
|
m_control2 = control;
|
|
|
|
|
} else {
|
|
|
|
|
m_syncPtr1 = syncPtr;
|
|
|
|
|
m_startPtr1 = startPtr;
|
|
|
|
|
m_endPtr1 = endPtr;
|
|
|
|
|
m_control1 = control;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
//DEBUG5("SYNC corr MS Voice found slot/pos/start/end: ", m_slot ? 2U : 1U, m_dataPtr, startPtr, endPtr);
|
2017-04-29 16:58:41 +02:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2017-04-30 04:05:03 +02:00
|
|
|
void CDMRSlotRX::bitsToBytes(uint16_t start, uint8_t count, uint8_t* buffer)
|
2017-04-29 16:58:41 +02:00
|
|
|
{
|
2017-04-30 04:05:03 +02:00
|
|
|
for (uint8_t i = 0U; i < count; i++) {
|
|
|
|
|
buffer[i] = 0U;
|
2018-07-16 02:51:42 +02:00
|
|
|
buffer[i] |= READ_BIT1(m_buffer, start) << 7;
|
|
|
|
|
start++;
|
2017-05-21 18:40:20 +02:00
|
|
|
if (start >= DMR_BUFFER_LENGTH_BITS)
|
|
|
|
|
start -= DMR_BUFFER_LENGTH_BITS;
|
2018-07-16 02:51:42 +02:00
|
|
|
buffer[i] |= READ_BIT1(m_buffer, start) << 6;
|
|
|
|
|
start++;
|
2017-05-21 18:40:20 +02:00
|
|
|
if (start >= DMR_BUFFER_LENGTH_BITS)
|
|
|
|
|
start -= DMR_BUFFER_LENGTH_BITS;
|
2018-07-16 02:51:42 +02:00
|
|
|
buffer[i] |= READ_BIT1(m_buffer, start) << 5;
|
|
|
|
|
start++;
|
2017-05-21 18:40:20 +02:00
|
|
|
if (start >= DMR_BUFFER_LENGTH_BITS)
|
|
|
|
|
start -= DMR_BUFFER_LENGTH_BITS;
|
2018-07-16 02:51:42 +02:00
|
|
|
buffer[i] |= READ_BIT1(m_buffer, start) << 4;
|
|
|
|
|
start++;
|
2017-05-21 18:40:20 +02:00
|
|
|
if (start >= DMR_BUFFER_LENGTH_BITS)
|
|
|
|
|
start -= DMR_BUFFER_LENGTH_BITS;
|
2018-07-16 02:51:42 +02:00
|
|
|
buffer[i] |= READ_BIT1(m_buffer, start) << 3;
|
|
|
|
|
start++;
|
2017-05-21 18:40:20 +02:00
|
|
|
if (start >= DMR_BUFFER_LENGTH_BITS)
|
|
|
|
|
start -= DMR_BUFFER_LENGTH_BITS;
|
2018-07-16 02:51:42 +02:00
|
|
|
buffer[i] |= READ_BIT1(m_buffer, start) << 2;
|
|
|
|
|
start++;
|
2017-05-21 18:40:20 +02:00
|
|
|
if (start >= DMR_BUFFER_LENGTH_BITS)
|
|
|
|
|
start -= DMR_BUFFER_LENGTH_BITS;
|
2018-07-16 02:51:42 +02:00
|
|
|
buffer[i] |= READ_BIT1(m_buffer, start) << 1;
|
|
|
|
|
start++;
|
2017-05-21 18:40:20 +02:00
|
|
|
if (start >= DMR_BUFFER_LENGTH_BITS)
|
|
|
|
|
start -= DMR_BUFFER_LENGTH_BITS;
|
2018-07-16 02:51:42 +02:00
|
|
|
buffer[i] |= READ_BIT1(m_buffer, start) << 0;
|
|
|
|
|
start++;
|
2017-05-07 01:19:08 +02:00
|
|
|
if (start >= DMR_BUFFER_LENGTH_BITS)
|
|
|
|
|
start -= DMR_BUFFER_LENGTH_BITS;
|
2017-04-29 16:58:41 +02:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void CDMRSlotRX::setColorCode(uint8_t colorCode)
|
|
|
|
|
{
|
|
|
|
|
m_colorCode = colorCode;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void CDMRSlotRX::setDelay(uint8_t delay)
|
|
|
|
|
{
|
2017-05-07 01:19:08 +02:00
|
|
|
m_delay = delay / 5;
|
2017-04-29 16:58:41 +02:00
|
|
|
}
|
|
|
|
|
|
2018-01-21 04:57:53 +01:00
|
|
|
void CDMRSlotRX::writeRSSIData1()
|
|
|
|
|
{
|
|
|
|
|
#if defined(SEND_RSSI_DATA)
|
|
|
|
|
uint16_t rssi = io.readRSSI();
|
|
|
|
|
|
|
|
|
|
frame1[34U] = (rssi >> 8) & 0xFFU;
|
|
|
|
|
frame1[35U] = (rssi >> 0) & 0xFFU;
|
|
|
|
|
|
|
|
|
|
serial.writeDMRData(0U, frame1, DMR_FRAME_LENGTH_BYTES + 3U);
|
|
|
|
|
#else
|
|
|
|
|
serial.writeDMRData(0U, frame1, DMR_FRAME_LENGTH_BYTES + 1U);
|
|
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void CDMRSlotRX::writeRSSIData2()
|
2017-04-29 16:58:41 +02:00
|
|
|
{
|
|
|
|
|
#if defined(SEND_RSSI_DATA)
|
2017-04-30 04:05:03 +02:00
|
|
|
uint16_t rssi = io.readRSSI();
|
|
|
|
|
|
2018-01-21 04:57:53 +01:00
|
|
|
frame2[34U] = (rssi >> 8) & 0xFFU;
|
|
|
|
|
frame2[35U] = (rssi >> 0) & 0xFFU;
|
2017-04-30 04:05:03 +02:00
|
|
|
|
2018-01-21 04:57:53 +01:00
|
|
|
serial.writeDMRData(1U, frame2, DMR_FRAME_LENGTH_BYTES + 3U);
|
2017-04-29 16:58:41 +02:00
|
|
|
#else
|
2018-01-21 04:57:53 +01:00
|
|
|
serial.writeDMRData(1U, frame2, DMR_FRAME_LENGTH_BYTES + 1U);
|
2017-04-29 16:58:41 +02:00
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#endif
|