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https://github.com/g4klx/MMDVM.git
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694b83123a
In to NXDN possible problem on sinc filter anc isinc filter, think they must be recalculated but do not know how to do it. On D-STAR, DMR, C4FM and P25 it work.
230 lines
7.2 KiB
C++
230 lines
7.2 KiB
C++
/*
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* Copyright (C) 2016,2017,2018 by Jonathan Naylor G4KLX
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include "Config.h"
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#include "Globals.h"
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#include "IO.h"
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#if defined(__MK20DX256__) || defined(__MK64FX512__) || defined(__MK66FX1M0__)
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#if defined(EXTERNAL_OSC)
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#define PIN_LED 3
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#else
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#define PIN_LED 13
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#endif
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#define PIN_COS 4
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#define PIN_PTT 5
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#define PIN_COSLED 6
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#define PIN_DSTAR 9
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#define PIN_DMR 10
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#define PIN_YSF 11
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#define PIN_P25 12
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#if defined(__MK20DX256__)
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#define PIN_NXDN 2
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#else
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#define PIN_NXDN 24
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#endif
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#define PIN_ADC 5 // A0, Pin 14
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#define PIN_RSSI 4 // Teensy 3.5/3.6, A16, Pin 35. Teensy 3.1/3.2, A17, Pin 28
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#define PDB_CHnC1_TOS 0x0100
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#define PDB_CHnC1_EN 0x0001
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const uint16_t DC_OFFSET = 2048U;
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extern "C" {
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void adc0_isr()
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{
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io.interrupt();
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}
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}
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void CIO::initInt()
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{
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// Set up the TX, COS and LED pins
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pinMode(PIN_PTT, OUTPUT);
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pinMode(PIN_COSLED, OUTPUT);
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pinMode(PIN_LED, OUTPUT);
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pinMode(PIN_COS, INPUT);
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#if defined(ARDUINO_MODE_PINS)
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// Set up the mode output pins
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pinMode(PIN_DSTAR, OUTPUT);
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pinMode(PIN_DMR, OUTPUT);
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pinMode(PIN_YSF, OUTPUT);
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pinMode(PIN_P25, OUTPUT);
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pinMode(PIN_NXDN, OUTPUT);
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#endif
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}
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void CIO::startInt()
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{
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// Initialise the DAC
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SIM_SCGC2 |= SIM_SCGC2_DAC0;
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DAC0_C0 = DAC_C0_DACEN | DAC_C0_DACRFS; // 3.3V VDDA is DACREF_2
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// Initialise ADC0
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SIM_SCGC6 |= SIM_SCGC6_ADC0;
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ADC0_CFG1 = ADC_CFG1_ADIV(1) | ADC_CFG1_ADICLK(1) | // Single-ended 12 bits, long sample time
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ADC_CFG1_MODE(1) | ADC_CFG1_ADLSMP;
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ADC0_CFG2 = ADC_CFG2_MUXSEL | ADC_CFG2_ADLSTS(2); // Select channels ADxxxb
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ADC0_SC2 = ADC_SC2_REFSEL(0) | ADC_SC2_ADTRG; // Voltage ref external, hardware trigger
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ADC0_SC3 = ADC_SC3_AVGE | ADC_SC3_AVGS(0); // Enable averaging, 4 samples
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ADC0_SC3 |= ADC_SC3_CAL;
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while (ADC0_SC3 & ADC_SC3_CAL) // Wait for calibration
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;
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uint16_t sum0 = ADC0_CLPS + ADC0_CLP4 + ADC0_CLP3 + // Plus side gain
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ADC0_CLP2 + ADC0_CLP1 + ADC0_CLP0;
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sum0 = (sum0 / 2U) | 0x8000U;
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ADC0_PG = sum0;
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ADC0_SC1A = ADC_SC1_AIEN | PIN_ADC; // Enable ADC interrupt, use A0
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NVIC_ENABLE_IRQ(IRQ_ADC0);
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#if defined(SEND_RSSI_DATA)
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// Initialise ADC1
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SIM_SCGC3 |= SIM_SCGC3_ADC1;
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ADC1_CFG1 = ADC_CFG1_ADIV(1) | ADC_CFG1_ADICLK(1) | // Single-ended 12 bits, long sample time
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ADC_CFG1_MODE(1) | ADC_CFG1_ADLSMP;
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ADC1_CFG2 = ADC_CFG2_MUXSEL | ADC_CFG2_ADLSTS(2); // Select channels ADxxxb
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ADC1_SC2 = ADC_SC2_REFSEL(0); // Voltage ref external, software trigger
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ADC1_SC3 = ADC_SC3_AVGE | ADC_SC3_AVGS(0); // Enable averaging, 4 samples
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ADC1_SC3 |= ADC_SC3_CAL;
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while (ADC1_SC3 & ADC_SC3_CAL) // Wait for calibration
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;
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uint16_t sum1 = ADC1_CLPS + ADC1_CLP4 + ADC1_CLP3 + // Plus side gain
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ADC1_CLP2 + ADC1_CLP1 + ADC1_CLP0;
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sum1 = (sum1 / 2U) | 0x8000U;
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ADC1_PG = sum1;
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#endif
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#if defined(EXTERNAL_OSC)
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// Set ADC0 to trigger from the LPTMR at 48 kHz
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SIM_SOPT7 = SIM_SOPT7_ADC0ALTTRGEN | // Enable ADC0 alternate trigger
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SIM_SOPT7_ADC0TRGSEL(14); // Trigger ADC0 by LPTMR0
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CORE_PIN13_CONFIG = PORT_PCR_MUX(3);
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SIM_SCGC5 |= SIM_SCGC5_LPTIMER; // Enable Low Power Timer Access
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LPTMR0_CSR = 0; // Disable
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LPTMR0_PSR = LPTMR_PSR_PBYP; // Bypass prescaler/filter
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LPTMR0_CMR = (EXTERNAL_OSC / 48000) - 1; // Frequency divided by CMR + 1
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LPTMR0_CSR = LPTMR_CSR_TPS(2) | // Pin: 0=CMP0, 1=xtal, 2=pin13
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LPTMR_CSR_TMS; // Mode Select, 0=timer, 1=counter
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LPTMR0_CSR |= LPTMR_CSR_TEN; // Enable
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#else
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// Setup PDB for ADC0 at 48 kHz
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SIM_SCGC6 |= SIM_SCGC6_PDB; // Enable PDB clock
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PDB0_MOD = (F_BUS / 48000) - 1; // Timer period - 1
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PDB0_IDLY = 0; // Interrupt delay
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PDB0_CH0C1 = PDB_CHnC1_TOS | PDB_CHnC1_EN; // Enable pre-trigger for ADC0
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PDB0_SC = PDB_SC_TRGSEL(15) | PDB_SC_PDBEN | // SW trigger, enable interrupts, continuous mode
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PDB_SC_PDBIE | PDB_SC_CONT | PDB_SC_LDOK; // No prescaling
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PDB0_SC |= PDB_SC_SWTRIG; // Software trigger (reset and restart counter)
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#endif
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digitalWrite(PIN_PTT, m_pttInvert ? HIGH : LOW);
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digitalWrite(PIN_COSLED, LOW);
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digitalWrite(PIN_LED, HIGH);
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}
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void CIO::interrupt()
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{
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uint8_t control = MARK_NONE;
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uint16_t sample = DC_OFFSET;
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m_txBuffer.get(sample, control);
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*(int16_t *)&(DAC0_DAT0L) = sample;
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if ((ADC0_SC1A & ADC_SC1_COCO) == ADC_SC1_COCO) {
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sample = ADC0_RA;
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m_rxBuffer.put(sample, control);
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}
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#if defined(SEND_RSSI_DATA)
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if ((ADC1_SC1A & ADC_SC1_COCO) == ADC_SC1_COCO) {
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uint16_t rssi = ADC1_RA;
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m_rssiBuffer.put(rssi);
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} else {
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m_rssiBuffer.put(0U);
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}
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ADC1_SC1A = PIN_RSSI; // Start the next RSSI conversion
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#else
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m_rssiBuffer.put(0U);
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#endif
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m_watchdog++;
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}
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bool CIO::getCOSInt()
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{
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return digitalRead(PIN_COS) == HIGH;
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}
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void CIO::setLEDInt(bool on)
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{
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digitalWrite(PIN_LED, on ? HIGH : LOW);
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}
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void CIO::setPTTInt(bool on)
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{
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digitalWrite(PIN_PTT, on ? HIGH : LOW);
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}
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void CIO::setCOSInt(bool on)
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{
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digitalWrite(PIN_COSLED, on ? HIGH : LOW);
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}
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void CIO::setDStarInt(bool on)
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{
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digitalWrite(PIN_DSTAR, on ? HIGH : LOW);
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}
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void CIO::setDMRInt(bool on)
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{
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digitalWrite(PIN_DMR, on ? HIGH : LOW);
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}
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void CIO::setYSFInt(bool on)
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{
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digitalWrite(PIN_YSF, on ? HIGH : LOW);
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}
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void CIO::setP25Int(bool on)
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{
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digitalWrite(PIN_P25, on ? HIGH : LOW);
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}
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void CIO::setNXDNInt(bool on)
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{
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digitalWrite(PIN_NXDN, on ? HIGH : LOW);
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}
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void CIO::delayInt(unsigned int dly)
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{
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delay(dly);
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}
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#endif
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