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https://github.com/g4klx/MMDVM.git
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694b83123a
In to NXDN possible problem on sinc filter anc isinc filter, think they must be recalculated but do not know how to do it. On D-STAR, DMR, C4FM and P25 it work.
423 lines
11 KiB
C++
423 lines
11 KiB
C++
/*
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* Copyright (C) 2009-2017 by Jonathan Naylor G4KLX
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* Copyright (C) 2016 by Colin Durbridge G4EML
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* Copyright (C) 2017 by Andy Uribe CA6JAU
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include "Config.h"
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#include "Globals.h"
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#include "DMRSlotType.h"
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// Generated using rcosdesign(0.2, 8, 10, 'sqrt') in MATLAB
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static q15_t RRC_0_2_FILTER[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 850, 592, 219, -234, -720, -1179,
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-1548, -1769, -1795, -1597, -1172, -544, 237, 1092, 1927, 2637,
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3120, 3286, 3073, 2454, 1447, 116, -1431, -3043, -4544, -5739,
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-6442, -6483, -5735, -4121, -1633, 1669, 5651, 10118, 14822,
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19484, 23810, 27520, 30367, 32156, 32767, 32156, 30367, 27520,
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23810, 19484, 14822, 10118, 5651, 1669, -1633, -4121, -5735,
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-6483, -6442, -5739, -4544, -3043, -1431, 116, 1447, 2454,
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3073, 3286, 3120, 2637, 1927, 1092, 237, -544, -1172, -1597,
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-1795, -1769, -1548, -1179, -720, -234, 219, 592, 850}; // numTaps = 90, L = 10
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const uint16_t RRC_0_2_FILTER_PHASE_LEN = 9U; // phaseLength = numTaps/L
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const q15_t DMR_LEVELA = 1362;
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const q15_t DMR_LEVELB = 454;
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const q15_t DMR_LEVELC = -454;
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const q15_t DMR_LEVELD = -1362;
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// The PR FILL and BS Data Sync pattern.
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const uint8_t IDLE_DATA[] =
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{0x53U, 0xC2U, 0x5EU, 0xABU, 0xA8U, 0x67U, 0x1DU, 0xC7U, 0x38U, 0x3BU, 0xD9U,
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0x36U, 0x00U, 0x0DU, 0xFFU, 0x57U, 0xD7U, 0x5DU, 0xF5U, 0xD0U, 0x03U, 0xF6U,
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0xE4U, 0x65U, 0x17U, 0x1BU, 0x48U, 0xCAU, 0x6DU, 0x4FU, 0xC6U, 0x10U, 0xB4U};
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const uint8_t CACH_INTERLEAVE[] =
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{ 1U, 2U, 3U, 5U, 6U, 7U, 9U, 10U, 11U, 13U, 15U, 16U, 17U, 19U, 20U, 21U, 23U,
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25U, 26U, 27U, 29U, 30U, 31U, 33U, 34U, 35U, 37U, 39U, 40U, 41U, 43U, 44U, 45U, 47U,
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49U, 50U, 51U, 53U, 54U, 55U, 57U, 58U, 59U, 61U, 63U, 64U, 65U, 67U, 68U, 69U, 71U,
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73U, 74U, 75U, 77U, 78U, 79U, 81U, 82U, 83U, 85U, 87U, 88U, 89U, 91U, 92U, 93U, 95U};
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const uint8_t EMPTY_SHORT_LC[] =
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{0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U};
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const uint8_t BIT_MASK_TABLE[] = {0x80U, 0x40U, 0x20U, 0x10U, 0x08U, 0x04U, 0x02U, 0x01U};
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#define WRITE_BIT1(p,i,b) p[(i)>>3] = (b) ? (p[(i)>>3] | BIT_MASK_TABLE[(i)&7]) : (p[(i)>>3] & ~BIT_MASK_TABLE[(i)&7])
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#define READ_BIT1(p,i) (p[(i)>>3] & BIT_MASK_TABLE[(i)&7])
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const uint32_t STARTUP_COUNT = 20U;
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const uint32_t ABORT_COUNT = 6U;
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CDMRTX::CDMRTX() :
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m_fifo(),
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m_modFilter(),
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m_modState(),
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m_state(DMRTXSTATE_IDLE),
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m_idle(),
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m_cachPtr(0U),
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m_shortLC(),
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m_newShortLC(),
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m_markBuffer(),
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m_poBuffer(),
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m_poLen(0U),
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m_poPtr(0U),
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m_frameCount(0U),
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m_abortCount(),
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m_abort()
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{
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::memset(m_modState, 0x00U, 16U * sizeof(q15_t));
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m_modFilter.L = DMR_RADIO_SYMBOL_LENGTH;
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m_modFilter.phaseLength = RRC_0_2_FILTER_PHASE_LEN;
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m_modFilter.pCoeffs = RRC_0_2_FILTER;
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m_modFilter.pState = m_modState;
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::memcpy(m_newShortLC, EMPTY_SHORT_LC, 12U);
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::memcpy(m_shortLC, EMPTY_SHORT_LC, 12U);
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m_abort[0U] = false;
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m_abort[1U] = false;
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m_abortCount[0U] = 0U;
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m_abortCount[1U] = 0U;
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}
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void CDMRTX::process()
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{
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if (m_state == DMRTXSTATE_IDLE)
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return;
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if (m_poLen == 0U) {
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switch (m_state) {
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case DMRTXSTATE_SLOT1:
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createData(0U);
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m_state = DMRTXSTATE_CACH2;
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break;
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case DMRTXSTATE_CACH2:
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createCACH(1U, 0U);
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m_state = DMRTXSTATE_SLOT2;
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break;
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case DMRTXSTATE_SLOT2:
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createData(1U);
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m_state = DMRTXSTATE_CACH1;
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break;
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case DMRTXSTATE_CAL:
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createCal();
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break;
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default:
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createCACH(0U, 1U);
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m_state = DMRTXSTATE_SLOT1;
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break;
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}
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}
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if (m_poLen > 0U) {
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uint16_t space = io.getSpace();
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while (space > (4U * DMR_RADIO_SYMBOL_LENGTH)) {
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uint8_t c = m_poBuffer[m_poPtr];
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uint8_t m = m_markBuffer[m_poPtr];
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m_poPtr++;
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writeByte(c, m);
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space -= 4U * DMR_RADIO_SYMBOL_LENGTH;
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if (m_poPtr >= m_poLen) {
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m_poPtr = 0U;
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m_poLen = 0U;
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return;
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}
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}
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}
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}
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uint8_t CDMRTX::writeData1(const uint8_t* data, uint8_t length)
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{
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if (length != (DMR_FRAME_LENGTH_BYTES + 1U))
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return 4U;
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uint16_t space = m_fifo[0U].getSpace();
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if (space < DMR_FRAME_LENGTH_BYTES)
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return 5U;
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if (m_abort[0U]) {
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m_fifo[0U].reset();
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m_abort[0U] = false;
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}
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for (uint8_t i = 0U; i < DMR_FRAME_LENGTH_BYTES; i++)
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m_fifo[0U].put(data[i + 1U]);
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// Start the TX if it isn't already on
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if (!m_tx)
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m_state = DMRTXSTATE_SLOT1;
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return 0U;
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}
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uint8_t CDMRTX::writeData2(const uint8_t* data, uint8_t length)
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{
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if (length != (DMR_FRAME_LENGTH_BYTES + 1U))
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return 4U;
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uint16_t space = m_fifo[1U].getSpace();
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if (space < DMR_FRAME_LENGTH_BYTES)
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return 5U;
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if (m_abort[1U]) {
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m_fifo[1U].reset();
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m_abort[1U] = false;
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}
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for (uint8_t i = 0U; i < DMR_FRAME_LENGTH_BYTES; i++)
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m_fifo[1U].put(data[i + 1U]);
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// Start the TX if it isn't already on
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if (!m_tx)
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m_state = DMRTXSTATE_SLOT1;
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return 0U;
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}
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uint8_t CDMRTX::writeShortLC(const uint8_t* data, uint8_t length)
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{
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if (length != 9U)
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return 4U;
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::memset(m_newShortLC, 0x00U, 12U);
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for (uint8_t i = 0U; i < 68U; i++) {
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bool b = READ_BIT1(data, i);
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uint8_t n = CACH_INTERLEAVE[i];
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WRITE_BIT1(m_newShortLC, n, b);
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}
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return 0U;
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}
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uint8_t CDMRTX::writeAbort(const uint8_t* data, uint8_t length)
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{
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if (length != 1U)
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return 4U;
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switch (data[0U]) {
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case 1U:
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m_abortCount[0U] = 0U;
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m_abort[0U] = true;
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return 0U;
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case 2U:
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m_abortCount[1U] = 0U;
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m_abort[1U] = true;
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return 0U;
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default:
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return 4U;
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}
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}
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void CDMRTX::setStart(bool start)
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{
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m_state = start ? DMRTXSTATE_SLOT1 : DMRTXSTATE_IDLE;
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m_frameCount = 0U;
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m_abortCount[0U] = 0U;
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m_abortCount[1U] = 0U;
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m_abort[0U] = false;
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m_abort[1U] = false;
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}
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void CDMRTX::setCal(bool start)
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{
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m_state = start ? DMRTXSTATE_CAL : DMRTXSTATE_IDLE;
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}
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void CDMRTX::writeByte(uint8_t c, uint8_t control)
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{
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q15_t inBuffer[4U];
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q15_t outBuffer[DMR_RADIO_SYMBOL_LENGTH * 4U];
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const uint8_t MASK = 0xC0U;
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for (uint8_t i = 0U; i < 4U; i++, c <<= 2) {
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switch (c & MASK) {
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case 0xC0U:
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inBuffer[i] = DMR_LEVELA;
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break;
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case 0x80U:
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inBuffer[i] = DMR_LEVELB;
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break;
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case 0x00U:
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inBuffer[i] = DMR_LEVELC;
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break;
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default:
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inBuffer[i] = DMR_LEVELD;
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break;
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}
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}
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uint8_t controlBuffer[DMR_RADIO_SYMBOL_LENGTH * 4U];
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::memset(controlBuffer, MARK_NONE, DMR_RADIO_SYMBOL_LENGTH * 4U * sizeof(uint8_t));
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controlBuffer[DMR_RADIO_SYMBOL_LENGTH * 2U] = control;
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::arm_fir_interpolate_q15(&m_modFilter, inBuffer, outBuffer, 4U);
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io.write(STATE_DMR, outBuffer, DMR_RADIO_SYMBOL_LENGTH * 4U, controlBuffer);
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}
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uint8_t CDMRTX::getSpace1() const
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{
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return m_fifo[0U].getSpace() / (DMR_FRAME_LENGTH_BYTES + 2U);
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}
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uint8_t CDMRTX::getSpace2() const
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{
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return m_fifo[1U].getSpace() / (DMR_FRAME_LENGTH_BYTES + 2U);
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}
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void CDMRTX::createData(uint8_t slotIndex)
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{
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if (m_fifo[slotIndex].getData() >= DMR_FRAME_LENGTH_BYTES && m_frameCount >= STARTUP_COUNT && m_abortCount[slotIndex] >= ABORT_COUNT) {
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for (unsigned int i = 0U; i < DMR_FRAME_LENGTH_BYTES; i++) {
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m_poBuffer[i] = m_fifo[slotIndex].get();
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m_markBuffer[i] = MARK_NONE;
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}
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} else {
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m_abort[slotIndex] = false;
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// Transmit an idle message
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for (unsigned int i = 0U; i < DMR_FRAME_LENGTH_BYTES; i++) {
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m_poBuffer[i] = m_idle[i];
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m_markBuffer[i] = MARK_NONE;
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}
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}
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m_poLen = DMR_FRAME_LENGTH_BYTES;
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m_poPtr = 0U;
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}
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void CDMRTX::createCal()
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{
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// 1.2 kHz sine wave generation
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if (m_modemState == STATE_DMRCAL) {
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for (unsigned int i = 0U; i < DMR_FRAME_LENGTH_BYTES; i++) {
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m_poBuffer[i] = 0x5FU; // +3, +3, -3, -3 pattern for deviation cal.
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m_markBuffer[i] = MARK_NONE;
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}
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m_poLen = DMR_FRAME_LENGTH_BYTES;
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}
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// 80 Hz square wave generation
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if (m_modemState == STATE_LFCAL) {
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for (unsigned int i = 0U; i < 7U; i++) {
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m_poBuffer[i] = 0x55U; // +3, +3, ... pattern
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m_markBuffer[i] = MARK_NONE;
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}
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m_poBuffer[7U] = 0x5FU; // +3, +3, -3, -3 pattern
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for (unsigned int i = 8U; i < 15U; i++) {
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m_poBuffer[i] = 0xFFU; // -3, -3, ... pattern
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m_markBuffer[i] = MARK_NONE;
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}
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m_poLen = 15U;
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}
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m_poPtr = 0U;
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}
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void CDMRTX::createCACH(uint8_t txSlotIndex, uint8_t rxSlotIndex)
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{
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m_frameCount++;
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m_abortCount[0U]++;
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m_abortCount[1U]++;
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if (m_cachPtr >= 12U)
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m_cachPtr = 0U;
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if (m_cachPtr == 0U) {
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if (m_fifo[0U].getData() == 0U && m_fifo[1U].getData() == 0U)
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::memcpy(m_shortLC, EMPTY_SHORT_LC, 12U);
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else
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::memcpy(m_shortLC, m_newShortLC, 12U);
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}
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::memcpy(m_poBuffer, m_shortLC + m_cachPtr, 3U);
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m_markBuffer[0U] = MARK_NONE;
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m_markBuffer[1U] = MARK_NONE;
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m_markBuffer[2U] = rxSlotIndex == 1U ? MARK_SLOT1 : MARK_SLOT2;
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bool at = false;
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if (m_frameCount >= STARTUP_COUNT)
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at = m_fifo[rxSlotIndex].getData() > 0U;
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bool tc = txSlotIndex == 1U;
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bool ls0 = true; // For 1 and 2
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bool ls1 = true;
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if (m_cachPtr == 0U) // For 0
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ls1 = false;
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else if (m_cachPtr == 9U) // For 3
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ls0 = false;
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bool h0 = at ^ tc ^ ls1;
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bool h1 = tc ^ ls1 ^ ls0;
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bool h2 = at ^ tc ^ ls0;
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m_poBuffer[0U] |= at ? 0x80U : 0x00U;
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m_poBuffer[0U] |= tc ? 0x08U : 0x00U;
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m_poBuffer[1U] |= ls1 ? 0x80U : 0x00U;
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m_poBuffer[1U] |= ls0 ? 0x08U : 0x00U;
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m_poBuffer[1U] |= h0 ? 0x02U : 0x00U;
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m_poBuffer[2U] |= h1 ? 0x20U : 0x00U;
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m_poBuffer[2U] |= h2 ? 0x02U : 0x00U;
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m_poLen = DMR_CACH_LENGTH_BYTES;
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m_poPtr = 0U;
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m_cachPtr += 3U;
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}
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void CDMRTX::setColorCode(uint8_t colorCode)
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{
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::memcpy(m_idle, IDLE_DATA, DMR_FRAME_LENGTH_BYTES);
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CDMRSlotType slotType;
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slotType.encode(colorCode, DT_IDLE, m_idle);
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}
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void CDMRTX::resetFifo1()
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{
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m_fifo[0U].reset();
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}
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void CDMRTX::resetFifo2()
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{
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m_fifo[1U].reset();
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}
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uint32_t CDMRTX::getFrameCount()
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{
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return m_frameCount;
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}
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