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Supports drcc_dvm_nqf board
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parent
43e00bbe1d
commit
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5 changed files with 75 additions and 14 deletions
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@ -50,7 +50,7 @@ extern "C" {
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}
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/* ************* USART1 ***************** */
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#if defined(STM32F4_PI) || defined(STM32F4_F4M) || defined(STM32F722_F7M) || defined(STM32F722_PI) || defined(STM32F722_RPT_HAT) || defined(STM32F4_DVM) || (defined(STM32F4_NUCLEO) && defined(STM32F4_NUCLEO_ARDUINO_HEADER))
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#if defined(STM32F4_PI) || defined(STM32F4_F4M) || defined(STM32F722_F7M) || defined(STM32F722_PI) || defined(STM32F722_RPT_HAT) || defined(STM32F4_DVM) || (defined(STM32F4_NUCLEO) && defined(STM32F4_NUCLEO_ARDUINO_HEADER)) || defined(DRCC_DVM)
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volatile uint8_t TXSerialfifo1[TX_SERIAL_FIFO_SIZE];
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volatile uint8_t RXSerialfifo1[RX_SERIAL_FIFO_SIZE];
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@ -241,7 +241,7 @@ void WriteUSART1(const uint8_t* data, uint16_t length)
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#endif
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/* ************* USART2 ***************** */
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#if defined(STM32F4_NUCLEO) || defined(STM32F4_RPT_HAT_TGO)
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#if defined(STM32F4_NUCLEO) || defined(STM32F4_RPT_HAT_TGO) || defined(DRCC_DVM)
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volatile uint8_t TXSerialfifo2[TX_SERIAL_FIFO_SIZE];
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volatile uint8_t RXSerialfifo2[RX_SERIAL_FIFO_SIZE];
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@ -845,11 +845,15 @@ void CSerialPort::beginInt(uint8_t n, int speed)
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InitUSART1(speed);
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#elif defined(STM32F4_NUCLEO) || defined(STM32F4_RPT_HAT_TGO)
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InitUSART2(speed);
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#elif defined(DRCC_DVM)
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InitUSART1(speed);
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#endif
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break;
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case 3U:
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#if defined(STM32F4_NUCLEO) && defined(STM32F4_NUCLEO_ARDUINO_HEADER)
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InitUSART1(speed);
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#elif defined(DRCC_DVM)
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InitUSART2(speed);
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#else
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InitUART5(speed);
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#endif
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@ -869,10 +873,14 @@ int CSerialPort::availableInt(uint8_t n)
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return AvailUSART1();
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#elif defined(STM32F4_NUCLEO) || defined(STM32F4_RPT_HAT_TGO)
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return AvailUSART2();
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#elif defined(DRCC_DVM)
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return AvailUSART1();
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#endif
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case 3U:
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#if defined(STM32F4_NUCLEO) && defined(STM32F4_NUCLEO_ARDUINO_HEADER)
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return AvailUSART1();
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#elif defined(DRCC_DVM)
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return AvailUSART2();
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#else
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return AvailUART5();
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#endif
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@ -891,10 +899,14 @@ int CSerialPort::availableForWriteInt(uint8_t n)
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return AvailForWriteUSART1();
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#elif defined(STM32F4_NUCLEO) || defined(STM32F4_RPT_HAT_TGO)
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return AvailForWriteUSART2();
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#elif defined(DRCC_DVM)
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return AvailForWriteUSART1();
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#endif
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case 3U:
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#if defined(STM32F4_NUCLEO) && defined(STM32F4_NUCLEO_ARDUINO_HEADER)
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return AvailForWriteUSART1();
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#elif defined(DRCC_DVM)
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AvailForWriteUSART2();
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#else
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return AvailForWriteUART5();
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#endif
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@ -913,10 +925,14 @@ uint8_t CSerialPort::readInt(uint8_t n)
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return ReadUSART1();
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#elif defined(STM32F4_NUCLEO) || defined(STM32F4_RPT_HAT_TGO)
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return ReadUSART2();
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#elif defined(DRCC_DVM)
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return ReadUSART1();
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#endif
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case 3U:
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#if defined(STM32F4_NUCLEO) && defined(STM32F4_NUCLEO_ARDUINO_HEADER)
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return ReadUSART1();
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#elif defined(DRCC_DVM)
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return ReadUSART2();
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#else
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return ReadUART5();
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#endif
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@ -941,6 +957,10 @@ void CSerialPort::writeInt(uint8_t n, const uint8_t* data, uint16_t length, bool
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WriteUSART2(data, length);
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if (flush)
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TXSerialFlush2();
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#elif defined(DRCC_DVM)
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WriteUSART1(data, length);
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if (flush)
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TXSerialFlush1();
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#endif
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break;
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case 3U:
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@ -948,6 +968,10 @@ void CSerialPort::writeInt(uint8_t n, const uint8_t* data, uint16_t length, bool
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WriteUSART1(data, length);
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if (flush)
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TXSerialFlush1();
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#elif defined(DRCC_DVM)
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WriteUSART2(data, length);
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if (flush)
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TXSerialFlush2();
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#else
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WriteUART5(data, length);
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if (flush)
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