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https://github.com/g4klx/MMDVM.git
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External TCXO support for STM32F4 and Nucleo 446 board support
This commit is contained in:
Andy CA6JAU
parent
eacabfb184
commit
b8febb517f
3 changed files with 318 additions and 28 deletions
255
SerialSTM.cpp
255
SerialSTM.cpp
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@ -22,35 +22,39 @@
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#include "SerialPort.h"
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#if defined(STM32F4XX) || defined(STM32F4)
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/*
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Pin definitions:
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volatile uint32_t intcount1, intcount3, intcount5;
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- Host communication:
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USART1 - TXD PA9 - RXD PA10 (Pi board)
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USART2 - TXD PA2 - RXD PA3 (Nucleo board)
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USART3 - TXD PC10 - RXD PC11 (Discovery board)
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- Serial repeater:
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UART5 - TXD PC12 - RXD PD2
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*/
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#if defined(STM32F4XX) || defined(STM32F4)
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#define TX_SERIAL_FIFO_SIZE 256U
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#define RX_SERIAL_FIFO_SIZE 256U
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volatile uint8_t TXSerialfifo1[TX_SERIAL_FIFO_SIZE];
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volatile uint8_t RXSerialfifo1[RX_SERIAL_FIFO_SIZE];
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volatile uint16_t TXSerialfifohead1, TXSerialfifotail1;
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volatile uint16_t RXSerialfifohead1, RXSerialfifotail1;
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volatile uint8_t TXSerialfifo3[TX_SERIAL_FIFO_SIZE];
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volatile uint8_t RXSerialfifo3[RX_SERIAL_FIFO_SIZE];
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volatile uint16_t TXSerialfifohead3, TXSerialfifotail3;
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volatile uint16_t RXSerialfifohead3, RXSerialfifotail3;
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volatile uint8_t TXSerialfifo5[TX_SERIAL_FIFO_SIZE];
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volatile uint8_t RXSerialfifo5[RX_SERIAL_FIFO_SIZE];
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volatile uint16_t TXSerialfifohead5, TXSerialfifotail5;
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volatile uint16_t RXSerialfifohead5, RXSerialfifotail5;
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extern "C" {
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void USART1_IRQHandler();
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void USART2_IRQHandler();
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void USART3_IRQHandler();
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void UART5_IRQHandler();
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}
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/* ************* USART1 ***************** */
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#if defined(STM32F4_PI)
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volatile uint32_t intcount1;
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volatile uint8_t TXSerialfifo1[TX_SERIAL_FIFO_SIZE];
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volatile uint8_t RXSerialfifo1[RX_SERIAL_FIFO_SIZE];
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volatile uint16_t TXSerialfifohead1, TXSerialfifotail1;
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volatile uint16_t RXSerialfifohead1, RXSerialfifotail1;
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// Init queues
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void TXSerialfifoinit1()
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@ -229,7 +233,204 @@ void WriteUSART1(const uint8_t* data, uint16_t length)
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USART_ITConfig(USART1, USART_IT_TXE, ENABLE);
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}
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#endif
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/* ************* USART2 ***************** */
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#if defined(STM32F4_NUCLEO)
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volatile uint32_t intcount2;
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volatile uint8_t TXSerialfifo2[TX_SERIAL_FIFO_SIZE];
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volatile uint8_t RXSerialfifo2[RX_SERIAL_FIFO_SIZE];
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volatile uint16_t TXSerialfifohead2, TXSerialfifotail2;
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volatile uint16_t RXSerialfifohead2, RXSerialfifotail2;
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// Init queues
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void TXSerialfifoinit2()
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{
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TXSerialfifohead2 = 0U;
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TXSerialfifotail2 = 0U;
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}
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void RXSerialfifoinit2()
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{
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RXSerialfifohead2 = 0U;
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RXSerialfifotail2 = 0U;
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}
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// How full is queue
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// TODO decide if how full or how empty is preferred info to return
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uint16_t TXSerialfifolevel2()
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{
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uint32_t tail = TXSerialfifotail2;
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uint32_t head = TXSerialfifohead2;
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if (tail > head)
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return TX_SERIAL_FIFO_SIZE + head - tail;
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else
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return head - tail;
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}
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uint16_t RXSerialfifolevel2()
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{
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uint32_t tail = RXSerialfifotail2;
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uint32_t head = RXSerialfifohead2;
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if (tail > head)
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return RX_SERIAL_FIFO_SIZE + head - tail;
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else
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return head - tail;
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}
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// Flushes the transmit shift register
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// warning: this call is blocking
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void TXSerialFlush2()
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{
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// wait until the TXE shows the shift register is empty
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while (USART_GetITStatus(USART2, USART_FLAG_TXE))
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;
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}
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uint8_t TXSerialfifoput2(uint8_t next)
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{
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if (TXSerialfifolevel2() < TX_SERIAL_FIFO_SIZE) {
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TXSerialfifo2[TXSerialfifohead2] = next;
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TXSerialfifohead2++;
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if (TXSerialfifohead2 >= TX_SERIAL_FIFO_SIZE)
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TXSerialfifohead2 = 0U;
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// make sure transmit interrupts are enabled as long as there is data to send
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USART_ITConfig(USART2, USART_IT_TXE, ENABLE);
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return 1U;
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} else {
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return 0U; // signal an overflow occurred by returning a zero count
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}
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}
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void USART2_IRQHandler()
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{
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uint8_t c;
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if (USART_GetITStatus(USART2, USART_IT_RXNE)) {
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c = (uint8_t) USART_ReceiveData(USART2);
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if (RXSerialfifolevel2() < RX_SERIAL_FIFO_SIZE) {
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RXSerialfifo2[RXSerialfifohead2] = c;
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RXSerialfifohead2++;
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if (RXSerialfifohead2 >= RX_SERIAL_FIFO_SIZE)
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RXSerialfifohead2 = 0U;
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} else {
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// TODO - do something if rx fifo is full?
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}
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USART_ClearITPendingBit(USART2, USART_IT_RXNE);
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intcount2++;
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}
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if (USART_GetITStatus(USART2, USART_IT_TXE)) {
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c = 0U;
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if (TXSerialfifohead2 != TXSerialfifotail2) { // if the fifo is not empty
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c = TXSerialfifo2[TXSerialfifotail2];
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TXSerialfifotail2++;
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if (TXSerialfifotail2 >= TX_SERIAL_FIFO_SIZE)
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TXSerialfifotail2 = 0U;
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USART_SendData(USART2, c);
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} else { // if there's no more data to transmit then turn off TX interrupts
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USART_ITConfig(USART2, USART_IT_TXE, DISABLE);
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}
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USART_ClearITPendingBit(USART2, USART_IT_TXE);
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}
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}
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void InitUSART2(int speed)
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{
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// USART2 - TXD PA2 - RXD PA3
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GPIO_InitTypeDef GPIO_InitStructure;
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USART_InitTypeDef USART_InitStructure;
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NVIC_InitTypeDef NVIC_InitStructure;
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RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE);
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RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE);
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GPIO_PinAFConfig(GPIOA, GPIO_PinSource2, GPIO_AF_USART2);
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GPIO_PinAFConfig(GPIOA, GPIO_PinSource3, GPIO_AF_USART2);
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// USART IRQ init
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NVIC_InitStructure.NVIC_IRQChannel = USART2_IRQn;
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NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
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NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
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NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
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NVIC_Init(&NVIC_InitStructure);
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// Configure USART as alternate function
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GPIO_StructInit(&GPIO_InitStructure);
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GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
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GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2 | GPIO_Pin_3; // Tx | Rx
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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GPIO_Init(GPIOA, &GPIO_InitStructure);
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// Configure USART baud rate
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USART_StructInit(&USART_InitStructure);
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USART_InitStructure.USART_BaudRate = speed;
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USART_InitStructure.USART_WordLength = USART_WordLength_8b;
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USART_InitStructure.USART_StopBits = USART_StopBits_1;
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USART_InitStructure.USART_Parity = USART_Parity_No;
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USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
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USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
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USART_Init(USART2, &USART_InitStructure);
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USART_Cmd(USART2, ENABLE);
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USART_ITConfig(USART2, USART_IT_RXNE, ENABLE);
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// initialize the fifos
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TXSerialfifoinit2();
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RXSerialfifoinit2();
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}
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uint8_t AvailUSART2(void)
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{
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if (RXSerialfifolevel2() > 0U)
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return 1U;
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else
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return 0U;
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}
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uint8_t ReadUSART2(void)
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{
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uint8_t data_c = RXSerialfifo2[RXSerialfifotail2];
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RXSerialfifotail2++;
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if (RXSerialfifotail2 >= RX_SERIAL_FIFO_SIZE)
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RXSerialfifotail2 = 0U;
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return data_c;
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}
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void WriteUSART2(const uint8_t* data, uint16_t length)
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{
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for (uint16_t i = 0U; i < length; i++)
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TXSerialfifoput2(data[i]);
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USART_ITConfig(USART2, USART_IT_TXE, ENABLE);
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}
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#endif
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/* ************* USART3 ***************** */
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#if defined(STM32F4_DISCOVERY) || defined(STM32F4_PI)
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volatile uint32_t intcount3;
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volatile uint8_t TXSerialfifo3[TX_SERIAL_FIFO_SIZE];
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volatile uint8_t RXSerialfifo3[RX_SERIAL_FIFO_SIZE];
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volatile uint16_t TXSerialfifohead3, TXSerialfifotail3;
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volatile uint16_t RXSerialfifohead3, RXSerialfifotail3;
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// Init queues
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void TXSerialfifoinit3()
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@ -408,8 +609,16 @@ void WriteUSART3(const uint8_t* data, uint16_t length)
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USART_ITConfig(USART3, USART_IT_TXE, ENABLE);
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}
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#endif
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/* ************* UART5 ***************** */
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volatile uint32_t intcount5;
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volatile uint8_t TXSerialfifo5[TX_SERIAL_FIFO_SIZE];
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volatile uint8_t RXSerialfifo5[RX_SERIAL_FIFO_SIZE];
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volatile uint16_t TXSerialfifohead5, TXSerialfifotail5;
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volatile uint16_t RXSerialfifohead5, RXSerialfifotail5;
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// Init queues
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void TXSerialfifoinit5()
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{
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@ -515,7 +724,7 @@ void UART5_IRQHandler()
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void InitUART5(int speed)
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{
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// USART5 - TXD PC12 - RXD PD2
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// UART5 - TXD PC12 - RXD PD2
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GPIO_InitTypeDef GPIO_InitStructure;
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USART_InitTypeDef USART_InitStructure;
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NVIC_InitTypeDef NVIC_InitStructure;
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@ -601,6 +810,8 @@ void CSerialPort::beginInt(uint8_t n, int speed)
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InitUSART3(speed);
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#elif defined(STM32F4_PI)
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InitUSART1(speed);
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#elif defined(STM32F4_NUCLEO)
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InitUSART2(speed);
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#endif
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break;
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case 3U:
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@ -619,6 +830,8 @@ int CSerialPort::availableInt(uint8_t n)
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return AvailUSART3();
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#elif defined(STM32F4_PI)
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return AvailUSART1();
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#elif defined(STM32F4_NUCLEO)
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return AvailUSART2();
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#endif
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case 3U:
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return AvailUART5();
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@ -635,6 +848,8 @@ uint8_t CSerialPort::readInt(uint8_t n)
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return ReadUSART3();
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#elif defined(STM32F4_PI)
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return ReadUSART1();
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#elif defined(STM32F4_NUCLEO)
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return ReadUSART2();
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#endif
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case 3U:
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return ReadUART5();
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@ -655,6 +870,10 @@ void CSerialPort::writeInt(uint8_t n, const uint8_t* data, uint16_t length, bool
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WriteUSART1(data, length);
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if (flush)
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TXSerialFlush1();
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#elif defined(STM32F4_NUCLEO)
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WriteUSART2(data, length);
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if (flush)
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TXSerialFlush2();
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#endif
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break;
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case 3U:
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