mirror of
https://github.com/g4klx/MMDVM.git
synced 2026-05-07 13:37:48 +00:00
Remove UART habndling Copy/Paste code
This commit is contained in:
Geoffrey Merck
parent
f14222e77d
commit
04d0b15545
3 changed files with 240 additions and 585 deletions
634
SerialSTM.cpp
634
SerialSTM.cpp
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@ -39,9 +39,7 @@ UART5 - TXD PC12 - RXD PD2 (Discovery, MMDVM-Pi, MMDVM-Pi F722 board, MMDVM-F4M
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#if defined(STM32F4XX) || defined(STM32F7XX)
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#define TX_SERIAL_FIFO_SIZE 512U
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#define RX_SERIAL_FIFO_SIZE 512U
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#include "STMUART.h"
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extern "C" {
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void USART1_IRQHandler();
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void USART2_IRQHandler();
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@ -52,111 +50,12 @@ extern "C" {
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/* ************* USART1 ***************** */
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#if defined(STM32F4_PI) || defined(STM32F4_F4M) || defined(STM32F722_F7M) || defined(STM32F722_PI) || defined(STM32F722_RPT_HAT) || defined(STM32F4_DVM) || (defined(STM32F4_NUCLEO) && defined(STM32F4_NUCLEO_ARDUINO_HEADER)) || defined(DRCC_DVM)
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volatile uint8_t TXSerialfifo1[TX_SERIAL_FIFO_SIZE];
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volatile uint8_t RXSerialfifo1[RX_SERIAL_FIFO_SIZE];
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volatile uint16_t TXSerialfifohead1, TXSerialfifotail1;
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volatile uint16_t RXSerialfifohead1, RXSerialfifotail1;
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// Init queues
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void TXSerialfifoinit1()
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{
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TXSerialfifohead1 = 0U;
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TXSerialfifotail1 = 0U;
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}
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void RXSerialfifoinit1()
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{
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RXSerialfifohead1 = 0U;
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RXSerialfifotail1 = 0U;
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}
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// How full is queue
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// TODO decide if how full or how empty is preferred info to return
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uint16_t TXSerialfifolevel1()
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{
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uint32_t tail = TXSerialfifotail1;
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uint32_t head = TXSerialfifohead1;
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if (tail > head)
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return TX_SERIAL_FIFO_SIZE + head - tail;
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else
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return head - tail;
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}
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uint16_t RXSerialfifolevel1()
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{
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uint32_t tail = RXSerialfifotail1;
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uint32_t head = RXSerialfifohead1;
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if (tail > head)
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return RX_SERIAL_FIFO_SIZE + head - tail;
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else
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return head - tail;
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}
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// Flushes the transmit shift register
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// warning: this call is blocking
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void TXSerialFlush1()
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{
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// wait until the TXE shows the shift register is empty
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while (USART_GetITStatus(USART1, USART_FLAG_TXE))
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;
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}
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uint8_t TXSerialfifoput1(uint8_t next)
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{
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if (TXSerialfifolevel1() < TX_SERIAL_FIFO_SIZE) {
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TXSerialfifo1[TXSerialfifohead1] = next;
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TXSerialfifohead1++;
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if (TXSerialfifohead1 >= TX_SERIAL_FIFO_SIZE)
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TXSerialfifohead1 = 0U;
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// make sure transmit interrupts are enabled as long as there is data to send
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USART_ITConfig(USART1, USART_IT_TXE, ENABLE);
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return 1U;
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} else {
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return 0U; // signal an overflow occurred by returning a zero count
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}
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}
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static CSTMUART m_USART1;
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void USART1_IRQHandler()
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{
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uint8_t c;
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if (USART_GetITStatus(USART1, USART_IT_RXNE)) {
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c = (uint8_t) USART_ReceiveData(USART1);
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if (RXSerialfifolevel1() < RX_SERIAL_FIFO_SIZE) {
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RXSerialfifo1[RXSerialfifohead1] = c;
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RXSerialfifohead1++;
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if (RXSerialfifohead1 >= RX_SERIAL_FIFO_SIZE)
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RXSerialfifohead1 = 0U;
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} else {
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// TODO - do something if rx fifo is full?
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}
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USART_ClearITPendingBit(USART1, USART_IT_RXNE);
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}
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if (USART_GetITStatus(USART1, USART_IT_TXE)) {
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c = 0U;
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if (TXSerialfifohead1 != TXSerialfifotail1) { // if the fifo is not empty
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c = TXSerialfifo1[TXSerialfifotail1];
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TXSerialfifotail1++;
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if (TXSerialfifotail1 >= TX_SERIAL_FIFO_SIZE)
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TXSerialfifotail1 = 0U;
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USART_SendData(USART1, c);
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} else { // if there's no more data to transmit then turn off TX interrupts
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USART_ITConfig(USART1, USART_IT_TXE, DISABLE);
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}
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USART_ClearITPendingBit(USART1, USART_IT_TXE);
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}
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m_USART1.handleIRQ();
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}
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void InitUSART1(int speed)
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@ -184,7 +83,7 @@ void InitUSART1(int speed)
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GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9 | GPIO_Pin_10; // Tx | Rx
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GPIO_InitStructure.GPIO_Speed = GPIO_Fast_Speed;
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GPIO_InitStructure.GPIO_Speed = GPIO_High_Speed;
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GPIO_Init(GPIOA, &GPIO_InitStructure);
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// Configure USART baud rate
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@ -201,41 +100,7 @@ void InitUSART1(int speed)
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USART_ITConfig(USART1, USART_IT_RXNE, ENABLE);
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// initialize the fifos
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TXSerialfifoinit1();
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RXSerialfifoinit1();
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}
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uint8_t AvailUSART1()
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{
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if (RXSerialfifolevel1() > 0U)
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return 1U;
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else
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return 0U;
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}
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int AvailForWriteUSART1()
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{
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return TX_SERIAL_FIFO_SIZE - TXSerialfifolevel1();
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}
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uint8_t ReadUSART1()
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{
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uint8_t data_c = RXSerialfifo1[RXSerialfifotail1];
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RXSerialfifotail1++;
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if (RXSerialfifotail1 >= RX_SERIAL_FIFO_SIZE)
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RXSerialfifotail1 = 0U;
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return data_c;
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}
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void WriteUSART1(const uint8_t* data, uint16_t length)
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{
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for (uint16_t i = 0U; i < length; i++)
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TXSerialfifoput1(data[i]);
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USART_ITConfig(USART1, USART_IT_TXE, ENABLE);
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m_USART1.init(USART1);
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}
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#endif
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@ -243,111 +108,12 @@ void WriteUSART1(const uint8_t* data, uint16_t length)
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/* ************* USART2 ***************** */
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#if defined(STM32F4_NUCLEO) || defined(STM32F4_RPT_HAT_TGO) || defined(DRCC_DVM)
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volatile uint8_t TXSerialfifo2[TX_SERIAL_FIFO_SIZE];
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volatile uint8_t RXSerialfifo2[RX_SERIAL_FIFO_SIZE];
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volatile uint16_t TXSerialfifohead2, TXSerialfifotail2;
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volatile uint16_t RXSerialfifohead2, RXSerialfifotail2;
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static CSTMUART m_USART2;
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// Init queues
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void TXSerialfifoinit2()
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{
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TXSerialfifohead2 = 0U;
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TXSerialfifotail2 = 0U;
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}
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void RXSerialfifoinit2()
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{
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RXSerialfifohead2 = 0U;
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RXSerialfifotail2 = 0U;
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}
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// How full is queue
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// TODO decide if how full or how empty is preferred info to return
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uint16_t TXSerialfifolevel2()
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{
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uint32_t tail = TXSerialfifotail2;
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uint32_t head = TXSerialfifohead2;
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if (tail > head)
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return TX_SERIAL_FIFO_SIZE + head - tail;
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else
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return head - tail;
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}
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uint16_t RXSerialfifolevel2()
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{
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uint32_t tail = RXSerialfifotail2;
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uint32_t head = RXSerialfifohead2;
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if (tail > head)
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return RX_SERIAL_FIFO_SIZE + head - tail;
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else
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return head - tail;
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}
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// Flushes the transmit shift register
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// warning: this call is blocking
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void TXSerialFlush2()
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{
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// wait until the TXE shows the shift register is empty
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while (USART_GetITStatus(USART2, USART_FLAG_TXE))
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;
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}
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uint8_t TXSerialfifoput2(uint8_t next)
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{
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if (TXSerialfifolevel2() < TX_SERIAL_FIFO_SIZE) {
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TXSerialfifo2[TXSerialfifohead2] = next;
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TXSerialfifohead2++;
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if (TXSerialfifohead2 >= TX_SERIAL_FIFO_SIZE)
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TXSerialfifohead2 = 0U;
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// make sure transmit interrupts are enabled as long as there is data to send
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USART_ITConfig(USART2, USART_IT_TXE, ENABLE);
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return 1U;
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} else {
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return 0U; // signal an overflow occurred by returning a zero count
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}
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}
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void USART2_IRQHandler()
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{
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uint8_t c;
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if (USART_GetITStatus(USART2, USART_IT_RXNE)) {
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c = (uint8_t) USART_ReceiveData(USART2);
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if (RXSerialfifolevel2() < RX_SERIAL_FIFO_SIZE) {
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RXSerialfifo2[RXSerialfifohead2] = c;
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RXSerialfifohead2++;
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if (RXSerialfifohead2 >= RX_SERIAL_FIFO_SIZE)
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RXSerialfifohead2 = 0U;
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} else {
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// TODO - do something if rx fifo is full?
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}
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USART_ClearITPendingBit(USART2, USART_IT_RXNE);
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}
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if (USART_GetITStatus(USART2, USART_IT_TXE)) {
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c = 0U;
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if (TXSerialfifohead2 != TXSerialfifotail2) { // if the fifo is not empty
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c = TXSerialfifo2[TXSerialfifotail2];
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TXSerialfifotail2++;
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if (TXSerialfifotail2 >= TX_SERIAL_FIFO_SIZE)
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TXSerialfifotail2 = 0U;
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USART_SendData(USART2, c);
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} else { // if there's no more data to transmit then turn off TX interrupts
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USART_ITConfig(USART2, USART_IT_TXE, DISABLE);
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}
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USART_ClearITPendingBit(USART2, USART_IT_TXE);
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}
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m_USART2.handleIRQ();
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}
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void InitUSART2(int speed)
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@ -392,41 +158,7 @@ void InitUSART2(int speed)
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USART_ITConfig(USART2, USART_IT_RXNE, ENABLE);
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// initialize the fifos
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TXSerialfifoinit2();
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RXSerialfifoinit2();
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}
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uint8_t AvailUSART2()
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{
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if (RXSerialfifolevel2() > 0U)
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return 1U;
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else
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return 0U;
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}
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int AvailForWriteUSART2()
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{
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return TX_SERIAL_FIFO_SIZE - TXSerialfifolevel2();
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}
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uint8_t ReadUSART2()
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{
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uint8_t data_c = RXSerialfifo2[RXSerialfifotail2];
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RXSerialfifotail2++;
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if (RXSerialfifotail2 >= RX_SERIAL_FIFO_SIZE)
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RXSerialfifotail2 = 0U;
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return data_c;
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}
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void WriteUSART2(const uint8_t* data, uint16_t length)
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{
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for (uint16_t i = 0U; i < length; i++)
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TXSerialfifoput2(data[i]);
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USART_ITConfig(USART2, USART_IT_TXE, ENABLE);
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m_USART2.init(USART2);
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}
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#endif
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@ -434,111 +166,11 @@ void WriteUSART2(const uint8_t* data, uint16_t length)
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/* ************* USART3 ***************** */
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#if defined(STM32F4_DISCOVERY) || defined(STM32F7_NUCLEO)
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volatile uint8_t TXSerialfifo3[TX_SERIAL_FIFO_SIZE];
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volatile uint8_t RXSerialfifo3[RX_SERIAL_FIFO_SIZE];
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volatile uint16_t TXSerialfifohead3, TXSerialfifotail3;
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volatile uint16_t RXSerialfifohead3, RXSerialfifotail3;
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// Init queues
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void TXSerialfifoinit3()
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{
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TXSerialfifohead3 = 0U;
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TXSerialfifotail3 = 0U;
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}
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void RXSerialfifoinit3()
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{
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RXSerialfifohead3 = 0U;
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RXSerialfifotail3 = 0U;
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}
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// How full is queue
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// TODO decide if how full or how empty is preferred info to return
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uint16_t TXSerialfifolevel3()
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{
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uint32_t tail = TXSerialfifotail3;
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uint32_t head = TXSerialfifohead3;
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if (tail > head)
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return TX_SERIAL_FIFO_SIZE + head - tail;
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else
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return head - tail;
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}
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uint16_t RXSerialfifolevel3()
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{
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uint32_t tail = RXSerialfifotail3;
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uint32_t head = RXSerialfifohead3;
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if (tail > head)
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return RX_SERIAL_FIFO_SIZE + head - tail;
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else
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return head - tail;
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}
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// Flushes the transmit shift register
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// warning: this call is blocking
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void TXSerialFlush3()
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{
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// wait until the TXE shows the shift register is empty
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while (USART_GetITStatus(USART3, USART_FLAG_TXE))
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;
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}
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uint8_t TXSerialfifoput3(uint8_t next)
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{
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if (TXSerialfifolevel3() < TX_SERIAL_FIFO_SIZE) {
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TXSerialfifo3[TXSerialfifohead3] = next;
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TXSerialfifohead3++;
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if (TXSerialfifohead3 >= TX_SERIAL_FIFO_SIZE)
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TXSerialfifohead3 = 0U;
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// make sure transmit interrupts are enabled as long as there is data to send
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USART_ITConfig(USART3, USART_IT_TXE, ENABLE);
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return 1U;
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} else {
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return 0U; // signal an overflow occurred by returning a zero count
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}
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}
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static CSTMUART m_USART3;
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void USART3_IRQHandler()
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{
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uint8_t c;
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if (USART_GetITStatus(USART3, USART_IT_RXNE)) {
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c = (uint8_t) USART_ReceiveData(USART3);
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if (RXSerialfifolevel3() < RX_SERIAL_FIFO_SIZE) {
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RXSerialfifo3[RXSerialfifohead3] = c;
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RXSerialfifohead3++;
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if (RXSerialfifohead3 >= RX_SERIAL_FIFO_SIZE)
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RXSerialfifohead3 = 0U;
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} else {
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// TODO - do something if rx fifo is full?
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}
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USART_ClearITPendingBit(USART3, USART_IT_RXNE);
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}
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if (USART_GetITStatus(USART3, USART_IT_TXE)) {
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c = 0U;
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if (TXSerialfifohead3 != TXSerialfifotail3) { // if the fifo is not empty
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c = TXSerialfifo3[TXSerialfifotail3];
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TXSerialfifotail3++;
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if (TXSerialfifotail3 >= TX_SERIAL_FIFO_SIZE)
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TXSerialfifotail3 = 0U;
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USART_SendData(USART3, c);
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} else { // if there's no more data to transmit then turn off TX interrupts
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USART_ITConfig(USART3, USART_IT_TXE, DISABLE);
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}
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USART_ClearITPendingBit(USART3, USART_IT_TXE);
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}
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m_USART3.handleIRQ();
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}
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#if defined(STM32F7_NUCLEO)
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@ -600,41 +232,7 @@ void InitUSART3(int speed)
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USART_ITConfig(USART3, USART_IT_RXNE, ENABLE);
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// initialize the fifos
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TXSerialfifoinit3();
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RXSerialfifoinit3();
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}
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uint8_t AvailUSART3()
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{
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if (RXSerialfifolevel3() > 0U)
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return 1U;
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else
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return 0U;
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}
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int AvailForWriteUSART3()
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{
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return TX_SERIAL_FIFO_SIZE - TXSerialfifolevel3();
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}
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uint8_t ReadUSART3()
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{
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uint8_t data_c = RXSerialfifo3[RXSerialfifotail3];
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RXSerialfifotail3++;
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if (RXSerialfifotail3 >= RX_SERIAL_FIFO_SIZE)
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RXSerialfifotail3 = 0U;
|
||||
|
||||
return data_c;
|
||||
}
|
||||
|
||||
void WriteUSART3(const uint8_t* data, uint16_t length)
|
||||
{
|
||||
for (uint16_t i = 0U; i < length; i++)
|
||||
TXSerialfifoput3(data[i]);
|
||||
|
||||
USART_ITConfig(USART3, USART_IT_TXE, ENABLE);
|
||||
m_USART3.init(USART3);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
@ -642,111 +240,11 @@ void WriteUSART3(const uint8_t* data, uint16_t length)
|
|||
/* ************* UART5 ***************** */
|
||||
#if !(defined(STM32F4_NUCLEO) && defined(STM32F4_NUCLEO_ARDUINO_HEADER))
|
||||
|
||||
volatile uint8_t TXSerialfifo5[TX_SERIAL_FIFO_SIZE];
|
||||
volatile uint8_t RXSerialfifo5[RX_SERIAL_FIFO_SIZE];
|
||||
volatile uint16_t TXSerialfifohead5, TXSerialfifotail5;
|
||||
volatile uint16_t RXSerialfifohead5, RXSerialfifotail5;
|
||||
|
||||
// Init queues
|
||||
void TXSerialfifoinit5()
|
||||
{
|
||||
TXSerialfifohead5 = 0U;
|
||||
TXSerialfifotail5 = 0U;
|
||||
}
|
||||
|
||||
void RXSerialfifoinit5()
|
||||
{
|
||||
RXSerialfifohead5 = 0U;
|
||||
RXSerialfifotail5 = 0U;
|
||||
}
|
||||
|
||||
// How full is queue
|
||||
// TODO decide if how full or how empty is preferred info to return
|
||||
uint16_t TXSerialfifolevel5()
|
||||
{
|
||||
uint32_t tail = TXSerialfifotail5;
|
||||
uint32_t head = TXSerialfifohead5;
|
||||
|
||||
if (tail > head)
|
||||
return TX_SERIAL_FIFO_SIZE + head - tail;
|
||||
else
|
||||
return head - tail;
|
||||
}
|
||||
|
||||
uint16_t RXSerialfifolevel5()
|
||||
{
|
||||
uint32_t tail = RXSerialfifotail5;
|
||||
uint32_t head = RXSerialfifohead5;
|
||||
|
||||
if (tail > head)
|
||||
return RX_SERIAL_FIFO_SIZE + head - tail;
|
||||
else
|
||||
return head - tail;
|
||||
}
|
||||
|
||||
// Flushes the transmit shift register
|
||||
// warning: this call is blocking
|
||||
void TXSerialFlush5()
|
||||
{
|
||||
// wait until the TXE shows the shift register is empty
|
||||
while (USART_GetITStatus(UART5, USART_FLAG_TXE))
|
||||
;
|
||||
}
|
||||
|
||||
uint8_t TXSerialfifoput5(uint8_t next)
|
||||
{
|
||||
if (TXSerialfifolevel5() < TX_SERIAL_FIFO_SIZE) {
|
||||
TXSerialfifo5[TXSerialfifohead5] = next;
|
||||
|
||||
TXSerialfifohead5++;
|
||||
if (TXSerialfifohead5 >= TX_SERIAL_FIFO_SIZE)
|
||||
TXSerialfifohead5 = 0U;
|
||||
|
||||
// make sure transmit interrupts are enabled as long as there is data to send
|
||||
USART_ITConfig(UART5, USART_IT_TXE, ENABLE);
|
||||
return 1U;
|
||||
} else {
|
||||
return 0U; // signal an overflow occurred by returning a zero count
|
||||
}
|
||||
}
|
||||
static CSTMUART m_UART5;
|
||||
|
||||
void UART5_IRQHandler()
|
||||
{
|
||||
uint8_t c;
|
||||
|
||||
if (USART_GetITStatus(UART5, USART_IT_RXNE)) {
|
||||
c = (uint8_t) USART_ReceiveData(UART5);
|
||||
|
||||
if (RXSerialfifolevel5() < RX_SERIAL_FIFO_SIZE) {
|
||||
RXSerialfifo5[RXSerialfifohead5] = c;
|
||||
|
||||
RXSerialfifohead5++;
|
||||
if (RXSerialfifohead5 >= RX_SERIAL_FIFO_SIZE)
|
||||
RXSerialfifohead5 = 0U;
|
||||
} else {
|
||||
// TODO - do something if rx fifo is full?
|
||||
}
|
||||
|
||||
USART_ClearITPendingBit(UART5, USART_IT_RXNE);
|
||||
}
|
||||
|
||||
if (USART_GetITStatus(UART5, USART_IT_TXE)) {
|
||||
c = 0U;
|
||||
|
||||
if (TXSerialfifohead5 != TXSerialfifotail5) { // if the fifo is not empty
|
||||
c = TXSerialfifo5[TXSerialfifotail5];
|
||||
|
||||
TXSerialfifotail5++;
|
||||
if (TXSerialfifotail5 >= TX_SERIAL_FIFO_SIZE)
|
||||
TXSerialfifotail5 = 0U;
|
||||
|
||||
USART_SendData(UART5, c);
|
||||
} else { // if there's no more data to transmit then turn off TX interrupts
|
||||
USART_ITConfig(UART5, USART_IT_TXE, DISABLE);
|
||||
}
|
||||
|
||||
USART_ClearITPendingBit(UART5, USART_IT_TXE);
|
||||
}
|
||||
m_UART5.handleIRQ();
|
||||
}
|
||||
|
||||
void InitUART5(int speed)
|
||||
|
|
@ -795,41 +293,7 @@ void InitUART5(int speed)
|
|||
|
||||
USART_ITConfig(UART5, USART_IT_RXNE, ENABLE);
|
||||
|
||||
// initialize the fifos
|
||||
TXSerialfifoinit5();
|
||||
RXSerialfifoinit5();
|
||||
}
|
||||
|
||||
uint8_t AvailUART5()
|
||||
{
|
||||
if (RXSerialfifolevel5() > 0U)
|
||||
return 1U;
|
||||
else
|
||||
return 0U;
|
||||
}
|
||||
|
||||
int AvailForWriteUART5()
|
||||
{
|
||||
return TX_SERIAL_FIFO_SIZE - TXSerialfifolevel5();
|
||||
}
|
||||
|
||||
uint8_t ReadUART5()
|
||||
{
|
||||
uint8_t data_c = RXSerialfifo5[RXSerialfifotail5];
|
||||
|
||||
RXSerialfifotail5++;
|
||||
if (RXSerialfifotail5 >= RX_SERIAL_FIFO_SIZE)
|
||||
RXSerialfifotail5 = 0U;
|
||||
|
||||
return data_c;
|
||||
}
|
||||
|
||||
void WriteUART5(const uint8_t* data, uint16_t length)
|
||||
{
|
||||
for (uint16_t i = 0U; i < length; i++)
|
||||
TXSerialfifoput5(data[i]);
|
||||
|
||||
USART_ITConfig(UART5, USART_IT_TXE, ENABLE);
|
||||
m_UART5.init(UART5);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
@ -868,21 +332,21 @@ int CSerialPort::availableInt(uint8_t n)
|
|||
switch (n) {
|
||||
case 1U:
|
||||
#if defined(STM32F4_DISCOVERY) || defined(STM32F7_NUCLEO)
|
||||
return AvailUSART3();
|
||||
return m_USART3.availble();//AvailUSART3();
|
||||
#elif defined(STM32F4_PI) || defined(STM32F4_F4M) || defined(STM32F722_PI) || defined(STM32F722_F7M) || defined(STM32F722_RPT_HAT) || defined(STM32F4_DVM)
|
||||
return AvailUSART1();
|
||||
return m_USART1.available();//AvailUSART1();
|
||||
#elif defined(STM32F4_NUCLEO) || defined(STM32F4_RPT_HAT_TGO)
|
||||
return AvailUSART2();
|
||||
return m_USART2.available();//AvailUSART2();
|
||||
#elif defined(DRCC_DVM)
|
||||
return AvailUSART1();
|
||||
return m_USART1.available();//AvailUSART1();
|
||||
#endif
|
||||
case 3U:
|
||||
#if defined(STM32F4_NUCLEO) && defined(STM32F4_NUCLEO_ARDUINO_HEADER)
|
||||
return AvailUSART1();
|
||||
return m_USART1.available(); //AvailUSART1();
|
||||
#elif defined(DRCC_DVM)
|
||||
return AvailUSART2();
|
||||
return m_USART2.available(); //AvailUSART2();
|
||||
#else
|
||||
return AvailUART5();
|
||||
return m_UART5.available();//AvailUART5();
|
||||
#endif
|
||||
default:
|
||||
return 0;
|
||||
|
|
@ -894,21 +358,21 @@ int CSerialPort::availableForWriteInt(uint8_t n)
|
|||
switch (n) {
|
||||
case 1U:
|
||||
#if defined(STM32F4_DISCOVERY) || defined(STM32F7_NUCLEO)
|
||||
return AvailForWriteUSART3();
|
||||
return m_USART3.availableForWrite(); //AvailForWriteUSART3();
|
||||
#elif defined(STM32F4_PI) || defined(STM32F4_F4M) || defined(STM32F722_PI) || defined(STM32F722_F7M) || defined(STM32F722_RPT_HAT) || defined(STM32F4_DVM)
|
||||
return AvailForWriteUSART1();
|
||||
return m_USART1.availableForWrite(); //AvailForWriteUSART1();
|
||||
#elif defined(STM32F4_NUCLEO) || defined(STM32F4_RPT_HAT_TGO)
|
||||
return AvailForWriteUSART2();
|
||||
return m_USART2.availableForWrite();//AvailForWriteUSART2();
|
||||
#elif defined(DRCC_DVM)
|
||||
return AvailForWriteUSART1();
|
||||
return m_USART1.availableForWrite();//AvailForWriteUSART1();
|
||||
#endif
|
||||
case 3U:
|
||||
#if defined(STM32F4_NUCLEO) && defined(STM32F4_NUCLEO_ARDUINO_HEADER)
|
||||
return AvailForWriteUSART1();
|
||||
return m_USART1.availableForWrite(); //AvailForWriteUSART1();
|
||||
#elif defined(DRCC_DVM)
|
||||
AvailForWriteUSART2();
|
||||
return m_USART2.availableForWrite();//AvailForWriteUSART2();
|
||||
#else
|
||||
return AvailForWriteUART5();
|
||||
return m_UART5.availableForWrite();//AvailForWriteUART5();
|
||||
#endif
|
||||
default:
|
||||
return 0;
|
||||
|
|
@ -920,21 +384,21 @@ uint8_t CSerialPort::readInt(uint8_t n)
|
|||
switch (n) {
|
||||
case 1U:
|
||||
#if defined(STM32F4_DISCOVERY) || defined(STM32F7_NUCLEO)
|
||||
return ReadUSART3();
|
||||
return m_USART3.read();//ReadUSART3();
|
||||
#elif defined(STM32F4_PI) || defined(STM32F4_F4M) || defined(STM32F722_PI) || defined(STM32F722_F7M) || defined(STM32F722_RPT_HAT) || defined(STM32F4_DVM)
|
||||
return ReadUSART1();
|
||||
return m_USART1.read();//ReadUSART1();
|
||||
#elif defined(STM32F4_NUCLEO) || defined(STM32F4_RPT_HAT_TGO)
|
||||
return ReadUSART2();
|
||||
return m_USART2.read();//ReadUSART2();
|
||||
#elif defined(DRCC_DVM)
|
||||
return ReadUSART1();
|
||||
return m_USART1.read();//ReadUSART1();
|
||||
#endif
|
||||
case 3U:
|
||||
#if defined(STM32F4_NUCLEO) && defined(STM32F4_NUCLEO_ARDUINO_HEADER)
|
||||
return ReadUSART1();
|
||||
return m_USART1.read();//ReadUSART1();
|
||||
#elif defined(DRCC_DVM)
|
||||
return ReadUSART2();
|
||||
return m_USART2.read();//ReadUSART2();
|
||||
#else
|
||||
return ReadUART5();
|
||||
return m_UART5.read();//ReadUART5();
|
||||
#endif
|
||||
default:
|
||||
return 0U;
|
||||
|
|
@ -946,36 +410,36 @@ void CSerialPort::writeInt(uint8_t n, const uint8_t* data, uint16_t length, bool
|
|||
switch (n) {
|
||||
case 1U:
|
||||
#if defined(STM32F4_DISCOVERY) || defined(STM32F7_NUCLEO)
|
||||
WriteUSART3(data, length);
|
||||
m_USART3.write(data, length); //WriteUSART3(data, length);
|
||||
if (flush)
|
||||
TXSerialFlush3();
|
||||
m_USART3.flush();//TXSerialFlush3();
|
||||
#elif defined(STM32F4_PI) || defined(STM32F4_F4M) || defined(STM32F722_PI) || defined(STM32F722_F7M) || defined(STM32F722_RPT_HAT) || defined(STM32F4_DVM)
|
||||
WriteUSART1(data, length);
|
||||
m_USART1.write(data, length);//WriteUSART1(data, length);
|
||||
if (flush)
|
||||
TXSerialFlush1();
|
||||
m_USART1.flush();//TXSerialFlush1();
|
||||
#elif defined(STM32F4_NUCLEO) || defined(STM32F4_RPT_HAT_TGO)
|
||||
WriteUSART2(data, length);
|
||||
m_USART2.write(data, length);//WriteUSART2(data, length);
|
||||
if (flush)
|
||||
TXSerialFlush2();
|
||||
m_USART2.flush();//TXSerialFlush2();
|
||||
#elif defined(DRCC_DVM)
|
||||
WriteUSART1(data, length);
|
||||
m_USART1.write(data, length);//WriteUSART1(data, length);
|
||||
if (flush)
|
||||
TXSerialFlush1();
|
||||
m_USART1.flush();//TXSerialFlush1();
|
||||
#endif
|
||||
break;
|
||||
case 3U:
|
||||
#if defined(STM32F4_NUCLEO) && defined(STM32F4_NUCLEO_ARDUINO_HEADER)
|
||||
WriteUSART1(data, length);
|
||||
m_USART1.write(data, length); //WriteUSART1(data, length);
|
||||
if (flush)
|
||||
TXSerialFlush1();
|
||||
m_USART1.flush();
|
||||
#elif defined(DRCC_DVM)
|
||||
WriteUSART2(data, length);
|
||||
m_USART2.write(data, length);//WriteUSART2(data, length);
|
||||
if (flush)
|
||||
TXSerialFlush2();
|
||||
m_USART2.flush();//TXSerialFlush2();
|
||||
#else
|
||||
WriteUART5(data, length);
|
||||
m_UART5.write(data, length);//WriteUART5(data, length);
|
||||
if (flush)
|
||||
TXSerialFlush5();
|
||||
m_UART5.flush();//TXSerialFlush5();
|
||||
#endif
|
||||
break;
|
||||
default:
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue