mirror of
https://github.com/g4klx/DMRGateway.git
synced 2026-03-14 09:03:55 +01:00
Split RF and network processing functionality.
This commit is contained in:
parent
ee438fd2dc
commit
92bda23094
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@ -346,12 +346,12 @@ int CDMRGateway::run()
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FLCO flco = data.getFLCO();
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if (flco == FLCO_GROUP && slotNo == m_xlx1Slot && dstId == m_xlx1TG) {
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m_xlx1Rewrite->process(data);
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m_xlx1Rewrite->processRF(data);
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m_xlxNetwork1->write(data);
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status[slotNo] = DMRGWS_XLXREFLECTOR1;
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timer[slotNo]->start();
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} else if (flco == FLCO_GROUP && slotNo == m_xlx2Slot && dstId == m_xlx2TG) {
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m_xlx2Rewrite->process(data);
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m_xlx2Rewrite->processRF(data);
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m_xlxNetwork2->write(data);
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status[slotNo] = DMRGWS_XLXREFLECTOR2;
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timer[slotNo]->start();
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@ -423,7 +423,7 @@ int CDMRGateway::run()
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if (m_dmrNetwork1 != NULL) {
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// Rewrite the slot and/or TG or neither
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for (std::vector<IRewrite*>::iterator it = m_dmr1RFRewrites.begin(); it != m_dmr1RFRewrites.end(); ++it) {
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bool ret = (*it)->process(data);
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bool ret = (*it)->processRF(data);
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if (ret) {
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rewritten = true;
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break;
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@ -444,7 +444,7 @@ int CDMRGateway::run()
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if (m_dmrNetwork2 != NULL) {
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// Rewrite the slot and/or TG or neither
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for (std::vector<IRewrite*>::iterator it = m_dmr2RFRewrites.begin(); it != m_dmr2RFRewrites.end(); ++it) {
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bool ret = (*it)->process(data);
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bool ret = (*it)->processRF(data);
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if (ret) {
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rewritten = true;
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break;
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@ -468,7 +468,7 @@ int CDMRGateway::run()
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ret = m_xlxNetwork1->read(data);
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if (ret) {
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if (status[m_xlx1Slot] == DMRGWS_NONE || status[m_xlx1Slot] == DMRGWS_XLXREFLECTOR1) {
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bool ret = m_rpt1Rewrite->process(data);
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bool ret = m_rpt1Rewrite->processNet(data);
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if (ret) {
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m_repeater->write(data);
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status[m_xlx1Slot] = DMRGWS_XLXREFLECTOR1;
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@ -487,7 +487,7 @@ int CDMRGateway::run()
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ret = m_xlxNetwork2->read(data);
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if (ret) {
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if (status[m_xlx2Slot] == DMRGWS_NONE || status[m_xlx2Slot] == DMRGWS_XLXREFLECTOR2) {
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bool ret = m_rpt2Rewrite->process(data);
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bool ret = m_rpt2Rewrite->processNet(data);
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if (ret) {
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m_repeater->write(data);
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status[m_xlx2Slot] = DMRGWS_XLXREFLECTOR2;
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@ -509,7 +509,7 @@ int CDMRGateway::run()
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// Rewrite the slot and/or TG or neither
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bool rewritten = false;
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for (std::vector<IRewrite*>::iterator it = m_dmr1NetRewrites.begin(); it != m_dmr1NetRewrites.end(); ++it) {
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bool ret = (*it)->process(data);
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bool ret = (*it)->processNet(data);
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if (ret) {
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rewritten = true;
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break;
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@ -536,7 +536,7 @@ int CDMRGateway::run()
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// Rewrite the slot and/or TG or neither
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bool rewritten = false;
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for (std::vector<IRewrite*>::iterator it = m_dmr2NetRewrites.begin(); it != m_dmr2NetRewrites.end(); ++it) {
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bool ret = (*it)->process(data);
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bool ret = (*it)->processNet(data);
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if (ret) {
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rewritten = true;
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break;
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@ -25,7 +25,8 @@ class IRewrite {
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public:
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virtual ~IRewrite() = 0;
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virtual bool process(CDMRData& data) = 0;
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virtual bool processRF(CDMRData& data) = 0;
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virtual bool processNet(CDMRData& data) = 0;
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private:
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};
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@ -42,6 +42,16 @@ CRewritePC::~CRewritePC()
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{
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}
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bool CRewritePC::processRF(CDMRData& data)
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{
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return process(data);
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}
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bool CRewritePC::processNet(CDMRData& data)
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{
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return process(data);
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}
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bool CRewritePC::process(CDMRData& data)
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{
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FLCO flco = data.getFLCO();
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@ -29,7 +29,8 @@ public:
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CRewritePC(const char* name, unsigned int fromSlot, unsigned int fromId, unsigned int toSlot, unsigned int toId, unsigned int range);
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virtual ~CRewritePC();
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virtual bool process(CDMRData& data);
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virtual bool processRF(CDMRData& data);
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virtual bool processNet(CDMRData& data);
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private:
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const char* m_name;
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@ -41,6 +42,7 @@ private:
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CDMRLC m_lc;
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CDMREmbeddedData m_embeddedLC;
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bool process(CDMRData& data);
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void processHeader(CDMRData& data, unsigned int dstId, unsigned char dataType);
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void processVoice(CDMRData& data, unsigned int dstId);
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};
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@ -45,6 +45,16 @@ CRewriteSrc::~CRewriteSrc()
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{
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}
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bool CRewriteSrc::processRF(CDMRData& data)
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{
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return process(data);
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}
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bool CRewriteSrc::processNet(CDMRData& data)
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{
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return process(data);
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}
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bool CRewriteSrc::process(CDMRData& data)
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{
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FLCO flco = data.getFLCO();
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@ -29,7 +29,8 @@ public:
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CRewriteSrc(const char* name, unsigned int fromSlot, unsigned int fromId, unsigned int toSlot, unsigned int toTG, unsigned int range);
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virtual ~CRewriteSrc();
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virtual bool process(CDMRData& data);
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virtual bool processRF(CDMRData& data);
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virtual bool processNet(CDMRData& data);
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private:
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const char* m_name;
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@ -41,6 +42,7 @@ private:
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CDMRLC m_lc;
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CDMREmbeddedData m_embeddedLC;
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bool process(CDMRData& data);
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void processHeader(CDMRData& data, unsigned char dataType);
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void processVoice(CDMRData& data);
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};
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@ -42,6 +42,16 @@ CRewriteTG::~CRewriteTG()
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{
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}
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bool CRewriteTG::processRF(CDMRData& data)
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{
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return process(data);
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}
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bool CRewriteTG::processNet(CDMRData& data)
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{
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return process(data);
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}
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bool CRewriteTG::process(CDMRData& data)
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{
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FLCO flco = data.getFLCO();
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@ -29,7 +29,8 @@ public:
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CRewriteTG(const char*name, unsigned int fromSlot, unsigned int fromTG, unsigned int toSlot, unsigned int toTG, unsigned int range);
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virtual ~CRewriteTG();
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virtual bool process(CDMRData& data);
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virtual bool processRF(CDMRData& data);
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virtual bool processNet(CDMRData& data);
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private:
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const char* m_name;
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@ -41,6 +42,7 @@ private:
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CDMRLC m_lc;
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CDMREmbeddedData m_embeddedLC;
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bool process(CDMRData& data);
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void processHeader(CDMRData& data, unsigned int tg, unsigned char dataType);
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void processVoice(CDMRData& data, unsigned int tg);
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};
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@ -42,6 +42,16 @@ CRewriteType::~CRewriteType()
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{
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}
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bool CRewriteType::processRF(CDMRData& data)
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{
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return process(data);
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}
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bool CRewriteType::processNet(CDMRData& data)
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{
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return process(data);
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}
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bool CRewriteType::process(CDMRData& data)
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{
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FLCO flco = data.getFLCO();
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@ -29,7 +29,8 @@ public:
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CRewriteType(const char* name, unsigned int fromSlot, unsigned int fromTG, unsigned int toSlot, unsigned int toId);
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virtual ~CRewriteType();
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virtual bool process(CDMRData& data);
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virtual bool processRF(CDMRData& data);
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virtual bool processNet(CDMRData& data);
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private:
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const char* m_name;
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@ -40,6 +41,7 @@ private:
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CDMRLC m_lc;
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CDMREmbeddedData m_embeddedLC;
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bool process(CDMRData& data);
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void processHeader(CDMRData& data, unsigned char dataType);
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void processVoice(CDMRData& data);
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};
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