g4klx/DMRGateway
1
0
Fork 0
mirror of https://github.com/g4klx/DMRGateway.git synced 2026-04-07 07:23:50 +00:00
Code Issues Projects Releases Packages Wiki Activity

First stage of rationalising the rule tracing code.

Browse source
This commit is contained in:
Jonathan Naylor 2017-06-07 21:22:01 +01:00
parent 06a8b203ce
commit 87bee93b2b
15 changed files with 113 additions and 239 deletions
Download patch file Download diff file Expand all files Collapse all files

41
RewritePC.cpp
View file

@ -25,7 +25,7 @@
#include <cstdio>
#include <cassert>
CRewritePC::CRewritePC(const char* name, unsigned int fromSlot, unsigned int fromId, unsigned int toSlot, unsigned int toId, unsigned int range, bool trace) :
CRewritePC::CRewritePC(const char* name, unsigned int fromSlot, unsigned int fromId, unsigned int toSlot, unsigned int toId, unsigned int range) :
m_name(name),
m_fromSlot(fromSlot),
m_fromIdStart(fromId),
@ -33,7 +33,6 @@ m_fromIdEnd(fromId + range - 1U),
m_toSlot(toSlot),
m_toIdStart(toId),
m_toIdEnd(toId + range - 1U),
m_trace(trace),
m_lc(FLCO_USER_USER, 0U, 0U),
m_embeddedLC()
{
@ -45,40 +44,17 @@ CRewritePC::~CRewritePC()
{
}
bool CRewritePC::processRF(CDMRData& data)
{
bool ret = process(data);
if (m_trace)
LogDebug("Rule Trace,\tRewritePC from %s Slot=%u Dst=%u-%u: %s", m_name, m_fromSlot, m_fromIdStart, m_fromIdEnd, ret ? "matched" : "not matched");
if (m_trace && ret)
LogDebug("Rule Trace,\tRewritePC to %s Slot=%u Dst=%u-%u", m_name, m_toSlot, m_toIdStart, m_toIdEnd);
return ret;
}
bool CRewritePC::processNet(CDMRData& data)
{
bool ret = process(data);
if (m_trace)
LogDebug("Rule Trace,\tRewritePC from %s Slot=%u Dst=%u-%u: %s", m_name, m_fromSlot, m_fromIdStart, m_fromIdEnd, ret ? "matched" : "not matched");
if (m_trace && ret)
LogDebug("Rule Trace,\tRewritePC to %s Slot=%u Dst=%u-%u", m_name, m_toSlot, m_toIdStart, m_toIdEnd);
return ret;
}
bool CRewritePC::process(CDMRData& data)
bool CRewritePC::process(CDMRData& data, bool trace)
{
FLCO flco = data.getFLCO();
unsigned int dstId = data.getDstId();
unsigned int slotNo = data.getSlotNo();
if (flco != FLCO_USER_USER || slotNo != m_fromSlot || dstId < m_fromIdStart || dstId > m_fromIdEnd)
if (flco != FLCO_USER_USER || slotNo != m_fromSlot || dstId < m_fromIdStart || dstId > m_fromIdEnd) {
if (trace)
LogDebug("Rule Trace,\tRewritePC from %s Slot=%u Dst=%u-%u: not matched", m_name, m_fromSlot, m_fromIdStart, m_fromIdEnd);
return false;
}
if (m_fromSlot != m_toSlot)
data.setSlotNo(m_toSlot);
@ -107,6 +83,11 @@ bool CRewritePC::process(CDMRData& data)
}
}
if (trace) {
LogDebug("Rule Trace,\tRewritePC from %s Slot=%u Dst=%u-%u: not matched", m_name, m_fromSlot, m_fromIdStart, m_fromIdEnd);
LogDebug("Rule Trace,\tRewritePC to %s Slot=%u Dst=%u-%u", m_name, m_toSlot, m_toIdStart, m_toIdEnd);
}
return true;
}