g4klx/DMRGateway
1
0
Fork 0
mirror of https://github.com/g4klx/DMRGateway.git synced 2025-12-06 05:32:01 +01:00
Code Issues Actions Packages Projects Releases Wiki Activity

Allow for more rewrite processing options.

Browse source
This commit is contained in:
Jonathan Naylor 2020-04-03 15:10:41 +01:00
parent bd2366ed23
commit 73270ad7a5
22 changed files with 115 additions and 109 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

102
DMRGateway.cpp
View file

@ -615,19 +615,19 @@ int CDMRGateway::run()
if (trace) if (trace)
LogDebug("Rule Trace, RF transmission: Slot=%u Src=%u Dst=%s%u", slotNo, srcId, flco == FLCO_GROUP ? "TG" : "", dstId); LogDebug("Rule Trace, RF transmission: Slot=%u Src=%u Dst=%s%u", slotNo, srcId, flco == FLCO_GROUP ? "TG" : "", dstId);
bool rewritten = false; PROCESS_RESULT result = RESULT_UNMATCHED;
if (m_dmrNetwork1 != NULL) { if (m_dmrNetwork1 != NULL) {
// Rewrite the slot and/or TG or neither // Rewrite the slot and/or TG or neither
for (std::vector<CRewrite*>::iterator it = m_dmr1RFRewrites.begin(); it != m_dmr1RFRewrites.end(); ++it) { for (std::vector<CRewrite*>::iterator it = m_dmr1RFRewrites.begin(); it != m_dmr1RFRewrites.end(); ++it) {
bool ret = (*it)->process(data, trace); PROCESS_RESULT res = (*it)->process(data, trace);
if (ret) { if (res != RESULT_UNMATCHED) {
rewritten = true; result = res;
break; break;
} }
} }
if (rewritten) { if (result == RESULT_MATCHED) {
if (m_status[slotNo] == DMRGWS_NONE || m_status[slotNo] == DMRGWS_DMRNETWORK1) { if (m_status[slotNo] == DMRGWS_NONE || m_status[slotNo] == DMRGWS_DMRNETWORK1) {
rewrite(m_dmr1SrcRewrites, data, trace); rewrite(m_dmr1SrcRewrites, data, trace);
m_dmrNetwork1->write(data); m_dmrNetwork1->write(data);
@ -638,18 +638,18 @@ int CDMRGateway::run()
} }
} }
if (!rewritten) { if (result == RESULT_UNMATCHED) {
if (m_dmrNetwork2 != NULL) { if (m_dmrNetwork2 != NULL) {
// Rewrite the slot and/or TG or neither // Rewrite the slot and/or TG or neither
for (std::vector<CRewrite*>::iterator it = m_dmr2RFRewrites.begin(); it != m_dmr2RFRewrites.end(); ++it) { for (std::vector<CRewrite*>::iterator it = m_dmr2RFRewrites.begin(); it != m_dmr2RFRewrites.end(); ++it) {
bool ret = (*it)->process(data, trace); PROCESS_RESULT res = (*it)->process(data, trace);
if (ret) { if (res != RESULT_UNMATCHED) {
rewritten = true; result = res;
break; break;
} }
} }
if (rewritten) { if (result == RESULT_MATCHED) {
if (m_status[slotNo] == DMRGWS_NONE || m_status[slotNo] == DMRGWS_DMRNETWORK2) { if (m_status[slotNo] == DMRGWS_NONE || m_status[slotNo] == DMRGWS_DMRNETWORK2) {
rewrite(m_dmr2SrcRewrites, data, trace); rewrite(m_dmr2SrcRewrites, data, trace);
m_dmrNetwork2->write(data); m_dmrNetwork2->write(data);
@ -661,18 +661,18 @@ int CDMRGateway::run()
} }
} }
if (!rewritten) { if (result == RESULT_UNMATCHED) {
if (m_dmrNetwork3 != NULL) { if (m_dmrNetwork3 != NULL) {
// Rewrite the slot and/or TG or neither // Rewrite the slot and/or TG or neither
for (std::vector<CRewrite*>::iterator it = m_dmr3RFRewrites.begin(); it != m_dmr3RFRewrites.end(); ++it) { for (std::vector<CRewrite*>::iterator it = m_dmr3RFRewrites.begin(); it != m_dmr3RFRewrites.end(); ++it) {
bool ret = (*it)->process(data, trace); PROCESS_RESULT res = (*it)->process(data, trace);
if (ret) { if (res != RESULT_UNMATCHED) {
rewritten = true; result = res;
break; break;
} }
} }
if (rewritten) { if (result == RESULT_MATCHED) {
if (m_status[slotNo] == DMRGWS_NONE || m_status[slotNo] == DMRGWS_DMRNETWORK3) { if (m_status[slotNo] == DMRGWS_NONE || m_status[slotNo] == DMRGWS_DMRNETWORK3) {
rewrite(m_dmr3SrcRewrites, data, trace); rewrite(m_dmr3SrcRewrites, data, trace);
m_dmrNetwork3->write(data); m_dmrNetwork3->write(data);
@ -684,18 +684,18 @@ int CDMRGateway::run()
} }
} }
if (!rewritten) { if (result == RESULT_UNMATCHED) {
if (m_dmrNetwork4 != NULL) { if (m_dmrNetwork4 != NULL) {
// Rewrite the slot and/or TG or neither // Rewrite the slot and/or TG or neither
for (std::vector<CRewrite*>::iterator it = m_dmr4RFRewrites.begin(); it != m_dmr4RFRewrites.end(); ++it) { for (std::vector<CRewrite*>::iterator it = m_dmr4RFRewrites.begin(); it != m_dmr4RFRewrites.end(); ++it) {
bool ret = (*it)->process(data, trace); PROCESS_RESULT res = (*it)->process(data, trace);
if (ret) { if (res != RESULT_UNMATCHED) {
rewritten = true; result = res;
break; break;
} }
} }
if (rewritten) { if (result == RESULT_MATCHED) {
if (m_status[slotNo] == DMRGWS_NONE || m_status[slotNo] == DMRGWS_DMRNETWORK4) { if (m_status[slotNo] == DMRGWS_NONE || m_status[slotNo] == DMRGWS_DMRNETWORK4) {
rewrite(m_dmr4SrcRewrites, data, trace); rewrite(m_dmr4SrcRewrites, data, trace);
m_dmrNetwork4->write(data); m_dmrNetwork4->write(data);
@ -707,18 +707,18 @@ int CDMRGateway::run()
} }
} }
if (!rewritten) { if (result == RESULT_UNMATCHED) {
if (m_dmrNetwork5 != NULL) { if (m_dmrNetwork5 != NULL) {
// Rewrite the slot and/or TG or neither // Rewrite the slot and/or TG or neither
for (std::vector<CRewrite*>::iterator it = m_dmr5RFRewrites.begin(); it != m_dmr5RFRewrites.end(); ++it) { for (std::vector<CRewrite*>::iterator it = m_dmr5RFRewrites.begin(); it != m_dmr5RFRewrites.end(); ++it) {
bool ret = (*it)->process(data, trace); PROCESS_RESULT res = (*it)->process(data, trace);
if (ret) { if (res != RESULT_UNMATCHED) {
rewritten = true; result = res;
break; break;
} }
} }
if (rewritten) { if (result == RESULT_MATCHED) {
if (m_status[slotNo] == DMRGWS_NONE || m_status[slotNo] == DMRGWS_DMRNETWORK5) { if (m_status[slotNo] == DMRGWS_NONE || m_status[slotNo] == DMRGWS_DMRNETWORK5) {
rewrite(m_dmr5SrcRewrites, data, trace); rewrite(m_dmr5SrcRewrites, data, trace);
m_dmrNetwork5->write(data); m_dmrNetwork5->write(data);
@ -730,17 +730,17 @@ int CDMRGateway::run()
} }
} }
if (!rewritten) { if (result == RESULT_UNMATCHED) {
if (m_dmrNetwork1 != NULL) { if (m_dmrNetwork1 != NULL) {
for (std::vector<CRewrite*>::iterator it = m_dmr1Passalls.begin(); it != m_dmr1Passalls.end(); ++it) { for (std::vector<CRewrite*>::iterator it = m_dmr1Passalls.begin(); it != m_dmr1Passalls.end(); ++it) {
bool ret = (*it)->process(data, trace); PROCESS_RESULT res = (*it)->process(data, trace);
if (ret) { if (res != RESULT_UNMATCHED) {
rewritten = true; result = res;
break; break;
} }
} }
if (rewritten) { if (result == RESULT_MATCHED) {
if (m_status[slotNo] == DMRGWS_NONE || m_status[slotNo] == DMRGWS_DMRNETWORK1) { if (m_status[slotNo] == DMRGWS_NONE || m_status[slotNo] == DMRGWS_DMRNETWORK1) {
rewrite(m_dmr1SrcRewrites, data, trace); rewrite(m_dmr1SrcRewrites, data, trace);
m_dmrNetwork1->write(data); m_dmrNetwork1->write(data);
@ -752,17 +752,17 @@ int CDMRGateway::run()
} }
} }
if (!rewritten) { if (result == RESULT_UNMATCHED) {
if (m_dmrNetwork2 != NULL) { if (m_dmrNetwork2 != NULL) {
for (std::vector<CRewrite*>::iterator it = m_dmr2Passalls.begin(); it != m_dmr2Passalls.end(); ++it) { for (std::vector<CRewrite*>::iterator it = m_dmr2Passalls.begin(); it != m_dmr2Passalls.end(); ++it) {
bool ret = (*it)->process(data, trace); PROCESS_RESULT res = (*it)->process(data, trace);
if (ret) { if (res != RESULT_UNMATCHED) {
rewritten = true; result = res;
break; break;
} }
} }
if (rewritten) { if (result == RESULT_MATCHED) {
if (m_status[slotNo] == DMRGWS_NONE || m_status[slotNo] == DMRGWS_DMRNETWORK2) { if (m_status[slotNo] == DMRGWS_NONE || m_status[slotNo] == DMRGWS_DMRNETWORK2) {
rewrite(m_dmr2SrcRewrites, data, trace); rewrite(m_dmr2SrcRewrites, data, trace);
m_dmrNetwork2->write(data); m_dmrNetwork2->write(data);
@ -774,17 +774,17 @@ int CDMRGateway::run()
} }
} }
if (!rewritten) { if (result == RESULT_UNMATCHED) {
if (m_dmrNetwork3 != NULL) { if (m_dmrNetwork3 != NULL) {
for (std::vector<CRewrite*>::iterator it = m_dmr3Passalls.begin(); it != m_dmr3Passalls.end(); ++it) { for (std::vector<CRewrite*>::iterator it = m_dmr3Passalls.begin(); it != m_dmr3Passalls.end(); ++it) {
bool ret = (*it)->process(data, trace); PROCESS_RESULT res = (*it)->process(data, trace);
if (ret) { if (res != RESULT_UNMATCHED) {
rewritten = true; result = res;
break; break;
} }
} }
if (rewritten) { if (result == RESULT_MATCHED) {
if (m_status[slotNo] == DMRGWS_NONE || m_status[slotNo] == DMRGWS_DMRNETWORK3) { if (m_status[slotNo] == DMRGWS_NONE || m_status[slotNo] == DMRGWS_DMRNETWORK3) {
rewrite(m_dmr3SrcRewrites, data, trace); rewrite(m_dmr3SrcRewrites, data, trace);
m_dmrNetwork3->write(data); m_dmrNetwork3->write(data);
@ -796,17 +796,17 @@ int CDMRGateway::run()
} }
} }
if (!rewritten) { if (result == RESULT_UNMATCHED) {
if (m_dmrNetwork4 != NULL) { if (m_dmrNetwork4 != NULL) {
for (std::vector<CRewrite*>::iterator it = m_dmr4Passalls.begin(); it != m_dmr4Passalls.end(); ++it) { for (std::vector<CRewrite*>::iterator it = m_dmr4Passalls.begin(); it != m_dmr4Passalls.end(); ++it) {
bool ret = (*it)->process(data, trace); PROCESS_RESULT res = (*it)->process(data, trace);
if (ret) { if (res != RESULT_UNMATCHED) {
rewritten = true; result = res;
break; break;
} }
} }
if (rewritten) { if (result == RESULT_MATCHED) {
if (m_status[slotNo] == DMRGWS_NONE || m_status[slotNo] == DMRGWS_DMRNETWORK4) { if (m_status[slotNo] == DMRGWS_NONE || m_status[slotNo] == DMRGWS_DMRNETWORK4) {
rewrite(m_dmr4SrcRewrites, data, trace); rewrite(m_dmr4SrcRewrites, data, trace);
m_dmrNetwork4->write(data); m_dmrNetwork4->write(data);
@ -818,17 +818,17 @@ int CDMRGateway::run()
} }
} }
if (!rewritten) { if (result == RESULT_UNMATCHED) {
if (m_dmrNetwork5 != NULL) { if (m_dmrNetwork5 != NULL) {
for (std::vector<CRewrite*>::iterator it = m_dmr5Passalls.begin(); it != m_dmr5Passalls.end(); ++it) { for (std::vector<CRewrite*>::iterator it = m_dmr5Passalls.begin(); it != m_dmr5Passalls.end(); ++it) {
bool ret = (*it)->process(data, trace); PROCESS_RESULT res = (*it)->process(data, trace);
if (ret) { if (res != RESULT_UNMATCHED) {
rewritten = true; result = res;
break; break;
} }
} }
if (rewritten) { if (result == RESULT_MATCHED) {
if (m_status[slotNo] == DMRGWS_NONE || m_status[slotNo] == DMRGWS_DMRNETWORK5) { if (m_status[slotNo] == DMRGWS_NONE || m_status[slotNo] == DMRGWS_DMRNETWORK5) {
rewrite(m_dmr5SrcRewrites, data, trace); rewrite(m_dmr5SrcRewrites, data, trace);
m_dmrNetwork5->write(data); m_dmrNetwork5->write(data);
@ -840,7 +840,7 @@ int CDMRGateway::run()
} }
} }
if (!rewritten && trace) if (result == RESULT_UNMATCHED && trace)
LogDebug("Rule Trace,\tnot matched so rejected"); LogDebug("Rule Trace,\tnot matched so rejected");
} }
} }

6
PassAllPC.cpp
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (C) 2017 by Jonathan Naylor G4KLX * Copyright (C) 2017,2020 by Jonathan Naylor G4KLX
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by * it under the terms of the GNU General Public License as published by
@ -36,7 +36,7 @@ CPassAllPC::~CPassAllPC()
{ {
} }
bool CPassAllPC::process(CDMRData& data, bool trace) PROCESS_RESULT CPassAllPC::process(CDMRData& data, bool trace)
{ {
FLCO flco = data.getFLCO(); FLCO flco = data.getFLCO();
unsigned int slotNo = data.getSlotNo(); unsigned int slotNo = data.getSlotNo();
@ -46,5 +46,5 @@ bool CPassAllPC::process(CDMRData& data, bool trace)
if (trace) if (trace)
LogDebug("Rule Trace,\tPassAllPC %s Slot=%u: %s", m_name.c_str(), m_slot, ret ? "matched" : "not matched"); LogDebug("Rule Trace,\tPassAllPC %s Slot=%u: %s", m_name.c_str(), m_slot, ret ? "matched" : "not matched");
return ret; return ret ? RESULT_MATCHED : RESULT_UNMATCHED;
} }

4
PassAllPC.h
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (C) 2017 by Jonathan Naylor G4KLX * Copyright (C) 2017,2020 by Jonathan Naylor G4KLX
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by * it under the terms of the GNU General Public License as published by
@ -29,7 +29,7 @@ public:
CPassAllPC(const std::string& name, unsigned int slot); CPassAllPC(const std::string& name, unsigned int slot);
virtual ~CPassAllPC(); virtual ~CPassAllPC();
virtual bool process(CDMRData& data, bool trace); virtual PROCESS_RESULT process(CDMRData& data, bool trace);
private: private:
std::string m_name; std::string m_name;

6
PassAllTG.cpp
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (C) 2017 by Jonathan Naylor G4KLX * Copyright (C) 2017,2020 by Jonathan Naylor G4KLX
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by * it under the terms of the GNU General Public License as published by
@ -36,7 +36,7 @@ CPassAllTG::~CPassAllTG()
{ {
} }
bool CPassAllTG::process(CDMRData& data, bool trace) PROCESS_RESULT CPassAllTG::process(CDMRData& data, bool trace)
{ {
FLCO flco = data.getFLCO(); FLCO flco = data.getFLCO();
unsigned int slotNo = data.getSlotNo(); unsigned int slotNo = data.getSlotNo();
@ -46,5 +46,5 @@ bool CPassAllTG::process(CDMRData& data, bool trace)
if (trace) if (trace)
LogDebug("Rule Trace,\tPassAllTG %s Slot=%u: %s", m_name.c_str(), m_slot, ret ? "matched" : "not matched"); LogDebug("Rule Trace,\tPassAllTG %s Slot=%u: %s", m_name.c_str(), m_slot, ret ? "matched" : "not matched");
return ret; return ret ? RESULT_MATCHED : RESULT_UNMATCHED;
} }

4
PassAllTG.h
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (C) 2017 by Jonathan Naylor G4KLX * Copyright (C) 2017,2020 by Jonathan Naylor G4KLX
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by * it under the terms of the GNU General Public License as published by
@ -29,7 +29,7 @@ public:
CPassAllTG(const std::string& name, unsigned int slot); CPassAllTG(const std::string& name, unsigned int slot);
virtual ~CPassAllTG(); virtual ~CPassAllTG();
virtual bool process(CDMRData& data, bool trace); virtual PROCESS_RESULT process(CDMRData& data, bool trace);
private: private:
std::string m_name; std::string m_name;

10
Rewrite.h
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (C) 2017 by Jonathan Naylor G4KLX * Copyright (C) 2017,2020 by Jonathan Naylor G4KLX
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by * it under the terms of the GNU General Public License as published by
@ -23,12 +23,18 @@
#include "DMRData.h" #include "DMRData.h"
#include "DMRLC.h" #include "DMRLC.h"
enum PROCESS_RESULT {
RESULT_UNMATCHED,
RESULT_MATCHED,
RESULT_IGNORED
};
class CRewrite { class CRewrite {
public: public:
CRewrite(); CRewrite();
virtual ~CRewrite(); virtual ~CRewrite();
virtual bool process(CDMRData& data, bool trace) = 0; virtual PROCESS_RESULT process(CDMRData& data, bool trace) = 0;
protected: protected:
void processMessage(CDMRData& data); void processMessage(CDMRData& data);

8
RewriteDstId.cpp
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (C) 2017 by Jonathan Naylor G4KLX * Copyright (C) 2017,2020 by Jonathan Naylor G4KLX
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by * it under the terms of the GNU General Public License as published by
@ -35,7 +35,7 @@ CRewriteDstId::~CRewriteDstId()
{ {
} }
bool CRewriteDstId::process(CDMRData& data, bool trace) PROCESS_RESULT CRewriteDstId::process(CDMRData& data, bool trace)
{ {
FLCO flco = data.getFLCO(); FLCO flco = data.getFLCO();
unsigned int dstId = data.getDstId(); unsigned int dstId = data.getDstId();
@ -44,7 +44,7 @@ bool CRewriteDstId::process(CDMRData& data, bool trace)
if (trace) if (trace)
LogDebug("Rule Trace,\tRewriteDstId from %s Src=%u: not matched", m_name.c_str(), m_fromId); LogDebug("Rule Trace,\tRewriteDstId from %s Src=%u: not matched", m_name.c_str(), m_fromId);
return false; return RESULT_UNMATCHED;
} }
data.setDstId(m_toId); data.setDstId(m_toId);
@ -56,5 +56,5 @@ bool CRewriteDstId::process(CDMRData& data, bool trace)
LogDebug("Rule Trace,\tRewriteDstId to %s Src=%u", m_name.c_str(), m_toId); LogDebug("Rule Trace,\tRewriteDstId to %s Src=%u", m_name.c_str(), m_toId);
} }
return true; return RESULT_MATCHED;
} }

4
RewriteDstId.h
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (C) 2017 by Jonathan Naylor G4KLX * Copyright (C) 2017,2020 by Jonathan Naylor G4KLX
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by * it under the terms of the GNU General Public License as published by
@ -29,7 +29,7 @@ public:
CRewriteDstId(const std::string& name, unsigned int fromId, unsigned int toID); CRewriteDstId(const std::string& name, unsigned int fromId, unsigned int toID);
virtual ~CRewriteDstId(); virtual ~CRewriteDstId();
virtual bool process(CDMRData& data, bool trace); virtual PROCESS_RESULT process(CDMRData& data, bool trace);
private: private:
std::string m_name; std::string m_name;

6
RewriteDynTGNet.cpp
View file

@ -38,7 +38,7 @@ CRewriteDynTGNet::~CRewriteDynTGNet()
{ {
} }
bool CRewriteDynTGNet::process(CDMRData& data, bool trace) PROCESS_RESULT CRewriteDynTGNet::process(CDMRData& data, bool trace)
{ {
FLCO flco = data.getFLCO(); FLCO flco = data.getFLCO();
unsigned int dstId = data.getDstId(); unsigned int dstId = data.getDstId();
@ -48,7 +48,7 @@ bool CRewriteDynTGNet::process(CDMRData& data, bool trace)
if (trace) if (trace)
LogDebug("Rule Trace,\tRewriteDynTGNet from %s Slot=%u Dst=TG%u: not matched", m_name.c_str(), m_slot, m_currentTG); LogDebug("Rule Trace,\tRewriteDynTGNet from %s Slot=%u Dst=TG%u: not matched", m_name.c_str(), m_slot, m_currentTG);
return false; return RESULT_UNMATCHED;
} }
data.setDstId(m_toTG); data.setDstId(m_toTG);
@ -58,7 +58,7 @@ bool CRewriteDynTGNet::process(CDMRData& data, bool trace)
if (trace) if (trace)
LogDebug("Rule Trace,\tRewriteDynTGNet from %s Slot=%u Dst=TG%u: matched", m_name.c_str(), m_slot, m_currentTG); LogDebug("Rule Trace,\tRewriteDynTGNet from %s Slot=%u Dst=TG%u: matched", m_name.c_str(), m_slot, m_currentTG);
return true; return RESULT_MATCHED;
} }
void CRewriteDynTGNet::setCurrentTG(unsigned int currentTG) void CRewriteDynTGNet::setCurrentTG(unsigned int currentTG)

2
RewriteDynTGNet.h
View file

@ -29,7 +29,7 @@ public:
CRewriteDynTGNet(const std::string& name, unsigned int slot, unsigned int toTG); CRewriteDynTGNet(const std::string& name, unsigned int slot, unsigned int toTG);
virtual ~CRewriteDynTGNet(); virtual ~CRewriteDynTGNet();
virtual bool process(CDMRData& data, bool trace); virtual PROCESS_RESULT process(CDMRData& data, bool trace);
void setCurrentTG(unsigned int tg); void setCurrentTG(unsigned int tg);

10
RewriteDynTGRF.cpp
View file

@ -43,7 +43,7 @@ CRewriteDynTGRF::~CRewriteDynTGRF()
{ {
} }
bool CRewriteDynTGRF::process(CDMRData& data, bool trace) PROCESS_RESULT CRewriteDynTGRF::process(CDMRData& data, bool trace)
{ {
FLCO flco = data.getFLCO(); FLCO flco = data.getFLCO();
unsigned int dstId = data.getDstId(); unsigned int dstId = data.getDstId();
@ -57,7 +57,7 @@ bool CRewriteDynTGRF::process(CDMRData& data, bool trace)
if (trace) if (trace)
LogDebug("Rule Trace,\tRewriteDynTGRF from %s Slot=%u Dst=TG%u: matched", m_name.c_str(), m_slot, m_toTG); LogDebug("Rule Trace,\tRewriteDynTGRF from %s Slot=%u Dst=TG%u: matched", m_name.c_str(), m_slot, m_toTG);
return true; return RESULT_MATCHED;
} }
if (flco == FLCO_GROUP && slotNo == m_slot && dstId == m_discTG && m_currentTG != 0U) { if (flco == FLCO_GROUP && slotNo == m_slot && dstId == m_discTG && m_currentTG != 0U) {
@ -67,7 +67,7 @@ bool CRewriteDynTGRF::process(CDMRData& data, bool trace)
m_rewriteNet->setCurrentTG(0U); m_rewriteNet->setCurrentTG(0U);
m_currentTG = 0U; m_currentTG = 0U;
return true; return RESULT_MATCHED;
} }
if (flco == FLCO_GROUP && slotNo == m_slot && dstId >= m_fromTGStart && dstId <= m_fromTGEnd) { if (flco == FLCO_GROUP && slotNo == m_slot && dstId >= m_fromTGStart && dstId <= m_fromTGEnd) {
@ -81,7 +81,7 @@ bool CRewriteDynTGRF::process(CDMRData& data, bool trace)
m_rewriteNet->setCurrentTG(dstId); m_rewriteNet->setCurrentTG(dstId);
m_currentTG = dstId; m_currentTG = dstId;
return true; return RESULT_MATCHED;
} }
if (trace) { if (trace) {
@ -91,5 +91,5 @@ bool CRewriteDynTGRF::process(CDMRData& data, bool trace)
LogDebug("Rule Trace,\tRewriteDynTGRF from %s Slot=%u Dst=TG%u-TG%u or Dst=TG%u or Dst=TG%u: not matched", m_name.c_str(), m_slot, m_fromTGStart, m_fromTGEnd, m_toTG, m_discTG); LogDebug("Rule Trace,\tRewriteDynTGRF from %s Slot=%u Dst=TG%u-TG%u or Dst=TG%u or Dst=TG%u: not matched", m_name.c_str(), m_slot, m_fromTGStart, m_fromTGEnd, m_toTG, m_discTG);
} }
return false; return RESULT_UNMATCHED;
} }

2
RewriteDynTGRF.h
View file

@ -31,7 +31,7 @@ public:
CRewriteDynTGRF(const std::string& name, unsigned int slot, unsigned int fromTG, unsigned int toTG, unsigned int discTG, unsigned int range, CRewriteDynTGNet* rewriteNet); CRewriteDynTGRF(const std::string& name, unsigned int slot, unsigned int fromTG, unsigned int toTG, unsigned int discTG, unsigned int range, CRewriteDynTGNet* rewriteNet);
virtual ~CRewriteDynTGRF(); virtual ~CRewriteDynTGRF();
virtual bool process(CDMRData& data, bool trace); virtual PROCESS_RESULT process(CDMRData& data, bool trace);
private: private:
std::string m_name; std::string m_name;

8
RewritePC.cpp
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (C) 2017 by Jonathan Naylor G4KLX * Copyright (C) 2017,2020 by Jonathan Naylor G4KLX
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by * it under the terms of the GNU General Public License as published by
@ -42,7 +42,7 @@ CRewritePC::~CRewritePC()
{ {
} }
bool CRewritePC::process(CDMRData& data, bool trace) PROCESS_RESULT CRewritePC::process(CDMRData& data, bool trace)
{ {
FLCO flco = data.getFLCO(); FLCO flco = data.getFLCO();
unsigned int dstId = data.getDstId(); unsigned int dstId = data.getDstId();
@ -52,7 +52,7 @@ bool CRewritePC::process(CDMRData& data, bool trace)
if (trace) if (trace)
LogDebug("Rule Trace,\tRewritePC from %s Slot=%u Dst=%u-%u: not matched", m_name.c_str(), m_fromSlot, m_fromIdStart, m_fromIdEnd); LogDebug("Rule Trace,\tRewritePC from %s Slot=%u Dst=%u-%u: not matched", m_name.c_str(), m_fromSlot, m_fromIdStart, m_fromIdEnd);
return false; return RESULT_UNMATCHED;
} }
if (m_fromSlot != m_toSlot) if (m_fromSlot != m_toSlot)
@ -70,5 +70,5 @@ bool CRewritePC::process(CDMRData& data, bool trace)
LogDebug("Rule Trace,\tRewritePC to %s Slot=%u Dst=%u-%u", m_name.c_str(), m_toSlot, m_toIdStart, m_toIdEnd); LogDebug("Rule Trace,\tRewritePC to %s Slot=%u Dst=%u-%u", m_name.c_str(), m_toSlot, m_toIdStart, m_toIdEnd);
} }
return true; return RESULT_MATCHED;
} }

4
RewritePC.h
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (C) 2017 by Jonathan Naylor G4KLX * Copyright (C) 2017,2020 by Jonathan Naylor G4KLX
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by * it under the terms of the GNU General Public License as published by
@ -29,7 +29,7 @@ public:
CRewritePC(const std::string& name, unsigned int fromSlot, unsigned int fromId, unsigned int toSlot, unsigned int toId, unsigned int range); CRewritePC(const std::string& name, unsigned int fromSlot, unsigned int fromId, unsigned int toSlot, unsigned int toId, unsigned int range);
virtual ~CRewritePC(); virtual ~CRewritePC();
virtual bool process(CDMRData& data, bool trace); virtual PROCESS_RESULT process(CDMRData& data, bool trace);
private: private:
std::string m_name; std::string m_name;

8
RewriteSrc.cpp
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (C) 2017 by Jonathan Naylor G4KLX * Copyright (C) 2017,2020 by Jonathan Naylor G4KLX
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by * it under the terms of the GNU General Public License as published by
@ -41,7 +41,7 @@ CRewriteSrc::~CRewriteSrc()
{ {
} }
bool CRewriteSrc::process(CDMRData& data, bool trace) PROCESS_RESULT CRewriteSrc::process(CDMRData& data, bool trace)
{ {
FLCO flco = data.getFLCO(); FLCO flco = data.getFLCO();
unsigned int srcId = data.getSrcId(); unsigned int srcId = data.getSrcId();
@ -51,7 +51,7 @@ bool CRewriteSrc::process(CDMRData& data, bool trace)
if (trace) if (trace)
LogDebug("Rule Trace,\tRewriteSrc from %s Slot=%u Src=%u-%u: not matched", m_name.c_str(), m_fromSlot, m_fromIdStart, m_fromIdEnd); LogDebug("Rule Trace,\tRewriteSrc from %s Slot=%u Src=%u-%u: not matched", m_name.c_str(), m_fromSlot, m_fromIdStart, m_fromIdEnd);
return false; return RESULT_UNMATCHED;
} }
if (m_fromSlot != m_toSlot) if (m_fromSlot != m_toSlot)
@ -67,5 +67,5 @@ bool CRewriteSrc::process(CDMRData& data, bool trace)
LogDebug("Rule Trace,\tRewriteSrc to %s Slot=%u Dst=TG%u", m_name.c_str(), m_toSlot, m_toTG); LogDebug("Rule Trace,\tRewriteSrc to %s Slot=%u Dst=TG%u", m_name.c_str(), m_toSlot, m_toTG);
} }
return true; return RESULT_MATCHED;
} }

4
RewriteSrc.h
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (C) 2017 by Jonathan Naylor G4KLX * Copyright (C) 2017,2020 by Jonathan Naylor G4KLX
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by * it under the terms of the GNU General Public License as published by
@ -29,7 +29,7 @@ public:
CRewriteSrc(const std::string& name, unsigned int fromSlot, unsigned int fromId, unsigned int toSlot, unsigned int toTG, unsigned int range); CRewriteSrc(const std::string& name, unsigned int fromSlot, unsigned int fromId, unsigned int toSlot, unsigned int toTG, unsigned int range);
virtual ~CRewriteSrc(); virtual ~CRewriteSrc();
virtual bool process(CDMRData& data, bool trace); virtual PROCESS_RESULT process(CDMRData& data, bool trace);
private: private:
std::string m_name; std::string m_name;

8
RewriteSrcId.cpp
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (C) 2017 by Jonathan Naylor G4KLX * Copyright (C) 2017,2020 by Jonathan Naylor G4KLX
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by * it under the terms of the GNU General Public License as published by
@ -35,7 +35,7 @@ CRewriteSrcId::~CRewriteSrcId()
{ {
} }
bool CRewriteSrcId::process(CDMRData& data, bool trace) PROCESS_RESULT CRewriteSrcId::process(CDMRData& data, bool trace)
{ {
unsigned int srcId = data.getSrcId(); unsigned int srcId = data.getSrcId();
@ -43,7 +43,7 @@ bool CRewriteSrcId::process(CDMRData& data, bool trace)
if (trace) if (trace)
LogDebug("Rule Trace,\tRewriteSrcId from %s Src=%u: not matched", m_name.c_str(), m_fromId); LogDebug("Rule Trace,\tRewriteSrcId from %s Src=%u: not matched", m_name.c_str(), m_fromId);
return false; return RESULT_UNMATCHED;
} }
data.setSrcId(m_toId); data.setSrcId(m_toId);
@ -55,5 +55,5 @@ bool CRewriteSrcId::process(CDMRData& data, bool trace)
LogDebug("Rule Trace,\tRewriteSrcId to %s Src=%u", m_name.c_str(), m_toId); LogDebug("Rule Trace,\tRewriteSrcId to %s Src=%u", m_name.c_str(), m_toId);
} }
return true; return RESULT_MATCHED;
} }

4
RewriteSrcId.h
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (C) 2017 by Jonathan Naylor G4KLX * Copyright (C) 2017,2020 by Jonathan Naylor G4KLX
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by * it under the terms of the GNU General Public License as published by
@ -29,7 +29,7 @@ public:
CRewriteSrcId(const std::string& name, unsigned int fromId, unsigned int toID); CRewriteSrcId(const std::string& name, unsigned int fromId, unsigned int toID);
virtual ~CRewriteSrcId(); virtual ~CRewriteSrcId();
virtual bool process(CDMRData& data, bool trace); virtual PROCESS_RESULT process(CDMRData& data, bool trace);
private: private:
std::string m_name; std::string m_name;

8
RewriteTG.cpp
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (C) 2017 by Jonathan Naylor G4KLX * Copyright (C) 2017,2020 by Jonathan Naylor G4KLX
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by * it under the terms of the GNU General Public License as published by
@ -42,7 +42,7 @@ CRewriteTG::~CRewriteTG()
{ {
} }
bool CRewriteTG::process(CDMRData& data, bool trace) PROCESS_RESULT CRewriteTG::process(CDMRData& data, bool trace)
{ {
FLCO flco = data.getFLCO(); FLCO flco = data.getFLCO();
unsigned int dstId = data.getDstId(); unsigned int dstId = data.getDstId();
@ -56,7 +56,7 @@ bool CRewriteTG::process(CDMRData& data, bool trace)
LogDebug("Rule Trace,\tRewriteTG from %s Slot=%u Dst=TG%u-TG%u: not matched", m_name.c_str(), m_fromSlot, m_fromTGStart, m_fromTGEnd); LogDebug("Rule Trace,\tRewriteTG from %s Slot=%u Dst=TG%u-TG%u: not matched", m_name.c_str(), m_fromSlot, m_fromTGStart, m_fromTGEnd);
} }
return false; return RESULT_UNMATCHED;
} }
if (m_fromSlot != m_toSlot) if (m_fromSlot != m_toSlot)
@ -81,5 +81,5 @@ bool CRewriteTG::process(CDMRData& data, bool trace)
LogDebug("Rule Trace,\tRewriteTG to %s Slot=%u Dst=TG%u-TG%u", m_name.c_str(), m_toSlot, m_toTGStart, m_toTGEnd); LogDebug("Rule Trace,\tRewriteTG to %s Slot=%u Dst=TG%u-TG%u", m_name.c_str(), m_toSlot, m_toTGStart, m_toTGEnd);
} }
return true; return RESULT_MATCHED;
} }

4
RewriteTG.h
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (C) 2017 by Jonathan Naylor G4KLX * Copyright (C) 2017,2020 by Jonathan Naylor G4KLX
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by * it under the terms of the GNU General Public License as published by
@ -29,7 +29,7 @@ public:
CRewriteTG(const std::string& name, unsigned int fromSlot, unsigned int fromTG, unsigned int toSlot, unsigned int toTG, unsigned int range); CRewriteTG(const std::string& name, unsigned int fromSlot, unsigned int fromTG, unsigned int toSlot, unsigned int toTG, unsigned int range);
virtual ~CRewriteTG(); virtual ~CRewriteTG();
virtual bool process(CDMRData& data, bool trace); virtual PROCESS_RESULT process(CDMRData& data, bool trace);
private: private:
std::string m_name; std::string m_name;

8
RewriteType.cpp
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (C) 2017 by Jonathan Naylor G4KLX * Copyright (C) 2017,2020 by Jonathan Naylor G4KLX
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by * it under the terms of the GNU General Public License as published by
@ -40,7 +40,7 @@ CRewriteType::~CRewriteType()
{ {
} }
bool CRewriteType::process(CDMRData& data, bool trace) PROCESS_RESULT CRewriteType::process(CDMRData& data, bool trace)
{ {
FLCO flco = data.getFLCO(); FLCO flco = data.getFLCO();
unsigned int dstId = data.getDstId(); unsigned int dstId = data.getDstId();
@ -50,7 +50,7 @@ bool CRewriteType::process(CDMRData& data, bool trace)
if (trace) if (trace)
LogDebug("Rule Trace,\tRewriteType %s Slot=%u Dst=TG%u: not matched", m_name.c_str(), m_fromSlot, m_fromTG); LogDebug("Rule Trace,\tRewriteType %s Slot=%u Dst=TG%u: not matched", m_name.c_str(), m_fromSlot, m_fromTG);
return false; return RESULT_UNMATCHED;
} }
if (m_fromSlot != m_toSlot) if (m_fromSlot != m_toSlot)
@ -64,5 +64,5 @@ bool CRewriteType::process(CDMRData& data, bool trace)
if (trace) if (trace)
LogDebug("Rule Trace,\tRewriteType %s Slot=%u Dst=TG%u: matched", m_name.c_str(), m_fromSlot, m_fromTG); LogDebug("Rule Trace,\tRewriteType %s Slot=%u Dst=TG%u: matched", m_name.c_str(), m_fromSlot, m_fromTG);
return true; return RESULT_MATCHED;
} }

4
RewriteType.h
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (C) 2017 by Jonathan Naylor G4KLX * Copyright (C) 2017,2020 by Jonathan Naylor G4KLX
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by * it under the terms of the GNU General Public License as published by
@ -29,7 +29,7 @@ public:
CRewriteType(const std::string& name, unsigned int fromSlot, unsigned int fromTG, unsigned int toSlot, unsigned int toId); CRewriteType(const std::string& name, unsigned int fromSlot, unsigned int fromTG, unsigned int toSlot, unsigned int toId);
virtual ~CRewriteType(); virtual ~CRewriteType();
virtual bool process(CDMRData& data, bool trace); virtual PROCESS_RESULT process(CDMRData& data, bool trace);
private: private:
std::string m_name; std::string m_name;