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Add optional names for each network for use in the log,

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This commit is contained in:
Jonathan Naylor 2017-08-01 21:51:22 +01:00
parent 49254bc7c9
commit 367116bdf4
19 changed files with 175 additions and 89 deletions
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14
RewriteTG.cpp
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@ -25,7 +25,7 @@
#include <cstdio>
#include <cassert>
CRewriteTG::CRewriteTG(const char* name, unsigned int fromSlot, unsigned int fromTG, unsigned int toSlot, unsigned int toTG, unsigned int range) :
CRewriteTG::CRewriteTG(const std::string& name, unsigned int fromSlot, unsigned int fromTG, unsigned int toSlot, unsigned int toTG, unsigned int range) :
m_name(name),
m_fromSlot(fromSlot),
m_fromTGStart(fromTG),
@ -53,9 +53,9 @@ bool CRewriteTG::process(CDMRData& data, bool trace)
if (flco != FLCO_GROUP || slotNo != m_fromSlot || dstId < m_fromTGStart || dstId > m_fromTGEnd) {
if (trace) {
if (m_fromTGStart == m_fromTGEnd)
LogDebug("Rule Trace,\tRewriteTG from %s Slot=%u Dst=TG%u: not matched", m_name, m_fromSlot, m_fromTGStart);
LogDebug("Rule Trace,\tRewriteTG from %s Slot=%u Dst=TG%u: not matched", m_name.c_str(), m_fromSlot, m_fromTGStart);
else
LogDebug("Rule Trace,\tRewriteTG from %s Slot=%u Dst=TG%u-TG%u: not matched", m_name, m_fromSlot, m_fromTGStart, m_fromTGEnd);
LogDebug("Rule Trace,\tRewriteTG from %s Slot=%u Dst=TG%u-TG%u: not matched", m_name.c_str(), m_fromSlot, m_fromTGStart, m_fromTGEnd);
}
return false;
}
@ -89,13 +89,13 @@ bool CRewriteTG::process(CDMRData& data, bool trace)
if (trace) {
if (m_fromTGStart == m_fromTGEnd)
LogDebug("Rule Trace,\tRewriteTG from %s Slot=%u Dst=TG%u: matched", m_name, m_fromSlot, m_fromTGStart);
LogDebug("Rule Trace,\tRewriteTG from %s Slot=%u Dst=TG%u: matched", m_name.c_str(), m_fromSlot, m_fromTGStart);
else
LogDebug("Rule Trace,\tRewriteTG from %s Slot=%u Dst=TG%u-TG%u: matched", m_name, m_fromSlot, m_fromTGStart, m_fromTGEnd);
LogDebug("Rule Trace,\tRewriteTG from %s Slot=%u Dst=TG%u-TG%u: matched", m_name.c_str(), m_fromSlot, m_fromTGStart, m_fromTGEnd);
if (m_toTGStart == m_toTGEnd)
LogDebug("Rule Trace,\tRewriteTG to %s Slot=%u Dst=TG%u", m_name, m_toSlot, m_toTGStart);
LogDebug("Rule Trace,\tRewriteTG to %s Slot=%u Dst=TG%u", m_name.c_str(), m_toSlot, m_toTGStart);
else
LogDebug("Rule Trace,\tRewriteTG to %s Slot=%u Dst=TG%u-TG%u", m_name, m_toSlot, m_toTGStart, m_toTGEnd);
LogDebug("Rule Trace,\tRewriteTG to %s Slot=%u Dst=TG%u-TG%u", m_name.c_str(), m_toSlot, m_toTGStart, m_toTGEnd);
}
return true;