mirror of
https://github.com/g4klx/DMRGateway.git
synced 2025-12-06 05:32:01 +01:00
85 lines
2.6 KiB
C++
85 lines
2.6 KiB
C++
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/*
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* Copyright (C) 2017,2020 by Jonathan Naylor G4KLX
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include "RewriteDynTGNet.h"
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#include "DMRDefines.h"
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#include "Log.h"
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#include <cstdio>
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#include <cassert>
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CRewriteDynTGNet::CRewriteDynTGNet(const std::string& name, unsigned int slot, unsigned int fromTG, unsigned int toTG, unsigned int discTG, unsigned int range) :
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CRewrite(),
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m_name(name),
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m_slot(slot),
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m_fromTGStart(fromTG),
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m_fromTGEnd(fromTG + range - 1U),
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m_toTG(toTG),
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m_discTG(discTG),
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m_currentTG(0U)
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{
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assert(slot == 1U || slot == 2U);
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}
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CRewriteDynTGNet::~CRewriteDynTGNet()
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{
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}
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bool CRewriteDynTGNet::process(CDMRData& data, bool trace)
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{
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FLCO flco = data.getFLCO();
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unsigned int dstId = data.getDstId();
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unsigned int slotNo = data.getSlotNo();
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if (flco != FLCO_GROUP || slotNo != m_fromSlot || dstId < m_fromTGStart || dstId > m_fromTGEnd) {
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if (trace) {
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if (m_fromTGStart == m_fromTGEnd)
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LogDebug("Rule Trace,\tRewriteDynTGNet from %s Slot=%u Dst=TG%u: not matched", m_name.c_str(), m_fromSlot, m_fromTGStart);
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else
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LogDebug("Rule Trace,\tRewriteDynTGNet from %s Slot=%u Dst=TG%u-TG%u: not matched", m_name.c_str(), m_fromSlot, m_fromTGStart, m_fromTGEnd);
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}
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return false;
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}
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if (m_fromSlot != m_toSlot)
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data.setSlotNo(m_toSlot);
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if (m_fromTGStart != m_toTGStart) {
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unsigned int newTG = dstId + m_toTGStart - m_fromTGStart;
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data.setDstId(newTG);
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processMessage(data);
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}
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if (trace) {
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if (m_fromTGStart == m_fromTGEnd)
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LogDebug("Rule Trace,\tRewriteDynTGNet from %s Slot=%u Dst=TG%u: matched", m_name.c_str(), m_fromSlot, m_fromTGStart);
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else
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LogDebug("Rule Trace,\tRewriteDynTGNet from %s Slot=%u Dst=TG%u-TG%u: matched", m_name.c_str(), m_fromSlot, m_fromTGStart, m_fromTGEnd);
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if (m_toTGStart == m_toTGEnd)
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LogDebug("Rule Trace,\tRewriteDynTGNet to %s Slot=%u Dst=TG%u", m_name.c_str(), m_toSlot, m_toTGStart);
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else
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LogDebug("Rule Trace,\tRewriteDynTGNet to %s Slot=%u Dst=TG%u-TG%u", m_name.c_str(), m_toSlot, m_toTGStart, m_toTGEnd);
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}
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return true;
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}
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