mirror of
https://github.com/ayufan/steam-deck-tools.git
synced 2026-04-04 13:57:39 +00:00
Add VangoghGPU SMU controller with CPU and GPU clock frequency control
This commit is contained in:
Kamil Trzciński
parent
9eba0239a1
commit
a3a25bfb4e
11 changed files with 816 additions and 39 deletions
214
PowerControl/Helpers/AMD/RyzenSMU.cs
Normal file
214
PowerControl/Helpers/AMD/RyzenSMU.cs
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@ -0,0 +1,214 @@
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using CommonHelpers;
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using System;
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using System.Collections.Generic;
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using System.Diagnostics;
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using System.Runtime.InteropServices;
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using System.Linq;
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using System.Text;
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using System.Threading.Tasks;
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namespace PowerControl.Helpers.GPU
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{
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public class RyzenSMU : IDisposable
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{
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public IntPtr MMIO_ADDR;
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public uint MMIO_SIZE;
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public uint RES_ADDR, MSG_ADDR, PARAM_ADDR;
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public uint INDEX_ADDR, DATA_ADDR;
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IntPtr mappedAddress;
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IntPtr physicalHandle;
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public RyzenSMU()
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{
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}
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~RyzenSMU()
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{
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Dispose();
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}
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public bool Opened
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{
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get { return physicalHandle != IntPtr.Zero && mappedAddress != IntPtr.Zero; }
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}
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public bool Open()
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{
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if (physicalHandle != IntPtr.Zero)
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return true;
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if (MMIO_ADDR == IntPtr.Zero || MMIO_SIZE == 0)
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return false;
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try
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{
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mappedAddress = InpOut.MapPhysToLin(MMIO_ADDR, MMIO_SIZE, out physicalHandle);
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}
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catch (Exception e)
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{
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TraceLine("RyzenSMU: {0}", e);
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return false;
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}
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return Opened;
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}
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public void Dispose()
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{
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if (physicalHandle == IntPtr.Zero)
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return;
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GC.SuppressFinalize(this);
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InpOut.UnmapPhysicalMemory(physicalHandle, mappedAddress);
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mappedAddress = IntPtr.Zero;
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physicalHandle = IntPtr.Zero;
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}
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private uint RregRaw(uint reg)
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{
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return (uint)Marshal.ReadInt32(mappedAddress, (int)reg);
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}
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private void WregRaw(uint reg, uint value)
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{
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Marshal.WriteInt32(mappedAddress, (int)reg, (int)value);
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}
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private bool WregCheckedRaw(uint reg, uint value)
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{
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WregRaw(reg, value);
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return RregRaw(reg) == value;
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}
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private bool Wreg(uint reg, uint value)
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{
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if (!Opened)
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return false;
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bool success = false;
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try
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{
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if (reg < MMIO_SIZE)
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{
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return success = WregCheckedRaw(reg, value);
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}
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else
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{
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if (!WregCheckedRaw(INDEX_ADDR, reg))
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return false;
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if (!WregCheckedRaw(DATA_ADDR, value))
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return false;
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}
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return success = true;
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}
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finally
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{
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TraceLine("Wreg: reg={0:X}, value={1:X} => success={2}",
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reg, value, success);
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}
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}
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private bool Rreg(uint reg, out uint value)
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{
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value = default;
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if (!Opened)
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return false;
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bool success = false;
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try
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{
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if (reg < MMIO_SIZE)
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{
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value = RregRaw(reg);
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}
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else
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{
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if (!WregCheckedRaw(INDEX_ADDR, reg))
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return false;
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value = RregRaw(DATA_ADDR);
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}
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return success = true;
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}
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finally
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{
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TraceLine("Rreg: reg={0:X} => read={1}/{1:X}, success={2}",
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reg, value, success);
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}
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}
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private uint WaitForResponse()
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{
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const int timeout = 20;
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for (int i = 0; i < timeout; i++)
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{
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uint value;
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if (!Rreg(RES_ADDR, out value))
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return 0;
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if (value != 0)
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return value;
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Thread.SpinWait(100);
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}
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return 0;
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}
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public bool SendMsg(ushort msg, uint param)
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{
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return SendMsg(msg, param, out _);
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}
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public bool SendMsg(ushort msg, uint param, out uint arg)
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{
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bool success = false;
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arg = 0;
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try
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{
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var res = WaitForResponse();
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if (res != 0x1)
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{
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// Reset SMU state
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if (res != 0)
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Wreg(RES_ADDR, 1);
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return false;
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}
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Wreg(RES_ADDR, 0);
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Wreg(PARAM_ADDR, param);
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Wreg(MSG_ADDR, msg);
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res = WaitForResponse();
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if (res != 0x1)
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return false;
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success = Rreg(PARAM_ADDR, out arg);
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return success;
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}
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finally
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{
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TraceLine(">> SendMsg: msg={0:X}, param={1:X} => arg={2}/{2:X}, success={3}",
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msg, param, arg, success);
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}
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}
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public bool SendMsg<T>(T msg, uint param)
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{
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return SendMsg((ushort)(object)msg, param, out _);
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}
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public bool SendMsg<T>(T msg, uint param, out uint arg) where T : unmanaged
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{
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return SendMsg((ushort)(object)msg, param, out arg);
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}
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private static void TraceLine(string format, params object?[]? arg)
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{
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Trace.WriteLine(string.Format(format, arg));
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}
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}
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}
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380
PowerControl/Helpers/AMD/VangoghGPU.cs
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380
PowerControl/Helpers/AMD/VangoghGPU.cs
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@ -0,0 +1,380 @@
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using CommonHelpers;
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using System.Diagnostics;
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namespace PowerControl.Helpers.GPU
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{
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internal class VangoghGPU : IDisposable
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{
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public struct SupportedDevice
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{
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public ushort VendorID, DeviceID;
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public IntPtr MMIOAddress;
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public uint MMIOSize;
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public uint SMUVersion;
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public SupportedDevice(ushort VendorID, ushort DeviceID, uint MMIOAddress, uint MMIOSize, uint SMUVersion)
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{
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this.VendorID = VendorID;
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this.DeviceID = DeviceID;
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this.MMIOAddress = new IntPtr(MMIOAddress);
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this.MMIOSize = MMIOSize;
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this.SMUVersion = SMUVersion;
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}
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private void Log(string format, params object?[]? arg)
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{
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Trace.WriteLine(string.Format("GPU: [{0:X4}:{1:X4}] ", VendorID, DeviceID) + string.Format(format, arg));
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}
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public bool Found()
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{
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// Strong validate device that it has our "memory layout"
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var pciAddress = WinRing0.FindPciDeviceById(VendorID, DeviceID, 0);
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if (pciAddress == WinRing0.NO_DEVICE)
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{
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Log("PCI: not found");
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return false;
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}
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Log("PCI: [{0:X8}]", pciAddress);
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var barAddr = WinRing0.ReadPciConfigDword(pciAddress, 0x24); // BAR6
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if (MMIOAddress != new IntPtr(barAddr))
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{
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Log("PCI: [{0:X8}] => BAR: {1:X8} vs {2:X8} => mismatch",
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pciAddress, MMIOAddress, barAddr);
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return false;
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}
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Log("PCI: [{0:X8}] => BAR: {1:X8} => OK",
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pciAddress, barAddr);
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return true;
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}
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public VangoghGPU? Open()
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{
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var gpu = VangoghGPU.OpenMMIO(MMIOAddress, MMIOSize);
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if (gpu == null)
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return null;
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// Check supported SMU version
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var smuVersion = gpu.SMUVersion;
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if (smuVersion != SMUVersion)
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{
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Log("SMU: {0:X8} => not supported", smuVersion);
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return null;
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}
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Log("SMU: {0:X8} => detected", smuVersion);
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return gpu;
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}
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};
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public static readonly SupportedDevice[] SupportedDevices = new SupportedDevice[]
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{
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// SteamDeck
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new SupportedDevice(0x1002, 0x163F, 0x80300000, 0x80380000 - 0x80300000, 0x43F3900)
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};
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private static SupportedDevice? DetectedDevice;
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public static bool IsSupported
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{
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get { return DetectedDevice != null; }
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}
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public static VangoghGPU? Open()
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{
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return DetectedDevice?.Open();
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}
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public static bool Detect()
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{
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foreach ( var device in SupportedDevices)
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{
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if (!device.Found())
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continue;
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using (var gpu = device.Open())
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{
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if (gpu is not null)
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{
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DetectedDevice = device;
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return true;
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}
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}
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}
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DetectedDevice = null;
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return false;
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}
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// Addresses:
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// drivers/gpu/drm/amd/include/vangogh_ip_offset.h => MP1_BASE => 0x00016000
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// drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c => mmMP1_SMN_C2PMSG_* => 0x0282/0x0292/0x029a
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// drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_offset.h => mmPCIE_INDEX2/mmPCIE_DATA2 => 0x000e/0x000f
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//
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// Messages:
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// drivers/gpu/drm/amd/pm/inc/smu_v11_5_ppsmc.h
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private RyzenSMU smu;
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~VangoghGPU()
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{
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Dispose();
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}
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public void Dispose()
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{
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GC.SuppressFinalize(this);
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if (smu != null)
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smu.Dispose();
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}
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private static VangoghGPU? OpenMMIO(IntPtr mmioAddress, uint mmioSize)
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{
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var gpu = new VangoghGPU
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{
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smu = new RyzenSMU()
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{
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MMIO_ADDR = mmioAddress,
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MMIO_SIZE = mmioSize,
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RES_ADDR = 0x0001629A * 4,
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MSG_ADDR = 0x00016282 * 4,
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PARAM_ADDR = 0x00016292 * 4,
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INDEX_ADDR = 0xE * 4,
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DATA_ADDR = 0xF * 4
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}
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};
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if (!gpu.smu.Open())
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return null;
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return gpu;
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}
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public UInt32 SMUVersion
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{
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get { return getValue(Message.PPSMC_MSG_GetSmuVersion); }
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}
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public UInt32 IfVersion
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{
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get { return getValue(Message.PPSMC_MSG_GetDriverIfVersion); }
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}
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const uint MIN_TDP = 3000;
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const uint MAX_TDP = 15000;
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public uint SlowTDP
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{
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get { return getValue(Message.PPSMC_MSG_GetSlowPPTLimit); }
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set { setValue(Message.PPSMC_MSG_SetSlowPPTLimit, value, MIN_TDP, MAX_TDP); }
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}
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public uint FastTDP
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{
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get { return getValue(Message.PPSMC_MSG_GetFastPPTLimit); }
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set { setValue(Message.PPSMC_MSG_SetFastPPTLimit, value, MIN_TDP, MAX_TDP); }
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}
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public uint GfxClock
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{
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get { return getValue(Message.PPSMC_MSG_GetGfxclkFrequency); }
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}
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public uint FClock
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{
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get { return getValue(Message.PPSMC_MSG_GetFclkFrequency); }
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}
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const uint MIN_CPU_CLOCK = 800;
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const uint MAX_CPU_CLOCK = 3500;
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public uint MinCPUClock
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{
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set { setValue(Message.PPSMC_MSG_SetSoftMinCclk, value, MIN_CPU_CLOCK, MAX_CPU_CLOCK); }
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}
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public uint MaxCPUClock
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{
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set { setValue(Message.PPSMC_MSG_SetSoftMaxCclk, value, MIN_CPU_CLOCK, MAX_CPU_CLOCK); }
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}
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const uint MIN_GFX_CLOCK = 200;
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const uint MAX_GFX_CLOCK = 1600;
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public uint HardMinGfxClock
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{
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set { setValue(Message.PPSMC_MSG_SetHardMinGfxClk, value, MIN_GFX_CLOCK, MAX_GFX_CLOCK); }
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}
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public uint SoftMinGfxClock
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{
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set { setValue(Message.PPSMC_MSG_SetSoftMinGfxclk, value, MIN_GFX_CLOCK, MAX_GFX_CLOCK); }
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}
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public uint SoftMaxGfxClock
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{
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set { setValue(Message.PPSMC_MSG_SetSoftMaxGfxClk, value, MIN_GFX_CLOCK, MAX_GFX_CLOCK); }
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}
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public Dictionary<string, uint> All
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{
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get
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{
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var dict = new Dictionary<string, uint>();
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foreach(var key in ValuesGetters)
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{
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if (!this.smu.SendMsg(key, 0, out var value))
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continue;
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var keyString = key.ToString().Replace("PPSMC_MSG_Get", "");
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dict[keyString] = value;
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}
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return dict;
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}
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}
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private uint getValue(Message msg)
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{
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this.smu.SendMsg(msg, 0, out var value);
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return value;
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}
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private void setValue(Message msg, uint value, uint min = UInt32.MinValue, uint max = UInt32.MaxValue)
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{
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this.smu.SendMsg(msg, Math.Clamp(value, min, max));
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}
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private readonly Message[] ValuesGetters = new Message[]
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{
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Message.PPSMC_MSG_GetGfxclkFrequency,
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Message.PPSMC_MSG_GetFclkFrequency,
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Message.PPSMC_MSG_GetPptLimit,
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Message.PPSMC_MSG_GetThermalLimit,
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Message.PPSMC_MSG_GetFastPPTLimit,
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Message.PPSMC_MSG_GetSlowPPTLimit,
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// Those values return PPSMC_Result_CmdRejectedPrereq
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Message.PPSMC_MSG_GetCurrentTemperature,
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Message.PPSMC_MSG_GetCurrentPower,
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Message.PPSMC_MSG_GetCurrentCurrent,
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Message.PPSMC_MSG_GetCurrentFreq,
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Message.PPSMC_MSG_GetCurrentVoltage,
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Message.PPSMC_MSG_GetAverageCpuActivity,
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Message.PPSMC_MSG_GetAverageGfxActivity,
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Message.PPSMC_MSG_GetAveragePower,
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Message.PPSMC_MSG_GetAverageTemperature
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};
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enum Result : byte
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{
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PPSMC_Result_OK = 0x1,
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PPSMC_Result_Failed = 0xFF,
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PPSMC_Result_UnknownCmd = 0xFE,
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PPSMC_Result_CmdRejectedPrereq = 0xFD,
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PPSMC_Result_CmdRejectedBusy = 0xFC
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}
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enum Tables : byte
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{
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TABLE_BIOS_IF = 0, // Called by BIOS
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TABLE_WATERMARKS = 1, // Called by DAL through VBIOS
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TABLE_CUSTOM_DPM = 2, // Called by Driver
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TABLE_SPARE1 = 3,
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TABLE_DPMCLOCKS = 4, // Called by Driver
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TABLE_SPARE2 = 5, // Called by Tools
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TABLE_MODERN_STDBY = 6, // Called by Tools for Modern Standby Log
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TABLE_SMU_METRICS = 7, // Called by Driver
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TABLE_COUNT = 8
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}
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enum Message : ushort
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{
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PPSMC_MSG_TestMessage = 0x1,
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PPSMC_MSG_GetSmuVersion = 0x2,
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PPSMC_MSG_GetDriverIfVersion = 0x3,
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PPSMC_MSG_EnableGfxOff = 0x4,
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PPSMC_MSG_DisableGfxOff = 0x5,
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PPSMC_MSG_PowerDownIspByTile = 0x6, // ISP is power gated by default
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PPSMC_MSG_PowerUpIspByTile = 0x7,
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PPSMC_MSG_PowerDownVcn = 0x8, // VCN is power gated by default
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PPSMC_MSG_PowerUpVcn = 0x9,
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PPSMC_MSG_RlcPowerNotify = 0xA,
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PPSMC_MSG_SetHardMinVcn = 0xB, // For wireless display
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PPSMC_MSG_SetSoftMinGfxclk = 0xC, //Sets SoftMin for GFXCLK. Arg is in MHz
|
||||
PPSMC_MSG_ActiveProcessNotify = 0xD,
|
||||
PPSMC_MSG_SetHardMinIspiclkByFreq = 0xE,
|
||||
PPSMC_MSG_SetHardMinIspxclkByFreq = 0xF,
|
||||
PPSMC_MSG_SetDriverDramAddrHigh = 0x10,
|
||||
PPSMC_MSG_SetDriverDramAddrLow = 0x11,
|
||||
PPSMC_MSG_TransferTableSmu2Dram = 0x12,
|
||||
PPSMC_MSG_TransferTableDram2Smu = 0x13,
|
||||
PPSMC_MSG_GfxDeviceDriverReset = 0x14, //mode 2 reset during TDR
|
||||
PPSMC_MSG_GetEnabledSmuFeatures = 0x15,
|
||||
PPSMC_MSG_spare1 = 0x16,
|
||||
PPSMC_MSG_SetHardMinSocclkByFreq = 0x17,
|
||||
PPSMC_MSG_SetSoftMinFclk = 0x18, //Used to be PPSMC_MSG_SetMinVideoFclkFreq
|
||||
PPSMC_MSG_SetSoftMinVcn = 0x19,
|
||||
PPSMC_MSG_EnablePostCode = 0x1A,
|
||||
PPSMC_MSG_GetGfxclkFrequency = 0x1B,
|
||||
PPSMC_MSG_GetFclkFrequency = 0x1C,
|
||||
PPSMC_MSG_AllowGfxOff = 0x1D,
|
||||
PPSMC_MSG_DisallowGfxOff = 0x1E,
|
||||
PPSMC_MSG_SetSoftMaxGfxClk = 0x1F,
|
||||
PPSMC_MSG_SetHardMinGfxClk = 0x20,
|
||||
PPSMC_MSG_SetSoftMaxSocclkByFreq = 0x21,
|
||||
PPSMC_MSG_SetSoftMaxFclkByFreq = 0x22,
|
||||
PPSMC_MSG_SetSoftMaxVcn = 0x23,
|
||||
PPSMC_MSG_spare2 = 0x24,
|
||||
PPSMC_MSG_SetPowerLimitPercentage = 0x25,
|
||||
PPSMC_MSG_PowerDownJpeg = 0x26,
|
||||
PPSMC_MSG_PowerUpJpeg = 0x27,
|
||||
PPSMC_MSG_SetHardMinFclkByFreq = 0x28,
|
||||
PPSMC_MSG_SetSoftMinSocclkByFreq = 0x29,
|
||||
PPSMC_MSG_PowerUpCvip = 0x2A,
|
||||
PPSMC_MSG_PowerDownCvip = 0x2B,
|
||||
PPSMC_MSG_GetPptLimit = 0x2C,
|
||||
PPSMC_MSG_GetThermalLimit = 0x2D,
|
||||
PPSMC_MSG_GetCurrentTemperature = 0x2E,
|
||||
PPSMC_MSG_GetCurrentPower = 0x2F,
|
||||
PPSMC_MSG_GetCurrentVoltage = 0x30,
|
||||
PPSMC_MSG_GetCurrentCurrent = 0x31,
|
||||
PPSMC_MSG_GetAverageCpuActivity = 0x32,
|
||||
PPSMC_MSG_GetAverageGfxActivity = 0x33,
|
||||
PPSMC_MSG_GetAveragePower = 0x34,
|
||||
PPSMC_MSG_GetAverageTemperature = 0x35,
|
||||
PPSMC_MSG_SetAveragePowerTimeConstant = 0x36,
|
||||
PPSMC_MSG_SetAverageActivityTimeConstant = 0x37,
|
||||
PPSMC_MSG_SetAverageTemperatureTimeConstant = 0x38,
|
||||
PPSMC_MSG_SetMitigationEndHysteresis = 0x39,
|
||||
PPSMC_MSG_GetCurrentFreq = 0x3A,
|
||||
PPSMC_MSG_SetReducedPptLimit = 0x3B,
|
||||
PPSMC_MSG_SetReducedThermalLimit = 0x3C,
|
||||
PPSMC_MSG_DramLogSetDramAddr = 0x3D,
|
||||
PPSMC_MSG_StartDramLogging = 0x3E,
|
||||
PPSMC_MSG_StopDramLogging = 0x3F,
|
||||
PPSMC_MSG_SetSoftMinCclk = 0x40,
|
||||
PPSMC_MSG_SetSoftMaxCclk = 0x41,
|
||||
PPSMC_MSG_SetDfPstateActiveLevel = 0x42,
|
||||
PPSMC_MSG_SetDfPstateSoftMinLevel = 0x43,
|
||||
PPSMC_MSG_SetCclkPolicy = 0x44,
|
||||
PPSMC_MSG_DramLogSetDramAddrHigh = 0x45,
|
||||
PPSMC_MSG_DramLogSetDramBufferSize = 0x46,
|
||||
PPSMC_MSG_RequestActiveWgp = 0x47,
|
||||
PPSMC_MSG_QueryActiveWgp = 0x48,
|
||||
PPSMC_MSG_SetFastPPTLimit = 0x49,
|
||||
PPSMC_MSG_SetSlowPPTLimit = 0x4A,
|
||||
PPSMC_MSG_GetFastPPTLimit = 0x4B,
|
||||
PPSMC_MSG_GetSlowPPTLimit = 0x4C,
|
||||
PPSMC_Message_Count = 0x4D,
|
||||
}
|
||||
private static void TraceLine(string format, params object?[]? arg)
|
||||
{
|
||||
Trace.WriteLine(string.Format(format, arg));
|
||||
}
|
||||
}
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue