Commit graph

121 commits

Author SHA1 Message Date
kd-11 ed82288c1b rsx/fp: Support more types of texture access
- Allows more instructions to correctly decode depth textures
2020-05-13 22:20:43 +03:00
kd-11 b6e8560532 rsx/fp: Fix PK2/UP2 instruction
- These variants take unsigned scalar inputs, not signed.
- Fixes ARGB8->X16Y16 in SR: Gat out of Hell
2020-05-11 09:37:00 +01:00
scribam f37adc4188 Add fallthrough attribute 2020-04-14 17:06:58 +03:00
kd-11 0b6e2b26fa rsx: Fix DST instruction
- It's the old-school distance vector, not the more modern distance() function
- There is seemingly no glsl function that maps to it directly.
2020-04-05 16:35:20 +03:00
Nekotekina 7a8772dafa Replace std::string::npos with umax 2020-03-05 14:05:23 +03:00
Nekotekina 972e0ab31d Remove -Wno-reorder and make it an error 2020-02-21 15:20:34 +03:00
Megamouse fe75311be2 move config structs to own files and clean up some headers 2020-02-17 15:08:17 +03:00
Nekotekina 15391f45d0 Modernize RSX logging (rsx_log variable) 2020-02-01 11:52:22 +03:00
Nekotekina 377e7d2a73 C-style cast cleanup VI 2019-12-04 17:56:22 +03:00
kd-11 2408922806 rsx: Do not ignore clamping for some routines that do not have implied range 2019-11-18 13:17:00 +03:00
kd-11 7072489a6e rsx: Implement point sprite coordinate generation
- When the point sprite flag is set, overrides the input similar to the
2D mask. The returned X and Y values are always the gl_PointCoord values
for the fragment.
- Stacks with the 2D mask to override the z and w coordinates.
2019-11-09 12:50:53 +03:00
kd-11 e04b6cd7c0 rsx: Copypasta fix
- r1 is always float4 never half4. Its a full-width register unlike the
other outputs which are optionally half-width.
2019-10-23 00:50:24 +03:00
kd-11 0b2f9f0f17 rsx: Add support for delayed shader discard.
- Noticed a glitch on AMD hw and windows drivers where discard seems to affect entire 4x4 cells.
- Dead fragments (outside the primitive boundary) could have their discards trigger as they do not have proper access to variables.
- This introduces dead fragments along triangle edges, causing a diagonal line pattern across the screen that is very annoying.
2019-10-22 13:44:49 +03:00
kd-11 0ee9d7b46d rsx/fp: Warnings cleanup 2019-09-01 18:59:50 +03:00
kd-11 eed32cf3a4 rsx: Decompiler fixups and improvements
- Fix 2D coordinate sampling of W coordinate.
  W is actually HPOS.w and not 1. Z is however always 0.
- Optimize register usage a bit
  Disassembling compiled SPV shows that global declaration results in less ops than using inout modifiers. Modifiers generate extra mov instructions.
2019-08-26 20:03:31 +03:00
kd-11 3e28e4b1e0 rsx/decompiler: Restructure program register behavior
- Fix reading of varying registers in FP
  Different registers have different behavior
- Always write to varying registers. If a register is not written to, it is initialized to (0, 0, 0, 1)
- Reimplements two-sided lighting correctly without hacks
- Also bumps shader cache version
2019-08-26 20:03:31 +03:00
kd-11 fe6ff8622a rsx: Decompiler fixups for conditional execution
- Cond actually obeys vector mask
2019-08-26 20:03:31 +03:00
kd-11 67dac94704 rsx/fp: Zero-initialize FragDepth register to match hw 2019-08-21 21:17:15 +03:00
kd-11 c9501b60ab rsx: Use explicit fma for MAD emulation 2019-06-25 20:50:54 +03:00
kd-11 c655036920 rsx/fp: Ease pressure on fragment shaders when emulating clamp16
- TODO: Option to completely skip clamping in some architectures as it is not needed in most games
- Mostly affects older GPUs that do not have access to native fp16
2019-06-14 16:19:52 +03:00
scribam 8f2647555a rsx: Apply Clang-Tidy fix "readability-redundant-string-init" 2019-06-12 15:11:52 +03:00
scribam db926ee671 rsx: Apply Clang-Tidy fix "performance-unnecessary-value-param" 2019-06-12 15:11:52 +03:00
Nekotekina dfd50d0185 Implement std::bit_cast<>
Partial implementation of std::bit_cast from C++20.
Also fix most strict-aliasing rule break warnings (gcc).
2019-06-02 23:22:16 +03:00
scribam 6c5ea068c9 Remove redundant semicolons
Fix "-Wextra-semi" warnings
2019-05-12 18:32:11 +03:00
kd-11 3cbccdd760 rsx: Fragment shader decompiler cleanup
TODO: Investigate the _s input modifier behaviour further, in case it can avoid generating zeroes from a MAD instruction.
x = MAD(+ve, -ve, -ve) with _s input modifier in BFBC expects result to be Non-zero
2019-04-25 16:23:05 +03:00
kd-11 4cd1c25729 "rsx: Ignore argument sign for SQRT operations" 2019-04-25 16:23:05 +03:00
kd-11 32396ba366 rsx: Simplify use of some mixed input functions using OPFLAGS to avoid implicit conversions 2019-04-25 16:23:05 +03:00
kd-11 f12bd8068c rsx: Fragment decompiler fixups
- Properly test for NaN and Inf when clamping down to fp16
- Optimize divsq a bit; mix(vec, vec, bvec) emits OpSelect which is what
we want here, instead of component-wise selection which is much slower.
2019-04-25 16:23:05 +03:00
kd-11 abe7188acf rsx: Proper workaround for broken DIVSQ instruction on realhw
- While mul(0, nan) = nan and 0 / 0 = nan, 0 / sqrt(0) = 0 because of hw
gremlins. normalize(0) is also nan so this behaviour does not work
around that particular case either which makes it even more baffling.
2019-04-25 16:23:05 +03:00
kd-11 60f3059d22 rsx: Compensate for nvidia's low precision attribute interpolation
- The hw generates inaccurate values when doing perspective-correct
  interpolation of vertex output attributes and makes the comparison (a ==
  b) fail even when they are a fixed constant value.
- Increase equality tolerance when doing comparisons in fragment
  shaders for NV cards only to work around this issue.
- Teepo fix
2019-04-25 16:23:05 +03:00
kd-11 463b1b220d rsx: Improve accuracy of shadow compare Ops when non-integer depth formats are used
- The fixed-point D24S8 format does special Z clamping during compare which matches PS3 behaviour
- D32S8 is a floating point format and comparison with Dref > 1 always fails causing black edges/borders
2019-04-25 16:23:05 +03:00
kd-11 06a85f00d1 rsx: Shader decompiler cleanup and improvements
- Improve support for float16_t by minimizing mixed inputs to functions
(ambiguous overloads)
- Minimize amount of downcasts in code by using opcode flags
- Re-enable float16_t support for vulkan
2019-04-25 16:23:05 +03:00
kd-11 a668560c68 rsx: Use native half float types if available
- Emulating f16 with f32 is not ideal and requires a lot of value clamping
- Using native data type can significantly improve performance and accuracy
- With openGL, check for the compatible extensions NV_gpu_shader5 and
AMD_gpu_shader_half_float
- With Vulkan, enable this functionality in the deviceFeatures if
applicable. (VK_KHR_shader_float16_int8 extension)
- Temporarily disable hw fp16 for vulkan
2019-04-25 16:23:05 +03:00
kd-11 ee319f7c13 rsx: Implement strict clamp16 operation needed for NVIDIA cards 2019-04-25 16:23:05 +03:00
kd-11 736415fcd9 rsx/fp: Detect broken/NOP shaders automatically
- Do not compile body if the shader is of no consequence, leave as a passthrough shader
2019-01-25 14:34:22 +03:00
kd-11 4b79ef1ad9 rsx: Implement stencil mirror views
- Implements a mirror view of D24S8 data that accesses the stencil components.
  Finishes the implementation of TEX2D_DEPTH_RGBA as the stencil component was previously missing from the reconstructed data
- Add a few missing destructors
  Image classes are inherited a lot and I forgot to make the dtors virtual
2018-12-24 09:05:19 +03:00
kd-11 696b91cb9b rsx: Reimplement conditional execution in shaders
- Per-channel conditional execution introduces RAW hazards all over the place
- Its cheaper to process both branches and select between the two
- Also improves ShaderVariable functionality to allow functionality such as match_size and taking complex variables as inputs
2018-12-24 09:05:19 +03:00
scribam d7bb59cd99 c++17: use std::size 2018-09-06 13:15:59 +03:00
Nekotekina ce4c4696dd Try to get rid of SIZE_32 macro 2018-09-03 21:40:36 +03:00
kd-11 dea5193fd7 rsx: Fix FP temp register count 2018-09-03 21:39:18 +03:00
eladash f349695a75 Rsx: rewrite address translation 2018-08-13 16:16:34 +03:00
scribam 04ad49de4d typos 2018-05-14 21:14:39 +04:00
kd-11 9fc1740608 rsx/fp: Fragment program overhaul
- Separate TXB from TXL: They are completely different!
- Properly perform TMU emulation in the fragment shader. Implemens SRGB conversion and alphakill at the moment
- Properly perform ROP emulation in the fragment shader. Implements FRAMEBUFFER_SRGB. While support on the chip looks to be incomplete (and wierd), it does work
- Document some more bits in SHADER_CONTROL register
2018-03-25 13:31:06 +03:00
kd-11 27552891ad rsx/fp: Improvements
- Export some debug information in the free texture register space components zw
  Very useful when analysing renderdoc captures
- Enable shadow comparison on depth as long as compare function is active and texture is uploaded for depth read
  Some engines (UE3) read all the components in the shader and use mul/mad with the result
2018-03-25 13:31:06 +03:00
kd-11 d41b49d8b4 rsx/fp: Color output registers are always present and zero initialized
- According to NV_fragment_program spec, registers are zero initialized always
- A program even without writing to these registers will have black (0, 0, 0, 0) output
  Confirmed behaviour with MotorStorm games. Their engine uses this quirk to clear color buffers when doing depth replace
  Might be an unfixed game bug
2018-03-13 18:55:03 +03:00
kd-11 68b3229756 rsx/fp: Improve rgister component gather detection
- Also avoids clobbering register data by keeping gathered bits in a temp var
2018-03-13 18:55:03 +03:00
kd-11 a64bea1286 rsx/fp: Discard shaders with undefined (non-existent) writes. On nvidia+vulkan, undefined writes autofill with blue color 2018-02-16 16:14:54 +03:00
kd-11 89c548b5d3 rsx: fbo fixes 2.5
- Implement flush-always behaviour to partially fix readback from a currently bound fbo
  - Without this, only the first read is correct, as more draws are added the results become 'wrong'
  - Fixes WCB and cpublit behviour
- Synchronize blit_dst surfaces to avoid data loss when gpu texture scaling is used
  - Its still faster in such cases to disable gpu texture scaling but some types cannot be disabled without force cpu blit (e.g framebuffer transfers)
- Memory management tuning
  - rsx: on-demand texture cache rescanning for unprotected sections
  - rsx: Only framebuffer resources are upscaled
  - Do not resize regular blit engine resources
  - Lazy initialize readback buffer when using opengl
  -- These measures should help minimize vram usage
2018-02-16 16:14:54 +03:00
kd-11 33bcdd476c glsl/fp/vp: Avoid shader clutter
- Do not add unused subroutines in shaders unless necessary
-- makes shaders easier to read and disassembled spir-v has less clutter
- glsl: Replace switch block with lookup table
2018-01-30 21:16:43 +03:00
kd-11 648fc92184 rsx/fp/vp: Epsilon value is too large!
- Original epsilon value was 1.E-10 which nvidia linux driver could not read properly
-- Restores the original value represented in decimal notation
2018-01-30 21:16:43 +03:00