From 4ee9c60f6963ed871510836fbedfb31b305fbde2 Mon Sep 17 00:00:00 2001
From: DH <dh.rpcs3@gmail.com>
Date: Thu, 4 Jan 2024 03:54:47 +0300
Subject: [PATCH] [rpcsx-gpu] do not use spirv cross in release builds

---
 hw/amdgpu/device/include/amdgpu/device/device.hpp |  6 +++---
 hw/amdgpu/device/src/device.cpp                   | 14 +++++++++++---
 2 files changed, 14 insertions(+), 6 deletions(-)

diff --git a/hw/amdgpu/device/include/amdgpu/device/device.hpp b/hw/amdgpu/device/include/amdgpu/device/device.hpp
index d5d42695b..773fc561c 100644
--- a/hw/amdgpu/device/include/amdgpu/device/device.hpp
+++ b/hw/amdgpu/device/include/amdgpu/device/device.hpp
@@ -813,7 +813,7 @@ enum Opcodes {
   kOpcodeALU_VS_CONST_UPDATE = 0x4F,
   kOpcodeDMA_DATA = 0x50,
   kOpcodeONE_REG_WRITE = 0x57,
-  kOpcodeAQUIRE_MEM = 0x58,
+  kOpcodeACQUIRE_MEM = 0x58,
   kOpcodeREWIND = 0x59,
   kOpcodeLOAD_UCONFIG_REG = 0x5E,
   kOpcodeLOAD_SH_REG = 0x5F,
@@ -955,8 +955,8 @@ inline const std::string opcodeToString(int op) {
     return "IT_DMA_DATA";
   case kOpcodeONE_REG_WRITE:
     return "IT_ONE_REG_WRITE";
-  case kOpcodeAQUIRE_MEM:
-    return "IT_AQUIRE_MEM";
+  case kOpcodeACQUIRE_MEM:
+    return "IT_ACQUIRE_MEM";
   case kOpcodeREWIND:
     return "IT_REWIND";
   case kOpcodeLOAD_UCONFIG_REG:
diff --git a/hw/amdgpu/device/src/device.cpp b/hw/amdgpu/device/src/device.cpp
index bb7e3b435..30da33325 100644
--- a/hw/amdgpu/device/src/device.cpp
+++ b/hw/amdgpu/device/src/device.cpp
@@ -28,7 +28,6 @@
 #include <set>
 #include <shaders/rect_list.geom.h>
 #include <span>
-#include <spirv_cross/spirv_glsl.hpp>
 #include <string>
 #include <sys/mman.h>
 #include <sys/stat.h>
@@ -37,6 +36,10 @@
 #include <utility>
 #include <vulkan/vulkan_core.h>
 
+#ifndef NDEBUG
+#include <spirv_cross/spirv_glsl.hpp>
+#endif
+
 using namespace amdgpu;
 using namespace amdgpu::device;
 
@@ -1715,6 +1718,7 @@ static bool validateSpirv(const std::vector<uint32_t> &bin) {
 }
 
 static void printSpirv(const std::vector<uint32_t> &bin) {
+#ifndef NDEBUG
   spv_target_env target_env = SPV_ENV_VULKAN_1_3;
   spv_context spvContext = spvContextCreate(target_env);
   spv_diagnostic diagnostic = nullptr;
@@ -1745,6 +1749,7 @@ static void printSpirv(const std::vector<uint32_t> &bin) {
   options.vulkan_semantics = true;
   glsl.set_common_options(options);
   std::printf("%s\n", glsl.compile().c_str());
+#endif
 }
 
 static std::optional<std::vector<uint32_t>>
@@ -4415,7 +4420,9 @@ static void handleRELEASE_MEM(TaskChain &waitTaskSet, QueueRegisters &regs,
 }
 
 static void handleEVENT_WRITE(TaskChain &waitTaskSet, QueueRegisters &regs,
-                              std::span<std::uint32_t> packet) {}
+                              std::span<std::uint32_t> packet) {
+  // std::printf("event write\n");
+}
 
 static void handleINDIRECT_BUFFER_3F(TaskChain &waitTaskSet,
                                      QueueRegisters &regs,
@@ -4564,7 +4571,7 @@ static auto g_commandHandlers = [] {
   handlers[kOpcodeEVENT_WRITE_EOS] = handleEVENT_WRITE_EOS;
   handlers[kOpcodeRELEASE_MEM] = handleRELEASE_MEM;
   handlers[kOpcodeDMA_DATA] = handleDMA_DATA;
-  handlers[kOpcodeAQUIRE_MEM] = handleAQUIRE_MEM;
+  handlers[kOpcodeACQUIRE_MEM] = handleAQUIRE_MEM;
 
   handlers[kOpcodeSET_CONTEXT_REG] = handleSET_CONTEXT_REG;
   handlers[kOpcodeSET_SH_REG] = handleSET_SH_REG;
@@ -4588,6 +4595,7 @@ static void handleCommandBuffer(TaskChain &waitTaskSet, QueueRegisters &regs,
       // auto shaderType = getBit(cmd, 1);
       auto op = getBits(cmd, 15, 8);
       auto len = getBits(cmd, 29, 16) + 2;
+      // std::printf("cmd: %s:%x, %x, %x\n", opcodeToString(op).c_str(), len, predicate, shaderType);
 
       g_commandHandlers[op](waitTaskSet, regs, packets.subspan(0, len));
       packets = packets.subspan(len);